# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Display Clock & Reset Controller for Qualcomm Eliza SoC

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Konrad Dybcio <konradybcio@kernel.org>
  - Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

description: |
  Display clock control module provides the clocks, resets and power
  domains on Qualcomm Eliza SoC platform.

  See also:
  - include/dt-bindings/clock/qcom,eliza-dispcc.h

properties:
  compatible:
    enum:
      - qcom,eliza-dispcc

  clocks:
    items:
      - description: Board XO source
      - description: Board Always On XO source
      - description: Display's AHB clock
      - description: sleep clock
      - description: Byte clock from DSI PHY0
      - description: Pixel clock from DSI PHY0
      - description: Byte clock from DSI PHY1
      - description: Pixel clock from DSI PHY1
      - description: Link clock from DP PHY0
      - description: VCO DIV clock from DP PHY0
      - description: Link clock from DP PHY1
      - description: VCO DIV clock from DP PHY1
      - description: Link clock from DP PHY2
      - description: VCO DIV clock from DP PHY2
      - description: Link clock from DP PHY3
      - description: VCO DIV clock from DP PHY3
      - description: HDMI link clock from HDMI PHY

  power-domains:
    maxItems: 1

  required-opps:
    maxItems: 1

required:
  - compatible
  - clocks
  - '#power-domain-cells'

allOf:
  - $ref: qcom,gcc.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
    #include <dt-bindings/clock/qcom,eliza-gcc.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    #include <dt-bindings/power/qcom,rpmhpd.h>
    clock-controller@af00000 {
        compatible = "qcom,eliza-dispcc";
        reg = <0x0af00000 0x20000>;
        clocks = <&bi_tcxo_div2>,
                 <&bi_tcxo_ao_div2>,
                 <&gcc GCC_DISP_AHB_CLK>,
                 <&sleep_clk>,
                 <&dsi0_phy DSI_BYTE_PLL_CLK>,
                 <&dsi0_phy DSI_PIXEL_PLL_CLK>,
                 <&dsi1_phy DSI_BYTE_PLL_CLK>,
                 <&dsi1_phy DSI_PIXEL_PLL_CLK>,
                 <&dp0_phy 0>,
                 <&dp0_phy 1>,
                 <&dp1_phy 0>,
                 <&dp1_phy 1>,
                 <&dp2_phy 0>,
                 <&dp2_phy 1>,
                 <&dp3_phy 0>,
                 <&dp3_phy 1>,
                 <&hdmi_phy>;

        #clock-cells = <1>;
        #power-domain-cells = <1>;
        #reset-cells = <1>;

        power-domains = <&rpmhpd RPMHPD_MMCX>;
        required-opps = <&rpmhpd_opp_low_svs>;
    };
...