From 42fc4263ec0e35ba6a5ac7c32956e25b4551c907 Mon Sep 17 00:00:00 2001 From: Alexey Kardashevskiy Date: Mon, 26 Feb 2024 17:01:34 +1100 Subject: ls-ecaps: Add decode support for IDE Extended Capability IDE (Integrity & Data Encryption) Extended Capability defined in [1] implements control of the PCI link encryption. The verbose level > 2 prints offsets of the fields to make running setpci easier. The example output is: Capabilities: [830 v1] Integrity & Data Encryption IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+ IDECtl: FTEn- SelectiveIDE#0 Cap: RID#=1 SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0 SelectiveIDE#0 Sta: insecure RecvChkFail- SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0 SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0 [1] PCIe r6.0.1, sections 6.33, 7.9.26 Signed-off-by: Alexey Kardashevskiy --- lib/header.h | 62 +++++++++++ ls-ecaps.c | 192 ++++++++++++++++++++++++++++++++ setpci.c | 1 + tests/cap-ide | 346 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 601 insertions(+) create mode 100644 tests/cap-ide diff --git a/lib/header.h b/lib/header.h index 2cee94f..68cb3c1 100644 --- a/lib/header.h +++ b/lib/header.h @@ -256,6 +256,7 @@ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ #define PCI_EXT_CAP_ID_32GT 0x2a /* Physical Layer 32.0 GT/s */ #define PCI_EXT_CAP_ID_DOE 0x2e /* Data Object Exchange */ +#define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ /*** Definitions of capabilities ***/ @@ -1422,6 +1423,67 @@ #define PCI_LMR_PORT_STS_READY 0x1 /* Margining Ready */ #define PCI_LMR_PORT_STS_SOFT_READY 0x2 /* Margining Software Ready */ +/* Integrity and Data Encryption Extended Capability */ +#define PCI_IDE_CAP 0x4 +#define PCI_IDE_CAP_LINK_IDE_SUPP 0x1 /* Link IDE Stream Supported */ +#define PCI_IDE_CAP_SELECTIVE_IDE_SUPP 0x2 /* Selective IDE Streams Supported */ +#define PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP 0x4 /* Flow-Through IDE Stream Supported */ +#define PCI_IDE_CAP_PARTIAL_HEADER_ENC_SUPP 0x8 /* Partial Header Encryption Supported */ +#define PCI_IDE_CAP_AGGREGATION_SUPP 0x10 /* Aggregation Supported */ +#define PCI_IDE_CAP_PCRC_SUPP 0x20 /* PCRC Supported */ +#define PCI_IDE_CAP_IDE_KM_SUPP 0x40 /* IDE_KM Protocol Supported */ +#define PCI_IDE_CAP_ALG(x) (((x) >> 8) & 0x1f) /* Supported Algorithms */ +#define PCI_IDE_CAP_ALG_AES_GCM_256 0 /* AES-GCM 256 key size, 96b MAC */ +#define PCI_IDE_CAP_LINK_TC_NUM(x) (((x) >> 13) & 0x7) /* Number of TCs Supported for Link IDE */ +#define PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(x) (((x) >> 16) & 0xff) /* Number of Selective IDE Streams Supported */ +#define PCI_IDE_CAP_TEE_LIMITED_SUPP 0x1000000 /* TEE-Limited Stream Supported */ +#define PCI_IDE_CTL 0x8 +#define PCI_IDE_CTL_FLOWTHROUGH_IDE 0x4 /* Flow-Through IDE Stream Enabled */ +#define PCI_IDE_LINK_STREAM 0xC +/* Link IDE Stream block, up to PCI_IDE_CAP_LINK_TC_NUM */ +/* Link IDE Stream Control Register */ +#define PCI_IDE_LINK_CTL_EN 0x1 /* Link IDE Stream Enable */ +#define PCI_IDE_LINK_CTL_TX_AGGR_NPR(x)(((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */ +#define PCI_IDE_LINK_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */ +#define PCI_IDE_LINK_CTL_TX_AGGR_CPL(x)(((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */ +#define PCI_IDE_LINK_CTL_PCRC_EN 0x100 /* PCRC Enable */ +#define PCI_IDE_LINK_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */ +#define PCI_IDE_LINK_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */ +#define PCI_IDE_LINK_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */ +#define PCI_IDE_LINK_CTL_ID(x) (((x) >> 24) & 0xff) /* Stream ID */ +/* Link IDE Stream Status Register */ +#define PCI_IDE_LINK_STS_STATUS(x) ((x) & 0xf) /* Link IDE Stream State */ +#define PCI_IDE_LINK_STS_RECVD_INTEGRITY_CHECK 0x80000000 /* Received Integrity Check Fail Message */ +/* Selective IDE Stream block, up to PCI_IDE_CAP_SELECTIVE_STREAMS_NUM */ +/* Selective IDE Stream Capability Register */ +#define PCI_IDE_SEL_CAP_BLOCKS_NUM(x) ((x) & 0xf) /* Number of Address Association Register Blocks */ +/* Selective IDE Stream Control Register */ +#define PCI_IDE_SEL_CTL_EN 0x1 /* Selective IDE Stream Enable */ +#define PCI_IDE_SEL_CTL_TX_AGGR_NPR(x) (((x) >> 2) & 0x3) /* Tx Aggregation Mode NPR */ +#define PCI_IDE_SEL_CTL_TX_AGGR_PR(x) (((x) >> 4) & 0x3) /* Tx Aggregation Mode PR */ +#define PCI_IDE_SEL_CTL_TX_AGGR_CPL(x) (((x) >> 6) & 0x3) /* Tx Aggregation Mode CPL */ +#define PCI_IDE_SEL_CTL_PCRC_EN 0x100 /* PCRC Enable */ +#define PCI_IDE_SEL_CTL_PART_ENC(x) (((x) >> 10) & 0xf) /* Partial Header Encryption Mode */ +#define PCI_IDE_SEL_CTL_ALG(x) (((x) >> 14) & 0x1f) /* Selected Algorithm */ +#define PCI_IDE_SEL_CTL_TC(x) (((x) >> 19) & 0x7) /* Traffic Class */ +#define PCI_IDE_SEL_CTL_DEFAULT 0x400000 /* Default Stream */ +#define PCI_IDE_SEL_CTL_ID(x) (((x) >> 24) & 0xff) /* Stream ID */ +/* Selective IDE Stream Status Register */ +#define PCI_IDE_SEL_STS_STATUS(x) ((x) & 0xf) /* Selective IDE Stream State */ +#define PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK 0x80000000 /* Received Integrity Check Fail Message */ +/* IDE RID Association Register 1 */ +#define PCI_IDE_SEL_RID_1_LIMIT(x) (((x) >> 8) & 0xffff) /* RID Limit */ +/* IDE RID Association Register 2 */ +#define PCI_IDE_SEL_RID_2_VALID 0x1 /* Valid */ +#define PCI_IDE_SEL_RID_2_BASE(x) (((x) >> 8) & 0xffff) /* RID Base */ +#define PCI_IDE_SEL_RID_2_SEG_BASE(x) (((x) >> 24) & 0xff) /* Segmeng Base */ +/* Selective IDE Address Association Register Block, up to PCI_IDE_SEL_CAP_BLOCKS_NUM */ +#define PCI_IDE_SEL_ADDR_1_VALID 0x1 /* Valid */ +#define PCI_IDE_SEL_ADDR_1_BASE_LOW(x) (((x) >> 8) & 0xfff) /* Memory Base Lower */ +#define PCI_IDE_SEL_ADDR_1_LIMIT_LOW(x)(((x) >> 20) & 0xfff) /* Memory Limit Lower */ +/* IDE Address Association Register 2 is "Memory Limit Upper" */ +/* IDE Address Association Register 3 is "Memory Base Upper" */ + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded diff --git a/ls-ecaps.c b/ls-ecaps.c index e73eb14..b40ba72 100644 --- a/ls-ecaps.c +++ b/ls-ecaps.c @@ -1488,6 +1488,195 @@ cap_doe(struct device *d, int where) FLAG(l, PCI_DOE_STS_OBJECT_READY)); } +static const char *offstr(char *buf, u32 off) +{ + if (verbose < 3) + return ""; + + sprintf(buf, "[%x]", off); + return buf; +} + +static const char *ide_alg(char *buf, size_t len, u32 l) +{ + const char *algo[] = { "AES-GCM-256-96b" }; // AES-GCM 256 key size, 96b MAC + + if (l == 0) + snprintf(buf, len, "%s", algo[l]); + else + snprintf(buf, len, "%s", "reserved"); + return buf; +} + +static void +cap_ide(struct device *d, int where) +{ + const char *hdr_enc_mode[] = { "no", "17:2", "25:2", "33:2", "41:2" }; + const char *stream_state[] = { "insecure", "secure" }; + const char *aggr[] = { "-", "=2", "=4", "=8" }; + u32 l, l2, linknum = 0, selnum = 0, addrnum, off, i, j; + char buf1[16], buf2[16], offs[16]; + + printf("Integrity & Data Encryption\n"); + + if (verbose < 2) + return; + + if (!config_fetch(d, where + PCI_IDE_CAP, 8)) + { + printf("\t\t\n"); + return; + } + + l = get_conf_long(d, where + PCI_IDE_CAP); + if (l & PCI_IDE_CAP_LINK_IDE_SUPP) + linknum = PCI_IDE_CAP_LINK_TC_NUM(l) + 1; + if (l & PCI_IDE_CAP_SELECTIVE_IDE_SUPP) + selnum = PCI_IDE_CAP_SELECTIVE_STREAMS_NUM(l) + 1; + + printf("\t\tIDECap: Lnk=%d Sel=%d FlowThru%c PartHdr%c Aggr%c PCPC%c IDE_KM%c Alg='%s' TCs=%d TeeLim%c\n", + linknum, + selnum, + FLAG(l, PCI_IDE_CAP_FLOWTHROUGH_IDE_SUPP), + FLAG(l, PCI_IDE_CAP_PARTIAL_HEADER_ENC_SUPP), + FLAG(l, PCI_IDE_CAP_AGGREGATION_SUPP), + FLAG(l, PCI_IDE_CAP_PCRC_SUPP), + FLAG(l, PCI_IDE_CAP_IDE_KM_SUPP), + ide_alg(buf2, sizeof(buf2), PCI_IDE_CAP_ALG(l)), + PCI_IDE_CAP_LINK_TC_NUM(l) + 1, + FLAG(l, PCI_IDE_CAP_TEE_LIMITED_SUPP) + ); + + l = get_conf_long(d, where + PCI_IDE_CTL); + printf("\t\tIDECtl: FTEn%c\n", + FLAG(l, PCI_IDE_CTL_FLOWTHROUGH_IDE)); + + // The rest of the capability is variable length arrays + off = where + PCI_IDE_LINK_STREAM; + + // Link IDE Register Block repeated 0 to 8 times + if (linknum) + { + if (!config_fetch(d, off, 8 * linknum)) + { + printf("\t\t\n"); + return; + } + for (i = 0; i < linknum; ++i) + { + // Link IDE Stream Control Register + l = get_conf_long(d, off); + printf("\t\t%sLinkIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d\n", + offstr(offs, off), + i, + FLAG(l, PCI_IDE_LINK_CTL_EN), + aggr[PCI_IDE_LINK_CTL_TX_AGGR_NPR(l)], + aggr[PCI_IDE_LINK_CTL_TX_AGGR_PR(l)], + aggr[PCI_IDE_LINK_CTL_TX_AGGR_CPL(l)], + FLAG(l, PCI_IDE_LINK_CTL_EN), + TABLE(hdr_enc_mode, PCI_IDE_LINK_CTL_PART_ENC(l), buf1), + ide_alg(buf2, sizeof(buf2), PCI_IDE_LINK_CTL_ALG(l)), + PCI_IDE_LINK_CTL_TC(l), + PCI_IDE_LINK_CTL_ID(l) + ); + off += 4; + + /* Link IDE Stream Status Register */ + l = get_conf_long(d, off); + printf("\t\t%sLinkIDE#%d Sta: Status=%s RecvChkFail%c\n", + offstr(offs, off), + i, + TABLE(stream_state, PCI_IDE_LINK_STS_STATUS(l), buf1), + FLAG(l, PCI_IDE_LINK_STS_RECVD_INTEGRITY_CHECK)); + off += 4; + } + } + + for (i = 0; i < selnum; ++i) + { + // Fetching Selective IDE Stream Capability/Control/Status/RID1/RID2 + if (!config_fetch(d, off, 20)) + { + printf("\t\t\n"); + return; + } + + // Selective IDE Stream Capability Register + l = get_conf_long(d, off); + printf("\t\t%sSelectiveIDE#%d Cap: RID#=%d\n", + offstr(offs, off), + i, + PCI_IDE_SEL_CAP_BLOCKS_NUM(l)); + off += 4; + addrnum = PCI_IDE_SEL_CAP_BLOCKS_NUM(l); + + // Selective IDE Stream Control Register + l = get_conf_long(d, off); + + printf("\t\t%sSelectiveIDE#%d Ctl: En%c NPR%s PR%s CPL%s PCRC%c HdrEnc=%s Alg='%s' TC%d ID%d%s\n", + offstr(offs, off), + i, + FLAG(l, PCI_IDE_SEL_CTL_EN), + aggr[PCI_IDE_SEL_CTL_TX_AGGR_NPR(l)], + aggr[PCI_IDE_SEL_CTL_TX_AGGR_PR(l)], + aggr[PCI_IDE_SEL_CTL_TX_AGGR_CPL(l)], + FLAG(l, PCI_IDE_SEL_CTL_PCRC_EN), + TABLE(hdr_enc_mode, PCI_IDE_SEL_CTL_PART_ENC(l), buf1), + ide_alg(buf2, sizeof(buf2), PCI_IDE_SEL_CTL_ALG(l)), + PCI_IDE_SEL_CTL_TC(l), + PCI_IDE_SEL_CTL_ID(l), + (l & PCI_IDE_SEL_CTL_DEFAULT) ? " Default" : "" + ); + off += 4; + + // Selective IDE Stream Status Register + l = get_conf_long(d, off); + printf("\t\t%sSelectiveIDE#%d Sta: %s RecvChkFail%c\n", + offstr(offs, off), + i , + TABLE(stream_state, PCI_IDE_SEL_STS_STATUS(l), buf1), + FLAG(l, PCI_IDE_SEL_STS_RECVD_INTEGRITY_CHECK)); + off += 4; + + // IDE RID Association Registers + l = get_conf_long(d, off); + l2 = get_conf_long(d, off + 4); + + printf("\t\t%sSelectiveIDE#%d RID: Valid%c Base=%x Limit=%x SegBase=%x\n", + offstr(offs, off), + i, + FLAG(l2, PCI_IDE_SEL_RID_2_VALID), + PCI_IDE_SEL_RID_2_BASE(l2), + PCI_IDE_SEL_RID_1_LIMIT(l), + PCI_IDE_SEL_RID_2_SEG_BASE(l2)); + off += 8; + + if (!config_fetch(d, off, addrnum * 12)) + { + printf("\t\t\n"); + return; + } + + // IDE Address Association Registers + for (j = 0; j < addrnum; ++j) + { + u64 limit, base; + + l = get_conf_long(d, off); + limit = get_conf_long(d, off + 4); + base = get_conf_long(d, off + 8); + printf("\t\t%sSelectiveIDE#%d RID#%d: Valid%c Base=%lx Limit=%lx\n", + offstr(offs, off), + i, + j, + FLAG(l, PCI_IDE_SEL_ADDR_1_VALID), + (base << 32) | PCI_IDE_SEL_ADDR_1_BASE_LOW(l), + (limit << 32) | PCI_IDE_SEL_ADDR_1_LIMIT_LOW(l)); + off += 12; + } + } +} + void show_ext_caps(struct device *d, int type) { @@ -1641,6 +1830,9 @@ show_ext_caps(struct device *d, int type) case PCI_EXT_CAP_ID_DOE: cap_doe(d, where); break; + case PCI_EXT_CAP_ID_IDE: + cap_ide(d, where); + break; default: printf("Extended Capability ID %#02x\n", id); break; diff --git a/setpci.c b/setpci.c index d2df573..7b7baea 100644 --- a/setpci.c +++ b/setpci.c @@ -396,6 +396,7 @@ static const struct reg_name pci_reg_names[] = { { 0x20027, 0, 0, 0x0, "ECAP_LMR" }, { 0x20028, 0, 0, 0x0, "ECAP_HIER_ID" }, { 0x20029, 0, 0, 0x0, "ECAP_NPEM" }, + { 0x20030, 0, 0, 0x0, "ECAP_IDE" }, { 0, 0, 0, 0x0, NULL } }; diff --git a/tests/cap-ide b/tests/cap-ide new file mode 100644 index 0000000..01a9e09 --- /dev/null +++ b/tests/cap-ide @@ -0,0 +1,346 @@ +e1:00.0 Class 0800: Device aaaa:bbbb + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- (32-bit, non-prefetchable) [disabled] + Region 2: Memory at 20018013000 (64-bit, prefetchable) [disabled] + Region 3: Memory at (32-bit, non-prefetchable) [disabled] + Expansion ROM at dc2c0000 [disabled] + Capabilities: [40] Power Management version 3 + Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [70] Express (v2) Endpoint, IntMsgNum 0 + DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us + ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 75W TEE-IO+ + DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq- + RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset- + MaxPayload 512 bytes, MaxReadReq 512 bytes + DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend- + LnkCap: Port #0, Speed 32GT/s, Width x16, ASPM not supported + ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ + LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 32GT/s, Width x16 + TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + DevCap2: Completion Timeout: Not Supported, TimeoutDis+ NROPrPrP- LTR+ + 10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1 + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- + FRS- TPHComp- ExtTPHComp- + AtomicOpsCap: 32bit+ 64bit+ 128bitCAS+ + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- + AtomicOpsCtl: ReqEn- + IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq- + 10BitTagReq+ OBFF Disabled, EETLPPrefixBlk- + LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS- + LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis- + Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- + Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot + LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+ + EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest- + Retimer- 2Retimers- CrosslinkRes: unsupported + Capabilities: [100 v2] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt- UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ + AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- + HeaderLog: 00000000 00000000 00000000 00000000 + Capabilities: [148 v1] Single Root I/O Virtualization (SR-IOV) + IOVCap: Migration- 10BitTagReq+ IntMsgNum 0 + IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+ 10BitTagReq- + IOVSta: Migration- + Initial VFs: 4, Total VFs: 4, Number of VFs: 0, Function Dependency Link: 00 + VF offset: 32, stride: 1, Device ID: 50a5 + Supported Page Size: 00000553, System Page Size: 00000001 + Region 0: Memory at 000001fff8000000 (64-bit, prefetchable) + Region 2: Memory at 000002001800c000 (64-bit, prefetchable) + VF Migration: offset: 00000000, BIR: 0 + Capabilities: [188 v1] Alternative Routing-ID Interpretation (ARI) + ARICap: MFVC- ACS-, Next Function: 1 + ARICtl: MFVC- ACS-, Function Group: 0 + Capabilities: [1c0 v1] Secondary PCI Express + LnkCtl3: LnkEquIntrruptEn- PerformEqu- + LaneErrStat: 0 + Capabilities: [3b0 v1] Physical Layer 16.0 GT/s + Capabilities: [400 v1] Lane Margining at the Receiver + PortCap: Uses Driver- + PortSta: MargReady+ MargSoftReady- + Capabilities: [450 v1] Access Control Services + ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- + ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- + Capabilities: [460 v1] Physical Layer 32.0 GT/s + Capabilities: [5f0 v1] Process Address Space ID (PASID) + PASIDCap: Exec+ Priv+, Max PASID Width: 10 + PASIDCtl: Enable+ Exec- Priv- + Capabilities: [830 v1] Integrity & Data Encryption + IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+ + IDECtl: FTEn- + SelectiveIDE#0 Cap: RID#=1 + SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0 + SelectiveIDE#0 Sta: insecure RecvChkFail- + SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0 + SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0 + Capabilities: [e00 v2] Data Object Exchange + DOECap: IntSup- + DOECtl: IntEn- + DOESta: Busy- IntSta- Error- ObjectReady- +00: aa aa bb bb 00 00 10 00 00 00 00 08 10 00 80 00 +10: 0c 00 00 14 00 02 00 00 0c 30 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