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Previously, we kept track of which fields were already filled, which
was quite brittle.
Now we keep only the set of already known fields in struct pci_dev.
We check if the current field is needed against this information.
Not only this simplifies the whole thing, but it also enables future
back-ends to call pci_fill_info() recursively as needed.
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Cross-compilers often provide only "gcc" and not "cc".
So let's try "cc" when building natively and "gcc" when cross-compiling.
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Do not report PCIe link downgrades for downstream ports.
Changed wording so that "overdriven" is reported instead of
"strange" for speeds greater than the maximum supported one.
Also report nothing instead of "ok".
Inspired by patches by Bjorn Helgaas and Matthew Wilcox.
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Users of the repeatedly complain that the library crashes, which is
usually caused by providing an error hook which returns to the library.
Let's try warning them more explicitly.
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Update the tests files with the new field 10BitTagReq
in SR-IOV Capabilities Register.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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Decode VF 10-Bit Tag Requester Supported and Enable bit
in SR-IOV Capabilities Register.
Sample output:
IOVCap: Migration- 10BitTagReq- Interrupt Message Number: 000
IOVCtl: Enable+ Migration- Interrupt- MSE+ ARIHierarchy- 10BitTagReq-
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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I believe "cc" is a much better default nowadays.
Another approach would be to (also) use "?=" for these variables.
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i386-ports.c: In function ‘conf12_setup_io’:
i386-io-windows.h:1021: warning: ‘old_token’ may be used uninitialized in this function
i386-io-windows.h:1021: note: ‘old_token’ was declared here
It is always properly initialized when accessed, just gcc compiler does not see it.
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It is used as argument for intel_cleanup_io() function.
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UCRT, MSVCRT and CRTDLL runtime libraries provides only _strcmpi()
function and not strcmpi().
MinGW32 has static libraries libcoldname.a and libmoldname.a which provides
strcmpi() function (as link-time redirect to _strcmpi()). libcoldname.a is
automatically linked when compiling for CRTDLL runtime and libmoldname.a
for MSVCRT runtime.
MinGW-w64 has only libmoldname.a library with strcmpi() function and it is
linked to final executable only when compiling for MSVCRT runtime.
when linking with MSVCRT.
To prevent dependency on particular linking configuration and MinGW
toolchain, use set strcasecmp() as alias to _strcmpi() function which is
provided by any runtime library.
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Remove "#if defined(__GNU_LIBRARY__)" guard for getopt() function
prototype in compat/getopt.h header file. The only purpose of
compat/getopt.h header is to provide getopt() function prototype for
compatibility purpose on every platform, specially those which do not use
GNU C library (e.g. Windows).
Without this change i586-mingw32msvc-gcc compiler complains that function
getopt() is used without defined prototype.
Also remove inclusion of #include <string.h> header file in compat/getopt.c
source file. Probably due to compatibility purposes compat/getopt.c file
has defined custom prototype for function strncmp() incompatible with C99
(length argument in C99 should be of type size_t). Including C99 prototype
of strncmp() function from MinGW32 <string.h> header file cause compile
errors for i586-mingw32msvc-gcc compiler. Instead of including <stringh>
provides custom and simple my_strncmp() implementation.
Thsi change fixes compilation of compat/getopt.c with i586-mingw32msvc-gcc,
i686-w64-mingw32-gcc, x86_64-w64-mingw32-gcc and also MSVC cl compilers.
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MinGW32 since version 3.0 declares getopt() function prototype in
<unistd.h> header file.
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As of PCIe 3.0, the LnkCtl2 "Compliance De-emphasis" field has been
renamed to "Compliance Preset/De-emphasis", and there are several new
bit encodings for various de-emphasis and preshoot combinations.
The name of the PCI_EXP_LNKCTL2_COM_DEEMPHASIS() macro is not changed
by this commit, as it is part of the libpci API.
Reported-by: Tim CC Chen(陳志佳) <Tim.CC.Chen@wnc.com.tw>
Signed-off-by: Lennert Buytenhek <buytenh@arista.com>
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PCI Express Base Specification rev. 3.0 has the following definition for
the Slot Power Limit Value:
=======================================================================
When the Slot Power Limit Scale field equals 00b (1.0x) and Slot Power
Limit Value exceeds EFh, the following alternative encodings are used:
F0h = 250 W Slot Power Limit
F1h = 275 W Slot Power Limit
F2h = 300 W Slot Power Limit
F3h to FFh = Reserved for Slot Power Limit values above 300 W
=======================================================================
Replace function power_limit() by show_power_limit() which also prints
power limit value. Show reserved value as string ">300W".
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Function intel_sanity_check() calls conf1_read() which access d->domain
field. But intel_sanity_check() does not initialize this field and so
conf1_read() access some random data on stack.
Tests showed that intel_sanity_check() always fails as in d->domain is
stored some non-zero number.
Fix this issue by zeroing struct pci_dev d in intel_sanity_check() as
sanity check is verifying PCI devices at domain 0.
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Currently PCI domains are printed in ascending order. Devices on each PCI
bus are also printed in ascending order. PCI buses behind PCI-to-PCI
bridges are also printed in ascending order.
But buses of PCI domain are currently printed in descending order because
function new_bus() puts newly created bus at the beginning of linked list.
In most cases PCI domain contains only one (top level) bus, so in most
cases it is not visible this inconsistency.
Multibus PCI domains (where PCI domain contains more independent top level
PCI buses) are available on ARM devices.
This change fixes print order of multibus PCI domains, so also top level
PCI buses are printed in ascending order, like PCI buses behind PCI-to-PCI
bridges.
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The value was quite misleading, as witnessed by multiple implementations
doing it wrong. In fact, the only return value which ever made sense was -1.
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U-Boot's "pci display.b" command prints pci config space dump with 8 digits
in line number. So allow up to the 8 digits in line number to easily parse
U-Boot's pci config space dumps.
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These files are old and cannot be used for compiling pcitutils anymore
(e.g. they use non-existent option TOOLPREFIX). As configure script now
works fine also for Windows build, remove these old win32 config files.
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This change adds support for using configure script for cross-compiling
pciutils on Linux for Windows platforms.
Following command can be used to compile pcitils for Windows platform:
make CROSS_COMPILE=i586-mingw32msvc- HOST=i386-windows ZLIB=no IDSDIR=.
PCI_OS_WINDOWS does not support BSD DNS functions, so do not automatically
enable DNS support.
Library ioperm is cygwin specific and is used only for PCI_OS_CYGWIN.
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This new option controls if compat/getopt.c should be compiled and linked
into lspci and setpci binaries. Useful for ancient platforms.
For example it is required to set COMPAT_GETOPT=yes for all versions of
MinGW32 with CRTDLL (as this MinGW32 variant does not have linkable
getopt() implementation). And also for MinGW32 with MSVCRT older than 3.0.
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If x86_64-w64-mingw32-gcc compiler is called with -o filename option
without any file extension then compiler automatically appends suffix
".exe" to output filename.
This behavior of x86_64-w64-mingw32-gcc compiler basically breaks pattern
rule of type '%: %.o' as x86_64-w64-mingw32-gcc compiler cannot generate
arbitrary output file via -o option just by stripping .o extension from
filename.
When generating executables by x86_64-w64-mingw32-gcc compiler it is
really the best option to specify .exe suffix in -o option.
So introduce a new makefile variable EXEEXT which will be automatically
appended to any executable filename. For Windows and DOS systems set it
to ".exe". For other systems set it just to empty string "".
GNU automake uses same makefile variable for same purpose.
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For Windows applications it is common to have all support data files in the
same directory where is stored executable itself, instead of in directory
hardcoded at compile time.
When PCI_PATH_IDS_DIR is set to "." it means that pci.ids file is located
in the current working directory. This is also unsuitable for Windows
command line applications stored in %PATH% because cmd.exe starts in some
default user or system location.
Adds a new option to allow specifying PCI_PATH_IDS_DIR to empty string ""
and for PCI_OS_WINDOWS platform it would mean to locate pci.ids file in the
same directory where is stored currently running executable. On Windows it
is always possible to detected this directory.
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ProcessUserModeIOPL syscall
libpci uses WinIo library from http://www.internals.com/ which is archived
at https://web.archive.org/web/20151005172744/http://www.internals.com/
This external WinIo library has two big issues:
1. Library license is incompatible with pciutils license.
2. It silently and automatically installs 3rd-party NT kernel module
WinIo.sys which is bundled in WinIO.dll binary.
That NT kernel module creates a device file "\\.\WinIo" which can be opened
by any running process. Via this device file can any process (including
unprivileged or those running under Guest account) ask that kernel module
to configure x86 TSS I/O port permissions for access to any I/O port. That
NT kernel module does not implement any permission checks and automatically
accept all requests.
Change in this commit replaces insecure WinIO.dll library and WinIo.sys
kernel module by proper NT system solution: Usage of ProcessUserModeIOPL
syscall (equivalent of iopl(3) on Linux) which is supported directly by NT
kernel. It does not require any external 3rd-party library or NT kernel
module.
This syscall can be invoked by NtSetInformationProcess() function from
ntdll.dll library (which is part of NT system) and for privileged processes
kernel changes x86 IOPL to 3.
Privileged process is that which has SeTcbPrivilege (Act as part of the
operating system privilege) or is running under account from local
Administrators group with SeImpersonatePrivilege (Impersonate a client
after authentication privilege). SeImpersonatePrivilege is enabled by
default for accounts from local Administrators group.
Usage of privileges is not easy operation and needs to call lot of
functions to gain required permissions, achieve thread-safety and follow
suggested guidelines. Hence code is quite long.
Privileges (including SeTcbPrivilege) can be enabled / disabled in User
Accounts settings by local Administrators and change takes effect after
next login, not immediately.
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CRTDLL and for 64-bit mode
Functions _outp(), _outpw(), _outpd(), _inp(), _inpw() and _inpd() are
available only in 32-bit version of the old MSVCRT library. They are not
available in 64-bit version of old MSVCRT library and neither the oldest
CRTDLL library or in new UCRT library.
Function prototypes for 32-bit mode should be available in <conio.h> header
file. But they are missing in some MinGW toolchains.
For 64-bit mode I/O port functions are defined only as inline functions or
intrinsics macros in <intrin.h> header file but under different names:
__outbyte(), __outword(), __outdword(), __inbyte(), __inword(), __indword()
This header file is available also in UCRT-compatible compilers.
When compiling with the oldest CRTDLL library and not using <intrin.h>
header file, it is required to provide own implementation of these
functions. Do it via inline assembly.
With this change it is possible to compile i386-io-windows.h with all
combination of toolchains, compilers, crt library and arch mode.
The most important is the fix to allow compilation with modern UCRT
library.
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16/32-bit non-NT systems allow applications to access PCI I/O ports without
any special setup.
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Include both the path and filename of pci.ids in the pci.ids man page
and the update-pciids man page
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Add cross-references to gzip, bzip2, curl, wget, and lynx.
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In the update-pciids man page:
* remove reference to setpci, since that does not use pci.ids
* add reference to pci.ids
Fixes: ef5b622f488e ("Added a man page for pci.ids")
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Based on a patch by <lixiaokeng@huawei.com>.
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There were multiple cases, in which malloc failure was either unchecked,
or a->error was called even though it was NULL.
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This enables "lspci" to show PCIe 6.0 data rate (64 GT/s) properly
according to the contents in register PCI_EXP_LNKCAP, PCI_EXP_LNKSTA
and PCI_EXP_LNKCTL2.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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guaranteed to set errnum so we initialized it to 0.
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Allow five nibbles as valid domain, when reading from a dump file with
domain
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If we move the file while making a backup, we can end up with no
pci.ids database in case the next step fails.
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Fix code alignment by using a hard-tab instead of 4 spaces. Add a blank
line after set -e.
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We should set -e as the first thing to catch any errors, so move the
quiet setup after the other variables setup.
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Signed-off-by: Guillem Jover <guillem@hadrons.org>
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The libpci.pc file does not seem to be correct for static linking.
$ pkg-config --libs --static libpci
-lpci
It brings no dependencies while -lresolv (and likely -lz) seems needed:
/usr/lib/gcc/x86_64-linux-gnu/4.7/../../../x86_64-linux-gnu/
libpci.a(names-net.o):function pci_id_net_lookup:
error: undefined reference to '__res_query'
Something like:
Libs.private: -lresolv -lz
Signed-off-by: Guillem Jover <guillem@hadrons.org>
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This handles the case when the HOST has not been specified by the user.
Signed-off-by: Guillem Jover <guillem@hadrons.org>
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We need to set a sys variable matching what would be found in the GNU
triplet for the GNU/kFreeBSD architecture, otherwise the later code will
not match correctly.
Signed-off-by: Guillem Jover <guillem@hadrons.org>
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Decode 10-Bit Tag Requester Enable bit in Device Control 2 Register.
Sample output changes:
- DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- OBFF Disabled, ARIFwd-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- LTR- 10BitTagReq- OBFF Disabled, ARIFwd-
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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Adjust PCI_EXP_DEV2_* to PCI_EXP_DEVCTL2_* macro definition to keep the
same style between the Linux kernel source [1] and lspci.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/uapi/linux/pci_regs.h#n651
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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Root Complex Event Collectors provide support for terminating error
and PME messages from RCiEPs. This patch provides basic decoding for
the lspci RCEC Endpoint Association Extended Capability. See PCIe 5.0-1,
sec 7.9.10 for further details.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
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Hurd: bug fixes and compile again
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Let us keep the bus scan light-weight. Whoever is interested
in device IDs, still has to call pci_fill_info(PCI_FILL_IDENT),
which handles this in generic way.
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Fixes a bug introduced by commit 82c06b47dea5a38075ce9d56f743360bc47b4c78.
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Update the cap-dvsec-cxl test to match the new vendor ID.
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
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Adjusted the output to better match the rest of lspci.
Made the code more straightforward.
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A patch by Paul Blinzer.
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Even if the back-end does not implement multiple domains, it can
be called on a device in a non-zero domain if the use obtained the
device by calling pci_get_dev() instead of scanning the bus.
In all such cases, report that 0 bytes were read/written.
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There was a lot of minor issues in the implementation of the fill_info
call-back in various back-ends. Most importantly, semantics of pci_dev->
known_fields was not formally defined and it was implemented inconsistently.
We now define known_fields as the set of fields which were already
obtained during the lifetime of the pci_dev. We never consider known
fields which are not supported by the back-end. All fields which are
unsupported by either the back-end, the OS, or the particular device,
are guaranteed to have sensible default values (0 or NULL). Also, bit
masks are always unsigned except for the signature of pci_fill_info()
which should be preferably kept stable.
All back-ends and the pci_generic_fill_info() function have been changed
to follow this semantics.
In the sysfs back-end, we read as few attributes as possible during
device initialization, so applications which use pci_get_dev() are not
slowed down unnecessarily.
In the Hurd back-end, we also respect the buscentric mode.
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Reported by Sean V Kelley <sean.v.kelley@linux.intel.com> on the
linux-pci list.
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We decode the DVSEC capability header first. If we recognize the vendor
and ID (and the length is at least the minimum we need), we call
a specific function to interpret the rest of the capability.
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Compute eXpress Link[1] is a new CPU interconnect created with
workload accelerators in mind. The interconnect relies on PCIe
electrical and physical interconnect for communication via a Flex Bus
port which allows designs to choose between providing PCIe or CXL.
This patch introduces basic support for lspci decode of CXL and
builds upon the existing Designated Vendor-Specific support in
lspci through identification of a supporting CXL device using DVSEC
Vendor ID and DVSEC ID.
[1] https://www.computeexpresslink.org/
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
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Instead of current generic 'unknown' output for DVSEC, decode details on
Vendor ID, Rev, etc.
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@linux.intel.com>
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General practice has been to use a comma after a multi-word item, but omit
commas between single-bit flags. Do this more consistently.
Sample output changes:
- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
+ LnkCtl: ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
- DevCap2: Completion Timeout: Not Supported, TimeoutDis-, NROPrPrP-, LTR+
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis- NROPrPrP- LTR+
- 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix-
+ 10BitTagComp- 10BitTagReq- OBFF Not Supported, ExtFmt- EETLPPrefix-
- FRS-, ARIFwd-
+ FRS- ARIFwd-
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Decode Link Capabilities 2, which includes the Supported Link Speeds
Vector, and decode more fields of Link Status 2.
The test case (data from https://bugzilla.kernel.org/show_bug.cgi?id=206837
comment #21) includes a Thunderbolt Downstream Port that advertises
2.5-8GT/s support in Link Capabilities 2.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Allow clients to read and write from a device w/o a bus scan
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A new module for the Hurd that accesses PCI bus using available RPCs.
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This will be the real 3.6.3.
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As reported in GitHub issue #24, tree dumping mode can smash the stack
if the hierarchy of buses is too deep.
Increased line buffer size to 1024 and switched to use of snprintf
everywhere, so that in the worst case, the line is truncated.
As snprintf can be problematic on obscure platforms, I wrapped it
in tree_printf(), so that we can add #ifdefs should problems arise.
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"[virtual]" and "[enhanced]" are now printed after the base address
along with other flags.
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Originally, I wanted to fix a bug, which caused 64-bit addresses
with their lower 32 bits zero to be reported as virtual regions.
However, it turned out that the whole function is quite messy,
so I rewrote it.
Also, we now print "[virtual]" and "[enhanced]" after the base address
along other modifiers.
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Change output displayed for memory behind bridge when the range is
empty to be consistent between each verbosity level. Replace "None" and
"[empty]" with "[disabled]". Old and new output examples listed below
for each verbosity level.
Show_range() is not called unless verbose == true. No output given
unless a verbose argument is provided.
OLD output for -v and -vv which uses "None" and -vvv uses "[empty]":
Memory behind bridge: None # lspci -v
Memory behind bridge: None # lspci -vv
Memory behind bridge: 0000e000-0000efff [empty] # lspci -vvv
NEW output for -v, -vv, and -vvv to use "[disabled]":
Memory behind bridge: [disabled] # lspci -v
Memory behind bridge: [disabled] # lspci -vv
Memory behind bridge: 0000e000-0000efff [disabled] # lspci -vvv
Advantage is consistent output regardless of verbosity level chosen and
to simplify the code.
Signed-off-by: Kelsey Skunberg <skunberg.kelsey@gmail.com>
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Remove 'if (!verbose)' code in show_range() due to not being called.
show_range() will only be called when verbose is true. Additional call
to check for verbosity within show_range() is dead code.
!verbose was used so nothing would print if the range behind a bridge
had a base > limit and verbose == false. Since show_range() will not be
called when verbose == false, not printing bridge information is
still accomplished.
Signed-off-by: Kelsey Skunberg <skunberg.kelsey@gmail.com>
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Include -vvv in help message.
Signed-off-by: Kelsey Skunberg <skunberg.kelsey@gmail.com>
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Registers in the PCI Express Capability come in sets of three (Capability,
Control, Status), and we typically print them in that order. The Root
Complex-related registers were an exception: we printed them in the
(Control, Capability, Status) order.
Decode the RootCap, RootCtl, and RootSta registers in the usual order.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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This includes clarified copyright statement.
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This enables "lspci" to show PCIe 5.0 data rate (32 GT/s) properly
according to the contents in register PCI_EXP_LNKCAP, PCI_EXP_LNKSTA
and PCI_EXP_LNKCTL2.
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
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Decode all defined fields in the Device Capabilities 2 register.
The difference from "lspci -vv" output now looks like this:
- DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
+ DevCap2: Completion Timeout: Range ABC, TimeoutDis+, NROPrPrP-, LTR+
+ 10BitTagComp-, 10BitTagReq-, OBFF Not Supported, ExtFmt-, EETLPPrefix-
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-, LN System CLS Not Supported, TPHComp-, ExtTPHComp-, ARIFwd+
Signed-off-by: Frederick Lawler <fred@fredlawl.com>
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Fixes: fb17077dc378 ("Cleaned up the previous patch")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
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Ordering of our cached list of capabilities now respects the original
order in the device's configuration space.
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According to discussion in GitHub PR #8, Root complex integrated
endpoints also support FLR.
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Signed-off-by: Basavaraja M S <basavam@cadence.com>
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New URLs suggested by GitHub PR #20.
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Add capability names for all the capabilities known to lspci.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Decode the Multicast Extended Capability described in PCIe r4.0, sec
7.9.11.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Found by Coverity scan.
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libpci uses PCIOCGETCONF for non-privileged access to /dev/pci
and calculates device_class value based on pc_class/pc_subclass
fields expecting the former to be higher 8 bits of the target value.
0f3d0ca73ecedaba180bf4607bb57fb8abe6d405 errorneously swapped
order of class/subclass during calculations.
Signed-off-by: Oleksandr Tymoshenko <gonzo@bluezbox.com>
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The cap_number is always set to the total number of capability instances
found, regardless of whether a match was found or not.
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Because a capability can exist multiple times with the same id,
there needs to be a way to target a specific one. Instead of
the current behaviour which always targets the first one.
Now you can optionally add `@number` (e.g `@1`) after the width to
choose which one to target.
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Suggested by Milan Kral.
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PCIe spec says root ports and root complex event collectors must implement
root CAP, STAT and CTRL registers, so call cap_express_root() not only for
PCI_EXP_TYPE_ROOT_PORT but also for PCI_EXP_TYPE_ROOT_EC.
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Contributed by Matthew Wilcox
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If bus topology is needed, we scan all devices regardless of filters,
and apply the filters later when showing devices.
Also, we forbid several impossible combinations of options: tree mode
with filters, bus mapping mode with anything requiring topology.
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Previously, only PCI_CLASS_BRIDGE_PCI was considered, which excluded
CardBus bridges. We now accept anything of the base class "bridge"
with the proper header type.
Also added a bunch of debugging messages.
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Originally implemented by Matthew Wilcox as a stand-alone feature.
I modified it to make use of bus topology calculated by ls-tree.c.
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The topology tree is now independent of the plain device list
and it can be traversed in both top-to-bottom and bottom-to-top
directions.
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The function canonicalize_file_name() is GLIBC-specific, use realpath()
instead, which is available also on MUSL libc.
Also, it leaked memory.
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This removes the need of explicit memory management and fixes
PCI_FILL_RESCAN.
To keep backward compatibility, I am keeping the raw pointers
in struct pci_dev, but they point inside the pci_property instead
of separately allocated memory.
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Introduction of device tree node properties broke library ABI.
I gave up on creating new symbol versions whenever we add a new
device property, so I introduced a generic property interface
with which new string properties can be added while keeping ABI
compatibility.
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Adds the path of the device-tree node of a PCI device to the lspci -v
output, like so:
0021:00:00.0 PCI bridge: IBM Device 03dc (prog-if 00 [Normal decode])
DT Node: /sys/firmware/devicetree/base/pciex@3fffe41100000/pci@0
This is added as a generic property to struct pci_device and populated
by the sysfs backend. Other platforms may find it useful though.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
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This patch adds 'ctags' and 'TAGS' targets to Makefile
Signed-off-by: Viktor Prutyanov <viktor.prutyanov@virtuozzo.com>
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IBM has defined several VPD fields that are not part of the PCI
spec, but are frequently used on embedded and pluggable pcie
adapters.
Since these fields are "Unknown", they are listed in hex
and less readable.
This patch adds commonly used vendor specific VPD keywords
described in "Table 160. LoPAPR VPD Fields" of the Linux on Power
Architecture Platform Reference (LoPAPR).
Signed-off-by: John Walthour <return.0@me.com>
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We wanted to add a "[virtual]" marker to all resources which are
known to the kernel, but not configured in the hardware. That is,
those where the BAR is all zero.
However, the test was never triggered for I/O regions, since their
BAR is never zero: it always has the region type bit set.
Now, we test only the address part of the BAR.
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Extended Capability ID 0x000a is the RCRB (Root Complex Register Block)
capability. Change the #define and the capability label to match the
terminology used in the specs.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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We don't have decoders for many new capabilities, so we currently print
just the capability ID, e.g.,
Capabilities: [220 v1] Extended Capability ID 0x19
Print the names, even if we don't yet know how to decode the contents,
e.g.,
Capabilities: [220 v1] Secondary PCI Express <?>
The capability IDs are taken from the PCI Code and ID Assignment spec,
r1.10. The #defines are named to match those in Linux when possible.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The PCI Code and ID Assignment spec, r1.9, sec 2, defines a "Null
Capability" containing no registers other than the 8-bit Capability ID
(00h) and an 8-bit Next Capability Pointer.
Some devices, e.g., the Intel [8086:2058] implement this Capability.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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For capabilities we don't know how to decode, we print the config address,
version, and capability ID:
Capabilities: [220 v1] #19
This doesn't clearly identify the capability ID ("19"), whether it is a
PCI-compatible Capability ID or an Extended Capability ID (although you can
infer this by whether the address is 2 or 3 digits), or the fact that the
ID is printed in hex, which makes it hard to parse this manually.
Add a label ("Capability ID" or "Extended Capability ID") and print a "0x"
prefix so it's clear the value is in hex:
Capabilities: [220 v1] Extended Capability ID 0x19
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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This kind of format strings is not available on some compilers.
Also added a test case for the HT capability.
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In commit ef6c9ec3a45992d9e7ef4716d444252baf2013e1 pci_fill_info() calls were moved
and the label field is filled after its output.
Before this patch lspci never prints 'DeviceName'.
Signed-off-by: Viktor Prutyanov <viktor.prutyanov@virtuozzo.com>
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Contributed by YuJian Gong.
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Previously, the probe order was determined by the order of back-ends.
However, new back-ends must be always added at the end of the list
to maintain ABI compatibility, so they were always probed last.
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On SylixOS, it is defined as a macro.
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SylixOS defines its own versions of these functions in its standard
library, which collide with ours. However, their prototypes make
more sense, because they follow the prototypes of the non-x versions
in the C standard, so there is no harm in following them.
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Based on an idea by Dmitry Monakhov.
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Change DevCtl error reporting enables so they match the corresponding
DevSta bits:
- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+ DevCtl: CorrErr- NonFatalErr- FatalErr- UnsupReq-
PCIe r4.0, sec 6.2.2, classifies errors as Correctable or Uncorrectable.
Uncorrectable includes both Non-Fatal and Fatal errors. Decode the DevSta
"Non-Fatal Error Detected" bit as "NonFatalErr", not "UncorrErr":
- DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend-
+ DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend-
Change the "Unsupported" and "UnsuppReq" labels in DevCtl and DevSta to
match the "UnsupReq" used in AER.
The Correctable error category doesn't include Non-Fatal errors, so change
the AER Correctable Error Status "Advisory Non-Fatal Error Status" from
"NonFatalErr" to "AdvNonFatalErr":
- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The previous version was obviously wrong: as Andriy Gapon pointed
out, we assign twice to t->dev, but never to t->func.
Not tested, though, as I have no FreeBSD system at hand.
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Decode the "VGA 16-bit decode" bit in the bridge control register. This
bit was added in the PCI-to-PCI Bridge Arch Spec, r1.2, sec 3.2.5.18.
Note that the bit is only meaningful if the VGA Enable bit or the VGA
Palette Snoop Enable bit is set.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Here is bit a blast from the past. The flashrom still supports the DOS/DJGPP environment, which requires
pciutils to be compiled with DJGPP. I originally developed this patch in 2010,
and I respun it for latest pciutils.
* Add DJGPP as an OS target
* Stop if endianess macros are not defined
* Introduce new intel_io_lock/unclock function to synchronize
I/O operations.
There is a small issue left that "lspci" and "lspci.exe" are created. The ".exe" variants
are not installed and also not cleaned. No idea if you want to fix that or not.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Compiled with:
make ZLIB=no DNS=no HOST=i386-djgpp-djgpp CROSS_COMPILE=i586-pc-msdosdjgpp- \
PREFIX=/ DESTDIR=$PWD/../libpci-libgetopt \
STRIP="--strip-program=i586-pc-msdosdjgpp-strip -s" install install-lib
If you put to C:\share\pci.ids file, the lspci.exe will also display the human readable output.
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The PCI spec defines all keyword data fields as ASCII unless
otherwise noted. The MN keyword is not otherwise noted. To make
the MN field human readable in lspci verbose outputs, this patch
changes the MN keyword definition from F_BINARY to F_TEXT.
Signed-off-by: John Walthour <return.0@me.com>
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This way we can at least fulfill some of the common requests without root
privileges. This allows various applications (for example the google chrome
webbrowser) to successfully probe the list of PCI devices without needing
read-write access to the /dev/pci device file.
Signed-off-by: Imre Vadász <imrevdsz@gmail.com>
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Signed-off-by: Imre Vadász <imrevdsz@gmail.com>
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DragonFly also supports PCI domains same as FreeBSD.
Signed-off-by: Imre Vadász <imrevdsz@gmail.com>
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The `echo -n` behavior is not in POSIX and not all shells support it.
Use the portable `printf` func as defined by POSIX.
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We are reading wrong size(word) for this cap, since:
RootSta has:
PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Use existing #defines when possible so grep/cscope/etc are more useful. No
functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Per PCIe spec r3.1, sec 7.8.6, the L0s Exit Latency is only valid when L0s
is supported, and similarly the L1 Exit Latency is only valid when L1 is
supported.
Only decode the L0s and L1 Exit Latencies if they are defined.
For example, on a device that supports L1 but not L0s, the difference in
the "lspci -vv" output looks like this:
- LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us
+ LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L1 <16us
Correct the comments on the PCI_EXP_LNKCAP_L0S and PCI_EXP_LNKCAP_L1
definitions.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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The secondary side of a PCI/PCI-X to PCIe Bridge (a "reverse bridge") is a
PCIe Downstream Port and could support a slot just like Root Ports and
Switch Downstream Ports.
Decode "Slot Implemented" for reverse bridges and, if true, the Slot
Capabilities, Control, and Status registers.
For a reverse bridge with no slot, the difference in the "lspci -vv" output
looks like this:
- Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge, MSI 00
+ Capabilities: [40] Express (v2) PCI/PCI-X to PCI-Express Bridge (Slot-), MSI 00
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Indent the AtomicOpsCap and AtomicOpsCtl fields to make it clear that these
are part of the DevCap2 and DevCtl2 registers.
The difference in the "lspci -vv" output looks like this:
DevCap2: Completion Timeout: Range ABC, TimeoutDis+, LTR+, OBFF Not Supported ARIFwd+
- AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
+ AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR+, OBFF Disabled ARIFwd-
- AtomicOpsCtl: ReqEn- EgressBlck-
+ AtomicOpsCtl: ReqEn- EgressBlck-
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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