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-rw-r--r--lib/header.h11
-rw-r--r--ls-caps.c24
-rw-r--r--ls-ecaps.c16
-rw-r--r--setpci.man2
-rw-r--r--tests/pri-pasid325
5 files changed, 358 insertions, 20 deletions
diff --git a/lib/header.h b/lib/header.h
index 57ef0ae..63fbb92 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -903,9 +903,13 @@
#define PCI_EXP_DEVCTL2_ARI 0x0020 /* ARI Forwarding */
#define PCI_EXP_DEVCTL2_ATOMICOP_REQUESTER_EN 0x0040 /* AtomicOp RequesterEnable */
#define PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK 0x0080 /* AtomicOp Egress Blocking */
+#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
+#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
#define PCI_EXP_DEVCTL2_LTR 0x0400 /* LTR enabled */
+#define PCI_EXP_DEVCTL2_EPR_REQ 0x0800 /* Emergency Power Reduction Request */
#define PCI_EXP_DEVCTL2_10BIT_TAG_REQ 0x1000 /* 10 Bit Tag Requester enabled */
#define PCI_EXP_DEVCTL2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */
+#define PCI_EXP_DEVCTL2_EE_TLP_BLK 0x8000 /* End-End TLP Prefix Blocking */
#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */
#define PCI_EXP_LNKCAP2_SPEED(x) (((x) >> 1) & 0x7f)
@@ -1301,9 +1305,10 @@
#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
#define PCI_PRI_CTRL_RESET 0x02 /* Reset */
#define PCI_PRI_STATUS 0x06 /* PRI status register */
-#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
-#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
-#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
+#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */
+#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
+#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
+#define PCI_PRI_STATUS_PASID 0x8000 /* PASID required in PRG response */
#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
diff --git a/ls-caps.c b/ls-caps.c
index 1b63262..2c99812 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -841,7 +841,7 @@ static void cap_express_link(struct device *d, int where, int type)
if ((type == PCI_EXP_TYPE_ROOT_PORT) || (type == PCI_EXP_TYPE_ENDPOINT) ||
(type == PCI_EXP_TYPE_LEG_END) || (type == PCI_EXP_TYPE_PCI_BRIDGE))
printf(" RCB %d bytes,", w & PCI_EXP_LNKCTL_RCB ? 128 : 64);
- printf(" Disabled%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
+ printf(" LnkDisable%c CommClk%c\n\t\t\tExtSynch%c ClockPM%c AutWidDis%c BWInt%c AutBWInt%c\n",
FLAG(w, PCI_EXP_LNKCTL_DISABLE),
FLAG(w, PCI_EXP_LNKCTL_CLOCK),
FLAG(w, PCI_EXP_LNKCTL_XSYNCH),
@@ -1153,12 +1153,9 @@ static void cap_express_dev2(struct device *d, int where, int type)
}
w = get_conf_word(d, where + PCI_EXP_DEVCTL2);
- printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c LTR%c 10BitTagReq%c OBFF %s,",
+ printf("\t\tDevCtl2: Completion Timeout: %s, TimeoutDis%c",
cap_express_dev2_timeout_value(PCI_EXP_DEVCTL2_TIMEOUT_VALUE(w)),
- FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS),
- FLAG(w, PCI_EXP_DEVCTL2_LTR),
- FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
- cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)));
+ FLAG(w, PCI_EXP_DEVCTL2_TIMEOUT_DIS));
if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_DOWNSTREAM)
printf(" ARIFwd%c\n", FLAG(w, PCI_EXP_DEVCTL2_ARI));
else
@@ -1176,6 +1173,15 @@ static void cap_express_dev2(struct device *d, int where, int type)
printf(" EgressBlck%c", FLAG(w, PCI_EXP_DEVCTL2_ATOMICOP_EGRESS_BLOCK));
printf("\n");
}
+ printf("\t\t\t IDOReq%c IDOCompl%c LTR%c EmergencyPowerReductionReq%c\n",
+ FLAG(w, PCI_EXP_DEVCTL2_IDO_REQ_EN),
+ FLAG(w, PCI_EXP_DEVCTL2_IDO_CMP_EN),
+ FLAG(w, PCI_EXP_DEVCTL2_LTR),
+ FLAG(w, PCI_EXP_DEVCTL2_EPR_REQ));
+ printf("\t\t\t 10BitTagReq%c OBFF %s, EETLPPrefixBlk%c\n",
+ FLAG(w, PCI_EXP_DEVCTL2_10BIT_TAG_REQ),
+ cap_express_devctl2_obff(PCI_EXP_DEVCTL2_OBFF(w)),
+ FLAG(w, PCI_EXP_DEVCTL2_EE_TLP_BLK));
}
static const char *cap_express_link2_speed_cap(int vector)
@@ -1185,8 +1191,10 @@ static const char *cap_express_link2_speed_cap(int vector)
* permitted to skip support for any data rates between 2.5GT/s and the
* highest supported rate.
*/
- if (vector & 0x60)
+ if (vector & 0x40)
return "RsvdP";
+ if (vector & 0x20)
+ return "2.5-64GT/s";
if (vector & 0x10)
return "2.5-32GT/s";
if (vector & 0x08)
@@ -1430,7 +1438,7 @@ cap_express(struct device *d, int where, int cap)
default:
printf("Unknown type %d", type);
}
- printf(", MSI %02x\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
+ printf(", IntMsgNum %d\n", (cap & PCI_EXP_FLAGS_IRQ) >> 9);
if (verbose < 2)
return type;
diff --git a/ls-ecaps.c b/ls-ecaps.c
index 6028607..267d98e 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -191,7 +191,7 @@ cap_aer(struct device *d, int where, int type)
l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
- "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsg %d\n",
+ "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d\n",
FLAG(l, PCI_ERR_ROOT_COR_RCV),
FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
@@ -221,7 +221,7 @@ static void cap_dpc(struct device *d, int where)
return;
l = get_conf_word(d, where + PCI_DPC_CAP);
- printf("\t\tDpcCap:\tINT Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
+ printf("\t\tDpcCap:\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
@@ -324,9 +324,9 @@ cap_pri(struct device *d, int where)
printf("\t\tPRICtl: Enable%c Reset%c\n",
FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
w = get_conf_word(d, where + PCI_PRI_STATUS);
- printf("\t\tPRISta: RF%c UPRGI%c Stopped%c\n",
+ printf("\t\tPRISta: RF%c UPRGI%c Stopped%c PASID%c\n",
FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
- FLAG(w, PCI_PRI_STATUS_STOPPED));
+ FLAG(w, PCI_PRI_STATUS_STOPPED), FLAG(w, PCI_PRI_STATUS_PASID));
l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
printf("\t\tPage Request Capacity: %08x, ", l);
l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
@@ -371,7 +371,7 @@ cap_sriov(struct device *d, int where)
return;
l = get_conf_long(d, where + PCI_IOV_CAP);
- printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c Interrupt Message Number: %03x\n",
+ printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c IntMsgNum %d\n",
FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
w = get_conf_word(d, where + PCI_IOV_CTRL);
printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
@@ -1245,7 +1245,7 @@ cap_ptm(struct device *d, int where)
buff = get_conf_long(d, where + 4);
printf("\t\tPTMCap: ");
- printf("Requester:%c Responder:%c Root:%c\n",
+ printf("Requester%c Responder%c Root%c\n",
FLAG(buff, 0x1),
FLAG(buff, 0x2),
FLAG(buff, 0x4));
@@ -1266,7 +1266,7 @@ cap_ptm(struct device *d, int where)
buff = get_conf_long(d, where + 8);
printf("\t\tPTMControl: ");
- printf("Enabled:%c RootSelected:%c\n",
+ printf("Enabled%c RootSelected%c\n",
FLAG(buff, 0x1),
FLAG(buff, 0x2));
@@ -1394,7 +1394,7 @@ cap_doe(struct device *d, int where)
printf("\t\tDOECap: IntSup%c\n",
FLAG(l, PCI_DOE_CAP_INT_SUPP));
if (l & PCI_DOE_CAP_INT_SUPP)
- printf("\t\t\tInterrupt Message Number %03x\n",
+ printf("\t\t\tIntMsgNum %d\n",
PCI_DOE_CAP_INT_MSG(l));
l = get_conf_long(d, where + PCI_DOE_CTL);
diff --git a/setpci.man b/setpci.man
index 9e4e1d8..fd4495f 100644
--- a/setpci.man
+++ b/setpci.man
@@ -135,7 +135,7 @@ are hexadecimal numbers. In the latter case, only the bits corresponding to bina
ones in the \fImask\fP are changed (technically, this is a read-modify-write operation).
.PP
-There are several ways how to identity a register:
+There are several ways to identify a register:
.IP \(bu
Tell its address in hexadecimal.
.IP \(bu
diff --git a/tests/pri-pasid b/tests/pri-pasid
new file mode 100644
index 0000000..9fc8c09
--- /dev/null
+++ b/tests/pri-pasid
@@ -0,0 +1,325 @@
+6a:01.0 Class 0880: Device 8086:0b25
+ Subsystem: Device 8086:0000
+ Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+ Latency: 0
+ NUMA node: 0
+ IOMMU group: 38
+ Region 0: Memory at 206ffff40000 (64-bit, prefetchable) [size=64K]
+ Region 2: Memory at 206ffff00000 (64-bit, prefetchable) [size=128K]
+ Capabilities: [40] Express (v2) Root Complex Integrated Endpoint, MSI 00
+ DevCap: MaxPayload 512 bytes, PhantFunc 0
+ ExtTag+ RBE+ FLReset+
+ DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset-
+ MaxPayload 512 bytes, MaxReadReq 4096 bytes
+ DevSta: CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
+ DevCap2: Completion Timeout: Not Supported, TimeoutDis+ NROPrPrP- LTR+
+ 10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1
+ EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit-
+ FRS-
+ AtomicOpsCap: 32bit- 64bit- 128bitCAS-
+ DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis+ LTR- 10BitTagReq+ OBFF Disabled,
+ AtomicOpsCtl: ReqEn-
+ Capabilities: [80] MSI-X: Enable+ Count=9 Masked-
+ Vector table: BAR=0 offset=00002000
+ PBA: BAR=0 offset=00003000
+ Capabilities: [90] Power Management version 3
+ Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
+ Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
+ Capabilities: [100 v2] Advanced Error Reporting
+ UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
+ UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq+ ACSViol-
+ UESvrt: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP+ ECRC- UnsupReq- ACSViol-
+ CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr-
+ AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn-
+ MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
+ HeaderLog: 00000000 00000000 00000000 00000000
+ Capabilities: [150 v1] Latency Tolerance Reporting
+ Max snoop latency: 0ns
+ Max no snoop latency: 0ns
+ Capabilities: [160 v1] Transaction Processing Hints
+ Device specific mode supported
+ Steering table in TPH capability structure
+ Capabilities: [170 v1] Virtual Channel
+ Caps: LPEVC=1 RefClk=100ns PATEntryBits=1
+ Arb: Fixed+ WRR32- WRR64- WRR128-
+ Ctrl: ArbSelect=Fixed
+ Status: InProgress-
+ VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+ Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+ Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=fd
+ Status: NegoPending- InProgress-
+ VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
+ Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
+ Ctrl: Enable+ ID=1 ArbSelect=Fixed TC/VC=02
+ Status: NegoPending- InProgress-
+ Capabilities: [200 v1] Designated Vendor-Specific: Vendor=8086 ID=0005 Rev=0 Len=24 <?>
+ Capabilities: [220 v1] Address Translation Service (ATS)
+ ATSCap: Invalidate Queue Depth: 00
+ ATSCtl: Enable+, Smallest Translation Unit: 00
+ Capabilities: [230 v1] Process Address Space ID (PASID)
+ PASIDCap: Exec- Priv+, Max PASID Width: 14
+ PASIDCtl: Enable+ Exec- Priv+
+ Capabilities: [240 v1] Page Request Interface (PRI)
+ PRICtl: Enable- Reset-
+ PRISta: RF- UPRGI- Stopped+ PASID+
+ Page Request Capacity: 00000200, Page Request Allocation: 00000000
+ Kernel driver in use: idxd
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generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-23 02:07:23 +0000