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authorMartin Mares <mj@ucw.cz>2018-12-31 15:15:09 +0100
committerMartin Mares <mj@ucw.cz>2018-12-31 15:15:09 +0100
commit9f7dc65c6973456fb765560bbd9c9e7fc03543ec (patch)
treec3db69201b5a1a6471fc39c6fb2b5c90a279a068
parent21ff9851e63a64eef9c031d3d40af5a5dadf43b9 (diff)
downloadpciutils-9f7dc65c6973456fb765560bbd9c9e7fc03543ec.tar.gz
Cosmetic cleanups of the previous commit
-rw-r--r--lib/header.h12
-rw-r--r--ls-ecaps.c2
2 files changed, 7 insertions, 7 deletions
diff --git a/lib/header.h b/lib/header.h
index 6ca93fe..ddc1e94 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -1143,12 +1143,12 @@
#define PCI_LTR_MAX_NOSNOOP 6 /* 16 bit value */
/* Secondary PCI Express Extended Capability */
-#define PCI_SEC_LNKCTL3 4 /* Link Control 3 register*/
-#define PCI_SEC_LNKCTL3_PERFORM_LINK_EQU 0x01
-#define PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN 0x02
-#define PCI_SEC_LNKCTL3_ENBL_LOWER_SKP_OS_GEN_VEC(x) ((x >> 8) & 0x7F)
-#define PCI_SEC_LANE_ERR 8 /* Lane Error status register */
-#define PCI_SEC_LANE_EQU_CTRL 12 /* Lane Equalization contol register */
+#define PCI_SEC_LNKCTL3 4 /* Link Control 3 register */
+#define PCI_SEC_LNKCTL3_PERFORM_LINK_EQU 0x01
+#define PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN 0x02
+#define PCI_SEC_LNKCTL3_ENBL_LOWER_SKP_OS_GEN_VEC(x) ((x >> 8) & 0x7F)
+#define PCI_SEC_LANE_ERR 8 /* Lane Error status register */
+#define PCI_SEC_LANE_EQU_CTRL 12 /* Lane Equalization control register */
/* Process Address Space ID */
#define PCI_PASID_CAP 0x04 /* PASID feature register */
diff --git a/ls-ecaps.c b/ls-ecaps.c
index a26ea03..db99ed0 100644
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -97,7 +97,7 @@ cap_sec(struct device *d, int where, int type)
printf("\t\tLaneErrStat: ");
if (lane_err_stat)
{
- printf("LaneErr at Lane:");
+ printf("LaneErr at lane:");
for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
if (BITS(lane_err_stat, 0, 1))
printf(" %u", lane);