| Age | Commit message (Collapse) | Author | Files | Lines |
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This one from my DMA_{32,64}BIT_MASK series did not seem to make it
through to upstream.
Use the DMA_{32,64}BIT_MASK constants from dma-mapping.h when calling
pci_set_dma_mask() or pci_set_consistent_dma_mask()
This patch includes dma-mapping.h explicitly because it caused errors
on some architectures otherwise.
See http://marc.theaimsgroup.com/?t=108001993000001&r=1&w=2 for details
Signed-off-by: Tobias Klauser <tklauser@nuerscht.ch>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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Update version and reldate and add more sanity checking to
tg3_set_settings().
Signed-off-by: Gary Zambrano <zambrano@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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Change the ASF heart beat to 5 seconds for faster detection of system
crash. The driver sends the heartbeat every 2 seconds and the ASF
firmware will timeout and reset the device if no heartbeat is received
after 5 seconds. The old scheme of 2 minutes is ineffective.
tg3_write_mem_fast() is added to speed up the IO to send the heartbeat.
When no workaround is needed, it will use direct MMIO to memory space
to write to memory.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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Add complete support for 5714/5715. These chips are very similar to
5780 so the changes are very trivial. A TG3_FLG2_5780_CLASS flag is
added to identify these chips.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Test for VIA K8T800 north bridge instead of AMD K8 HyperTransport
bridge based on new information from Andi Kleen. The AMD
HyperTransport interface is not responsible for PCI transactions
and so the re-ordering is more likely done by the VIA north bridge.
This code is subject to change if we get more information from AMD
or VIA.
PCI Express devices are excluded from doing the read flush since all
chipsets in the write_reorder list are PCI chipsets.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Fix interrupt test handler by adding check for IRQ assertion in
PCI_STATE register in addition to the status block updated bit.
Add test for valid ethernet address in tg3_set_mac_addr().
Add tg3_bus_string() to setup the PCI bus speed/width string for all
PCI/PCIX/PCI Express devices. This is used to print the bus type
during init_one().
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Fix 5780 PHY related problems:
1. MAC_RX_MODE reset must be done before setting up the MAC_MODE
register on 5705_PLUS chips or the chip will stop receiving after
a while. The MAC_RX_MODE reset is needed to prevent intermittently
losing the first receive packet on serdes chips.
2. Skip MAC loopback test on 5780 because of hardware errata. Normal
traffic including PHY loopback is not affected by the errata.
3. PHY loopback fails intermittently on 5708S and this is fixed by
putting the PHY in loopback mode first before programming the MAC
mode register. A MAC_RX_MODE reset is also added.
4. Return -EINVAL in tg3_nway_reset() if device is in TBI mode. Allow
nway_reset if 5780S is in parallel detect mode.
5. Add missing PHY IDs in KNOWN_PHY_ID() macro.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Fix and simplify the workaround code for the 4GB boundary tx buffer
hardware bug.
1. Need to unmap the original SKB's dma addresses if a new SKB cannot
be allocated.
2. Need to pass the base flag to tigon3_4gb_hwbug_workaround() or TSO
won't work properly.
3. The guilty entry and length parameters for
tigon3_4gb_hwbug_workaround() are removed as they are not necessary.
4. Remove assumption that only one fragment can hit the 4GB boundary.
Another fragment can hit 8GB for example.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Change 0 to NULL where appropriate.
Signed-off-by: Peter Hagervall <hager@cs.umu.se>
Acked-by: Jeff Garzik <jgarzik@pobox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Thanks to Andy Stewart for the report and testing
debug patches from Michael Chan.
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Instead, count them as part of rx_missed_errors.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Use the status tag to determine if there are new events in
tg3_interrupt_tagged(). We discussed about this a while ago with Grant
Grundler and DaveM. This scheme makes it unnecessary to clear the
updated bit in the status block when using tagged mode, and only
a simple comparison is needed to determine if there are new events.
The tp->lock around netif_rx_complete() and tg3_restart_ints() is also
removed. It is unnecessary with DaveM's new locking scheme.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Remove unnecessary status block accesses in tg3_msi(). Since MSI is
not shared, it is unnecessary to read the status block to determine if
there are any new events in the MSI handler. It is also unnecessary to
clear the updated bit in the status block.
Since the poll list is per-cpu, tg3_poll() will be scheduled to run on
the same CPU that received the MSI. Prefetches for the status block
and the next rx descriptors are added in tg3_msi() to improve their
access times when tg3_poll() runs.
In the non-MSI irq handlers, we need to check the status block because
interrupts may be shared. Only prefetches for the next rx descriptors
are added.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Improve ethtool loopback self test by adding PHY loopback to the
existing MAC loopback test.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Minor SerDes bug fixes for 5780S and nvram bug fixes for 5780 and
5752.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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This is similar to Eric Dumazet's tx_lock patch for tg3 but takes it
one step further to eliminate the tx_lock in the tx_completion path
when the tx queue is not stopped.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Found a bug while reviewing the patches the second time.
The TG3_FLAG_TXD_MBOX_HWBUG flag is set after the register access
methods have been determined. This patch fixes it by moving it up before
the various access methods are assigned.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The register write to register 0x68 to restart interrupts is unnecessary
as the interrupt wasn't masked in that register by the irq handler. This
will save one register write in the fast path.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch adds the new workaround for 5703 A1/A2 if it is behind
certain ICH bridges. The workaround disables memory and uses config.
cycles only to access all registers. The 5702/03 chips can mistakenly
decode the special cycles from the ICH chipsets as memory write cycles,
causing corruption of register and memory space. Only certain ICH
bridges will drive special cycles with non-zero data during the address
phase which can fall within the 5703's address range. This is not an ICH
bug as the PCI spec allows non-zero address during special cycles.
However, only these ICH bridges are known to drive non-zero addresses
during special cycles.
The indirect_lock is also changed to spin_lock_irqsave from spin_lock_bh
because it is used in irq handler when using the indirect method to
disable interrupts.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch adds the mailbox read method and also adds an inline function
tw32_mailbox_f() for mailbox writes that require read flush.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch adds various dedicated register read/write methods for the
existing workarounds, including PCIX target workaround, write with read
flush, etc. The chips that require these workarounds will use these
dedicated access functions.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch adds the basic function pointers to do register accesses in
the fast path. This was suggested by David Miller. The idea is that
various register access methods for different hardware errata can easily
be implemented with these function pointers and performance will not be
degraded on chips that use normal register access methods.
The various register read write macros (e.g. tw32, tr32, tw32_mailbox)
are redefined to call the function pointers.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The tg3_abort_hw() call in tg3_test_loopback() is causing lockups on
some devices. tg3_abort_hw() disables the memory arbiter, causing
tg3_reset_hw() to hang when it tries to write the pre-reset signature.
tg3_abort_hw() should only be called after the pre-reset signature has
been written. This is all done in tg3_reset_hw() so the tg3_abort_hw()
call is unnecessary and can be removed.
[ Also bump driver version and release date. -DaveM ]
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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A problem was reported by Grant Grundler on an HP rx8620 using IOX
Core LAN partno(A7109-6) 5701 copper NIC. The tg3 driver mistakenly
detects this NIC as having a SerDes PHY and link does not come up as a
result.
The problem was caused by an incorrectly programmed eeprom that set the
NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit in the NIC_SRAM_DATA_CFG location.
This patch will override the NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit if a
valid PHY ID is read from the MII registers on older 570x chips where
the MII interface is not used on SerDes chips. On newer chips such as
the 5780 that use MII for both copper and SerDes, SerDes detection must
rely on the eeprom.
This patch will make the SerDes detection identical to versions 3.25 and
older.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Acked-by: Grant Grundler <iod00d@hp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Else on SMP systems it is possible for hotplug to execute,
invoke tg3_open(), and end up loading the uninitialized
PCI register save area into the card.
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Add 5780S support by adding a new tg3_setup_fiber_mii_phy() function and
a timer function for parallel link detection. 5780S uses standard MII
registers for 1000BaseX and runs in GMII mode as opposed to TBI mode on
older serdes chips.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Disallow jumbo TSO on 5780 due to hardware restrictions.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Consolidate all DMA watermark settings for standard and jumbo frames on
all chips in tg3_init_bufmgr_config() and add new settings for 5780.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add a new rx_pkt_buf_sz to the tg3 structure to support variable buffer
sizes on the standard ring.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add basic jumbo frames support for 5780. This chip supports jumbo frames
on the standard receive ring without the jumbo ring. The
TG3_FLAG_JUMBO_ENABLE is changed to TG3_FLAG_JUMBO_RING_ENABLE to
indicate using the jumbo ring on 5704 and older chips. A new
TG3_FLG2_JUMBO_CAPABLE flag is added to indicate jumbo frames support
with or without the jumbo ring.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add 5780 PCI IDs, chip IDs, and other basic support.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Add support for ethtool -C with verification of user parameters.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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1. Move tp->irq_sync = 0 to before the interrupt mailbox IO in
tg3_enable_ints() so that the interrupt handler will always see
irq_sync == 0 when interrupts are enabled.
2. Remove the tg3_enable_ints() call in tg3_reset_hw(). Interrupts are
always enabled explicitly or through tg3_netif_start(). This is to
prevent interrupts being enabled while poll is disabled.
3. Update trans_start with jiffies in tg3_netif_stop() to prevent false
NETDEV WATCHDOG.
4. Pass in the proper irq_sync parameter to tg3_full_lock() depending on
netif_running() in some of the ethtool set calls.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Move all driver spinlocks to be taken at sw IRQ
context only.
This fixes the skb_copy() we were doing with hw
IRQs disabled (which is illegal and triggers a
BUG() with HIGHMEM enabled). It also simplifies
the locking all over the driver tremendously.
We accomplish this feat by creating a special
sequence to synchronize with the hw IRQ handler
using a binary state and synchronize_irq().
This idea is from Herbert Xu.
Thanks to Michael Chan for helping to track down
all of the race conditions in initial versions
of this code.
Signed-off-by: David S. Miller <davem@davemloft.net>
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There must be a rmb() between reading the status block tag
and calling tg3_has_work(). This was missing in tg3_mis()
and tg3_interrupt_tagged(). tg3_poll() got it right.
Also, SD_STATUS_UPDATED must be cleared in the status block
right before we call tg3_has_work(). Only tg3_poll() got this
wrong.
Based upon patches and commentary from Grant Grundler and
Michael Chan.
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Fix 5700/5701 DMA write corruption on Apple G4 by detecting the Apple
UniNorth PCI 1.5 chipset and adjusting the DMA write boundary to 16. DMA
test fails to detect the problem with this chipset.
Thanks to Manuel Perez Ayala for reporting the problem and helping to
debug it.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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On some 5701 devices with older bootcode, the LED configuration bits in
SRAM may be invalid with value zero. The fix is to check for invalid
bits (0) and default to PHY 1 mode. Incorrect LED mode will lead to
error in programming the PHY.
Thanks to Grant Grundler for debugging the problem.
>From Grant:
| In May, 2004, tg3 v3.4 changed how MAC_LED_CTRL (0x40c) was getting
| programmed and how to determine what to program into LED_CTRL. The new
| code trusted NIC_SRAM_DATA_CFG (0x00000b58) to indicate what to write
| to LED_CTRL and MII EXT_CTRL registers. On "IOX Core Lan", SRAM was
| saying MODE_MAC (0x0) and that doesn't work.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add tg3_nvram_lock() and tg3_nvram_unlock() calls around tg3_halt_cpu().
It is possible that the bootcode may be loading code from nvram during
this call and stopping the cpu without getting the lock may cause
uncompleted nvram data to be left in the nvram data register. Subsequent
calls to read/write nvram data will fail.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This test uses the previously added tg3_test_interrupt() to perform the
test.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The test will loopback one packet in MAC loopback mode and verify the
packet data.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add a reset kind parameter to tg3_halt() so that the RESET_KIND_SUSPEND
parameter can be passed to tg3_halt() before doing offline tests.
All other calls to tg3_halt() will use the RESET_KIND_SHUTDOWN
parameter.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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This makes the DMA bug workaround test more likely
to find the problem on some systems.
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Add 0x1601 as 5752M, it's a 5752 but for mobile PCs.
Stolen from Broadcom bcm5700-8.1.55 driver.
Someone forgot to add it to tg3 ;-)
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Extract DMA boundary bit selection into a seperate
function, tg3_calc_dma_bndry(). Call this from
tg3_test_dma().
Make DMA test more reliable by using no DMA boundry
setting during the test. If the test passes, then
use the setting we selected before the test.
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Michael Chan <mchan@broadcom.com>
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Even though we do software interrupt mitigation
via NAPI, it still helps to have some minimal
hw assisted mitigation.
This helps, particularly, on systems where register
I/O overhead is much greater than the CPU horsepower.
For example, it helps on NUMA systems. In such cases
the PIO overhead to disable interrupts for NAPI accounts
for the majority of the packet processing cost. The
CPU is fast enough such that only a single packet is
processed by each NAPI poll call.
Thanks to Michael Chan for reviewing this patch.
Signed-off-by: David S. Miller <davem@davemloft.net>
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When supported, use the TAGGED interrupt processing support
the chip provides. In this mode, instead of a "on/off" binary
semaphore, an incrementing tag scheme is used to ACK interrupts.
All MSI supporting chips support TAGGED mode, so the tg3_msi()
interrupt handler uses it unconditionally. This invariant is
verified when MSI support is tested.
Since we can invoke tg3_poll() multiple times per interrupt under
high packet load, we fetch a new copy of the tag value in the
status block right before we actually do the work.
Also, because the tagged status tells the chip exactly which
work we have processed, we can make two optimizations:
1) tg3_restart_ints() need not check tg3_has_work()
2) the tg3_timer() need not poke the chip 10 times per
second to keep from losing interrupt events
Based upon valuable feedback from Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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tg3_stop_block() errors can be safely ignored since tg3_chip_reset()
always follows tg3_stop_block() calls.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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tg3_restart_ints() is called to re-enable interrupts after tg3_poll()
has finished all the work. It calls tg3_cond_int() to force an interrupt
if the status block updated bit is set. The updated bit will be set if
there is a new status block update sometime during tg3_poll() and it can
be very often. The worst part is that even if all the work has been
processed, the updated bit remains set and an interrupt will be forced
unnecessarily.
The fix is to call tg3_has_work() instead to determine if new work is
posted before forcing an interrupt. The way to force an interrupt is
also changed to use "coalesce_now" instead of "SETINT". The former is
generally a safer way to force the interrupt.
Also deleted the first parameter to tg3_has_work() which is unused.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch refreshes the hw rx producer in tg3_rx() so that additional
work posted by the hardware can be processed.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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This patch fixes a bug that causes tg3_has_work() to always return 1.
rx work is determined by comparing tp->rx_rcb_ptr with the current hw
producer index. The hw producer index is modulo the ring size, but tp-
>rx_rcb_ptr is a free running counter that goes up beyond the ring size.
After the ring wraps around once, tg3_has_work() will always return 1.
The fix is to always do modulo arithmetic on tp->rx_rcb_ptr.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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Add MSI test for chips that support MSI. If MSI test fails, it will
switch back to INTx mode and will print a message asking the user to
report the failure.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add MSI support for 5751 C0 and 5752.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Fix a bug in tg3_set_eeprom() when the length is less than 4 and the
offset is not 4-byte aligned.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add support for the NVRAM lock-out feature for TPM in 5752. If lock-out
is enabled, certain NVRAM registers cannot be written to.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add bit definitions for the new GPIO3 in 5752. GPIO3 must be driven as
output when it is unused.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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The 5752 A0 chip ID is wrong in hardware. The simplest way to workaround
it is to change it to the correct value in tp->pci_chip_rev_id. This
way, it is easier to check for the ASIC_REV_5752 in the rest of the
driver.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Fix tg3_set_power_state to drive GPIOs properly based on the
TG3_FLAG_EEPROM_WRITE_PROTECT flag. Some delays are also added after D0
and D3 power state changes.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Setup proper GPIO settings in tp->grc_local_ctrl before calling
tg3_set_power() state in tg3_get_invariants() and after chip reset.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Split the 1st half of tg3_phy_probe() into tg3_get_eeprom_hw_cfg() so
that the TG3_FLAG_EEPROM_WRITE_PROT can be determined before calling
tg3_set_power_state() in tg3_get_invariants(). This will allow
tg3_set_power_state() to drive the GPIOs correctly based on the config.
information in eeprom.
On the 5752, there are no pull-up resistors on the GPIO pins and it is
necessary to drive the unused GPIOs as output.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Some minor 5752 fixes mostly for correctness and add 5752 PHY ID.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Replace existing ASIC_REV_5752 definition with ASIC_REV_5752_A0,
and add definition for ASIC_REV_5752_A1. Then, add ASIC_REV_5752_A1
to check for setting TG3_FLG2_5750_PLUS in tg3_get_invariants.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Use check of TG3_FLG2_5750_PLUS in tg3_get_invariants to set
TG3_FLG2_5705_PLUS flag.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Rewrite checks in tg3_get_invariants to use TG3_FLG2_5705_PLUS and
TG3_FLG2_5750_PLUS flags.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Rewrite of a couple of troublesome multi-way if statements to use
TG3_FLG2_5705_PLUS flag.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Replace a number of two-way if statements checking for 5750, and/or
5752 to reference the newly-defined TG3_FLG2_5750_PLUS flag instead.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Define TG3_FLG2_5750_PLUS flag and set it in tg3_get_invariants for
ASIC_REV_5750 or ASIC_REV_5752.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Replace a number of three-way if statements checking for 5705, 5750,
and 5752 to reference the equivalent TG3_FLG2_5705_PLUS flag instead.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add proper entry for bcm5752 PCI ID to pci_ids.h, and use it in tg3.
I did this separately in case patches like this (i.e. new PCI IDs)
need to come from more "official" sources.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add hard-coded definition of bcm5752 PCI ID to tg3_pci_tbl.
Next patch will change entry to use pci_ids.h-based definition.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add ASIC_REV_5752 definition.
Track-down all references to ASIC_REV_5750 and mirror them with
references to the newly defined ASIC_REV_5752.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
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