diff options
143 files changed, 3017 insertions, 5453 deletions
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 2ea080c958bbd..b6b1f5ab5354b 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt @@ -17,21 +17,6 @@ Who: Greg Kroah-Hartman <greg@kroah.com> --------------------------- -What: /proc/sys/cpu/*, sysctl and /proc/cpufreq interfaces to cpufreq (2.4.x interfaces) -When: January 2005 -Files: drivers/cpufreq/: cpufreq_userspace.c, proc_intf.c -Why: /proc/sys/cpu/* has been deprecated since inclusion of cpufreq into - the main kernel tree. It bloats /proc/ unnecessarily and doesn't work - well with the "governor"-based design of cpufreq. - /proc/cpufreq/* has also been deprecated for a long time and was only - meant for usage during 2.5. until the new sysfs-based interface became - ready. It has an inconsistent interface which doesn't work well with - userspace setting the frequency. The output from /proc/cpufreq/* can - be emulated using "cpufreq-info --proc" (cpufrequtils). - Both interfaces are superseded by the cpufreq interface in - /sys/devices/system/cpu/cpu%n/cpufreq/. -Who: Dominik Brodowski <linux@brodo.de> - What: ACPI S4bios support When: May 2005 Why: Noone uses it, and it probably does not work, anyway. swsusp is @@ -40,6 +25,15 @@ Who: Pavel Machek <pavel@suse.cz> --------------------------- +What: PCI Name Database (CONFIG_PCI_NAMES) +When: July 2005 +Why: It bloats the kernel unnecessarily, and is handled by userspace better + (pciutils supports it.) Will eliminate the need to try to keep the + pci.ids file in sync with the sf.net database all of the time. +Who: Greg Kroah-Hartman <gregkh@suse.de> + +--------------------------- + What: io_remap_page_range() (macro or function) When: September 2005 Why: Replaced by io_remap_pfn_range() which allows more memory space diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig index 7f5df795881df..692af6b5e8ff2 100644 --- a/arch/arm/common/Kconfig +++ b/arch/arm/common/Kconfig @@ -17,5 +17,8 @@ config TIMER_ACORN config SHARP_LOCOMO bool +config SHARP_PARAM + bool + config SHARP_SCOOP bool diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile index ba4a9d3957cce..11f20a43ee3aa 100644 --- a/arch/arm/common/Makefile +++ b/arch/arm/common/Makefile @@ -11,4 +11,5 @@ obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o obj-$(CONFIG_DMABOUNCE) += dmabounce.o obj-$(CONFIG_TIMER_ACORN) += time-acorn.o obj-$(CONFIG_SHARP_LOCOMO) += locomo.o +obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o obj-$(CONFIG_SHARP_SCOOP) += scoop.o diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 37a39f229236d..21fce3414ed1e 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -800,7 +800,7 @@ struct sa1111_save_data { #ifdef CONFIG_PM -static int sa1111_suspend(struct device *dev, u32 state, u32 level) +static int sa1111_suspend(struct device *dev, pm_message_t state, u32 level) { struct sa1111 *sachip = dev_get_drvdata(dev); struct sa1111_save_data *save; diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c new file mode 100644 index 0000000000000..c2c557a224c2a --- /dev/null +++ b/arch/arm/common/sharpsl_param.c @@ -0,0 +1,60 @@ +/* + * Hardware parameter area specific to Sharp SL series devices + * + * Copyright (c) 2005 Richard Purdie + * + * Based on Sharp's 2.4 kernel patches + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/kernel.h> +#include <linux/string.h> +#include <asm/mach/sharpsl_param.h> + +/* + * Certain hardware parameters determined at the time of device manufacture, + * typically including LCD parameters are loaded by the bootloader at the + * address PARAM_BASE. As the kernel will overwrite them, we need to store + * them early in the boot process, then pass them to the appropriate drivers. + * Not all devices use all paramaters but the format is common to all. + */ +#ifdef ARCH_SA1100 +#define PARAM_BASE 0xe8ffc000 +#else +#define PARAM_BASE 0xa0000a00 +#endif +#define MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 ) | ( b << 8 ) | a ) + +#define COMADJ_MAGIC MAGIC_CHG('C','M','A','D') +#define UUID_MAGIC MAGIC_CHG('U','U','I','D') +#define TOUCH_MAGIC MAGIC_CHG('T','U','C','H') +#define AD_MAGIC MAGIC_CHG('B','V','A','D') +#define PHAD_MAGIC MAGIC_CHG('P','H','A','D') + +struct sharpsl_param_info sharpsl_param; + +void sharpsl_save_param(void) +{ + memcpy(&sharpsl_param, (void *)PARAM_BASE, sizeof(struct sharpsl_param_info)); + + if (sharpsl_param.comadj_keyword != COMADJ_MAGIC) + sharpsl_param.comadj=-1; + + if (sharpsl_param.phad_keyword != PHAD_MAGIC) + sharpsl_param.phadadj=-1; + + if (sharpsl_param.uuid_keyword != UUID_MAGIC) + sharpsl_param.uuid[0]=-1; + + if (sharpsl_param.touch_keyword != TOUCH_MAGIC) + sharpsl_param.touch_xp=-1; + + if (sharpsl_param.adadj_keyword != AD_MAGIC) + sharpsl_param.adadj=-1; +} + + diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index 3c62021fc838c..c232f24f4a600 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c @@ -178,7 +178,7 @@ static ssize_t leds_store(struct sys_device *dev, const char *buf, size_t size) static SYSDEV_ATTR(event, 0200, NULL, leds_store); -static int leds_suspend(struct sys_device *dev, u32 state) +static int leds_suspend(struct sys_device *dev, pm_message_t state) { leds_event(led_stop); return 0; @@ -351,7 +351,7 @@ void timer_tick(struct pt_regs *regs) } #ifdef CONFIG_PM -static int timer_suspend(struct sys_device *dev, u32 state) +static int timer_suspend(struct sys_device *dev, pm_message_t state) { struct sys_timer *timer = container_of(dev, struct sys_timer, dev); diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index 219ae5080a307..91ba9fd79c87c 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c @@ -137,7 +137,7 @@ static void __init ap_init_irq(void) #ifdef CONFIG_PM static unsigned long ic_irq_enable; -static int irq_suspend(struct sys_device *dev, u32 state) +static int irq_suspend(struct sys_device *dev, pm_message_t state) { ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE); return 0; diff --git a/arch/arm/mach-integrator/time.c b/arch/arm/mach-integrator/time.c index 249581f88f5ec..20729de2af285 100644 --- a/arch/arm/mach-integrator/time.c +++ b/arch/arm/mach-integrator/time.c @@ -158,7 +158,7 @@ static int rtc_remove(struct amba_device *dev) static struct timespec rtc_delta; -static int rtc_suspend(struct amba_device *dev, u32 state) +static int rtc_suspend(struct amba_device *dev, pm_message_t state) { struct timespec rtc; diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index c437660bf92f8..405a55f2287cc 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig @@ -23,6 +23,7 @@ config PXA_SHARPSL bool "SHARP SL-5600 and SL-C7xx Models" select PXA25x select SHARP_SCOOP + select SHARP_PARAM help Say Y here if you intend to run this kernel on a Sharp SL-5600 (Poodle), Sharp SL-C700 (Corgi), diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 94841068a688e..f691cf77d3908 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c @@ -37,6 +37,7 @@ #include <asm/arch/udc.h> #include <asm/arch/corgi.h> +#include <asm/mach/sharpsl_param.h> #include <asm/hardware/scoop.h> #include <video/w100fb.h> @@ -231,28 +232,10 @@ static struct platform_device *devices[] __initdata = { &corgibl_device, }; -static struct sharpsl_flash_param_info sharpsl_flash_param; - -static void corgi_get_param(void) -{ - sharpsl_flash_param.comadj_keyword = readl(FLASH_MEM_BASE + FLASH_COMADJ_MAGIC_ADR); - sharpsl_flash_param.comadj = readl(FLASH_MEM_BASE + FLASH_COMADJ_DATA_ADR); - - sharpsl_flash_param.phad_keyword = readl(FLASH_MEM_BASE + FLASH_PHAD_MAGIC_ADR); - sharpsl_flash_param.phadadj = readl(FLASH_MEM_BASE + FLASH_PHAD_DATA_ADR); -} - static void __init corgi_init(void) { - if (sharpsl_flash_param.comadj_keyword == FLASH_COMADJ_MAJIC) - corgi_fb_info.comadj=sharpsl_flash_param.comadj; - else - corgi_fb_info.comadj=-1; - - if (sharpsl_flash_param.phad_keyword == FLASH_PHAD_MAJIC) - corgi_fb_info.phadadj=sharpsl_flash_param.phadadj; - else - corgi_fb_info.phadadj=-1; + corgi_fb_info.comadj=sharpsl_param.comadj; + corgi_fb_info.phadadj=sharpsl_param.phadadj; pxa_gpio_mode(CORGI_GPIO_USB_PULLUP | GPIO_OUT); pxa_set_udc_info(&udc_info); @@ -264,7 +247,7 @@ static void __init corgi_init(void) static void __init fixup_corgi(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { - corgi_get_param(); + sharpsl_save_param(); mi->nr_banks=1; mi->bank[0].start = 0xa0000000; mi->bank[0].node = 0; diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index 9e01883025d6a..8ccffba0018fa 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c @@ -210,7 +210,7 @@ static int corgi_ssp_remove(struct device *dev) return 0; } -static int corgi_ssp_suspend(struct device *dev, u32 state, u32 level) +static int corgi_ssp_suspend(struct device *dev, pm_message_t state, u32 level) { if (level == SUSPEND_POWER_DOWN) { ssp_flush(&corgi_ssp_dev); diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index 5ee67808224a9..b6c746ea38305 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c @@ -35,6 +35,7 @@ #include <asm/hardware/scoop.h> #include <asm/hardware/locomo.h> +#include <asm/mach/sharpsl_param.h> #include "generic.h" @@ -152,6 +153,12 @@ static void __init poodle_init(void) } } +static void __init fixup_poodle(struct machine_desc *desc, + struct tag *tags, char **cmdline, struct meminfo *mi) +{ + sharpsl_save_param(); +} + static struct map_desc poodle_io_desc[] __initdata = { /* virtual physical length */ { 0xef800000, 0x00000000, 0x00800000, MT_DEVICE }, /* Boot Flash */ @@ -174,6 +181,7 @@ static void __init poodle_map_io(void) MACHINE_START(POODLE, "SHARP Poodle") BOOT_MEM(0xa0000000, 0x40000000, io_p2v(0x40000000)) + FIXUP(fixup_poodle) MAPIO(poodle_map_io) INITIRQ(pxa_init_irq) .timer = &pxa_timer, diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 5ecfa58371160..bc229fab86d44 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c @@ -1092,7 +1092,7 @@ EXPORT_SYMBOL(s3c2410_dma_getposition); #ifdef CONFIG_PM -static int s3c2410_dma_suspend(struct sys_device *dev, u32 state) +static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state) { s3c2410_dma_chan_t *cp = container_of(dev, s3c2410_dma_chan_t, dev); diff --git a/arch/arm/mach-s3c2410/mach-rx3715.c b/arch/arm/mach-s3c2410/mach-rx3715.c index 26e2d86cdd03c..f8d3a9784e711 100644 --- a/arch/arm/mach-s3c2410/mach-rx3715.c +++ b/arch/arm/mach-s3c2410/mach-rx3715.c @@ -54,6 +54,16 @@ static struct map_desc rx3715_iodesc[] __initdata = { { (u32)S3C24XX_VA_ISA_BYTE, S3C2410_CS3, SZ_16M, MT_DEVICE }, }; + +static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { + [0] = { + .name = "fclk", + .divisor = 0, + .min_baud = 0, + .max_baud = 0, + } +}; + static struct s3c2410_uartcfg rx3715_uartcfgs[] = { [0] = { .hwport = 0, @@ -61,6 +71,8 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x51, + .clocks = rx3715_serial_clocks, + .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), }, [1] = { .hwport = 1, @@ -68,6 +80,8 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x00, + .clocks = rx3715_serial_clocks, + .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), }, /* IR port */ [2] = { @@ -76,6 +90,8 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x43, .ufcon = 0x51, + .clocks = rx3715_serial_clocks, + .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), } }; diff --git a/arch/arm/mach-s3c2410/s3c2440.c b/arch/arm/mach-s3c2410/s3c2440.c index 7799d81494615..9a8cc5ae22556 100644 --- a/arch/arm/mach-s3c2410/s3c2440.c +++ b/arch/arm/mach-s3c2410/s3c2440.c @@ -159,7 +159,7 @@ struct sleep_save s3c2440_sleep[] = { SAVE_ITEM(S3C2440_GPJUP) }; -static int s3c2440_suspend(struct sys_device *dev, u32 state) +static int s3c2440_suspend(struct sys_device *dev, pm_message_t state) { s3c2410_pm_do_save(s3c2440_sleep, ARRAY_SIZE(s3c2440_sleep)); return 0; diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index 5178cde08ab96..50cde576dadfc 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig @@ -47,6 +47,7 @@ config SA1100_COLLIE bool "Sharp Zaurus SL5500" select SHARP_LOCOMO select SHARP_SCOOP + select SHARP_PARAM help Say Y here to support the Sharp Zaurus SL5500 PDAs. diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index da9412c5d385e..99287890d3964 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c @@ -38,6 +38,7 @@ #include <asm/mach/serial_sa1100.h> #include <asm/hardware/scoop.h> +#include <asm/mach/sharpsl_param.h> #include <asm/hardware/locomo.h> #include "generic.h" @@ -166,6 +167,8 @@ static void __init collie_init(void) sa11x0_set_flash_data(&collie_flash_data, collie_flash_resources, ARRAY_SIZE(collie_flash_resources)); + + sharpsl_save_param(); } static struct map_desc collie_io_desc[] __initdata = { diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c index 64dd21cfba431..66a929cb7bc5b 100644 --- a/arch/arm/mach-sa1100/irq.c +++ b/arch/arm/mach-sa1100/irq.c @@ -218,7 +218,7 @@ static struct sa1100irq_state { unsigned int iccr; } sa1100irq_state; -static int sa1100irq_suspend(struct sys_device *dev, u32 state) +static int sa1100irq_suspend(struct sys_device *dev, pm_message_t state) { struct sa1100irq_state *st = &sa1100irq_state; diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c index 6ffa50151a8c3..1405383463ea7 100644 --- a/arch/arm/mach-sa1100/neponset.c +++ b/arch/arm/mach-sa1100/neponset.c @@ -178,7 +178,7 @@ static int neponset_probe(struct device *dev) /* * LDM power management. */ -static int neponset_suspend(struct device *dev, u32 state, u32 level) +static int neponset_suspend(struct device *dev, pm_message_t state, u32 level) { /* * Save state. diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c index 615a3ccfea5cb..e57dde8828981 100644 --- a/arch/arm/oprofile/common.c +++ b/arch/arm/oprofile/common.c @@ -26,7 +26,7 @@ static void pmu_stop(void); static int pmu_create_files(struct super_block *, struct dentry *); #ifdef CONFIG_PM -static int pmu_suspend(struct sys_device *dev, u32 state) +static int pmu_suspend(struct sys_device *dev, pm_message_t state) { if (pmu_enabled) pmu_stop(); diff --git a/arch/frv/mb93090-mb00/pci-frv.c b/arch/frv/mb93090-mb00/pci-frv.c index c5a7f78bf5f98..83e5489cf039a 100644 --- a/arch/frv/mb93090-mb00/pci-frv.c +++ b/arch/frv/mb93090-mb00/pci-frv.c @@ -31,7 +31,7 @@ pcibios_update_resource(struct pci_dev *dev, struct resource *root, if (resource < 6) { reg = PCI_BASE_ADDRESS_0 + 4*resource; } else if (resource == PCI_ROM_RESOURCE) { - res->flags |= PCI_ROM_ADDRESS_ENABLE; + res->flags |= IORESOURCE_ROM_ENABLE; new |= PCI_ROM_ADDRESS_ENABLE; reg = dev->rom_base_reg; } else { @@ -170,11 +170,11 @@ static void __init pcibios_allocate_resources(int pass) } if (!pass) { r = &dev->resource[PCI_ROM_RESOURCE]; - if (r->flags & PCI_ROM_ADDRESS_ENABLE) { + if (r->flags & IORESOURCE_ROM_ENABLE) { /* Turn the ROM off, leave the resource region, but keep it unregistered. */ u32 reg; DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); - r->flags &= ~PCI_ROM_ADDRESS_ENABLE; + r->flags &= ~IORESOURCE_ROM_ENABLE; pci_read_config_dword(dev, dev->rom_base_reg, ®); pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE); } diff --git a/arch/i386/pci/i386.c b/arch/i386/pci/i386.c index 7a7b35a375d8d..c205ea7e233bc 100644 --- a/arch/i386/pci/i386.c +++ b/arch/i386/pci/i386.c @@ -124,7 +124,7 @@ static void __init pcibios_allocate_resources(int pass) u16 command; struct resource *r, *pr; - while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + for_each_pci_dev(dev) { pci_read_config_word(dev, PCI_COMMAND, &command); for(idx = 0; idx < 6; idx++) { r = &dev->resource[idx]; @@ -150,11 +150,11 @@ static void __init pcibios_allocate_resources(int pass) } if (!pass) { r = &dev->resource[PCI_ROM_RESOURCE]; - if (r->flags & PCI_ROM_ADDRESS_ENABLE) { + if (r->flags & IORESOURCE_ROM_ENABLE) { /* Turn the ROM off, leave the resource region, but keep it unregistered. */ u32 reg; DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); - r->flags &= ~PCI_ROM_ADDRESS_ENABLE; + r->flags &= ~IORESOURCE_ROM_ENABLE; pci_read_config_dword(dev, dev->rom_base_reg, ®); pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE); } @@ -168,7 +168,7 @@ static int __init pcibios_assign_resources(void) int idx; struct resource *r; - while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { + for_each_pci_dev(dev) { int class = dev->class >> 8; /* Don't touch classless devices and host bridges */ diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c index ca811853e87f5..dad228d3a220e 100644 --- a/arch/mips/pmc-sierra/yosemite/ht.c +++ b/arch/mips/pmc-sierra/yosemite/ht.c @@ -361,7 +361,7 @@ void pcibios_update_resource(struct pci_dev *dev, struct resource *root, if (resource < 6) { reg = PCI_BASE_ADDRESS_0 + 4 * resource; } else if (resource == PCI_ROM_RESOURCE) { - res->flags |= PCI_ROM_ADDRESS_ENABLE; + res->flags |= IORESOURCE_ROM_ENABLE; reg = dev->rom_base_reg; } else { /* diff --git a/arch/ppc/kernel/pci.c b/arch/ppc/kernel/pci.c index b8f67396ec48d..98f94b60204cc 100644 --- a/arch/ppc/kernel/pci.c +++ b/arch/ppc/kernel/pci.c @@ -521,11 +521,11 @@ pcibios_allocate_resources(int pass) if (pass) continue; r = &dev->resource[PCI_ROM_RESOURCE]; - if (r->flags & PCI_ROM_ADDRESS_ENABLE) { + if (r->flags & IORESOURCE_ROM_ENABLE) { /* Turn the ROM off, leave the resource region, but keep it unregistered. */ u32 reg; DBG("PCI: Switching off ROM of %s\n", pci_name(dev)); - r->flags &= ~PCI_ROM_ADDRESS_ENABLE; + r->flags &= ~IORESOURCE_ROM_ENABLE; pci_read_config_dword(dev, dev->rom_base_reg, ®); pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE); diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 363bc839b2840..c1669905abe4d 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -57,7 +57,7 @@ pcibios_update_resource(struct pci_dev *dev, struct resource *root, if (resource < 6) { reg = PCI_BASE_ADDRESS_0 + 4*resource; } else if (resource == PCI_ROM_RESOURCE) { - res->flags |= PCI_ROM_ADDRESS_ENABLE; + res->flags |= IORESOURCE_ROM_ENABLE; new |= PCI_ROM_ADDRESS_ENABLE; reg = dev->rom_base_reg; } else { diff --git a/arch/sh64/kernel/pcibios.c b/arch/sh64/kernel/pcibios.c index 4f707dfd5dc18..50c61dcb9faee 100644 --- a/arch/sh64/kernel/pcibios.c +++ b/arch/sh64/kernel/pcibios.c @@ -45,7 +45,7 @@ pcibios_update_resource(struct pci_dev *dev, struct resource *root, if (resource < 6) { reg = PCI_BASE_ADDRESS_0 + 4*resource; } else if (resource == PCI_ROM_RESOURCE) { - res->flags |= PCI_ROM_ADDRESS_ENABLE; + res->flags |= IORESOURCE_ROM_ENABLE; new |= PCI_ROM_ADDRESS_ENABLE; reg = dev->rom_base_reg; } else { diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c index 8c66349f316b2..c89a803cbc20d 100644 --- a/arch/sparc/mm/srmmu.c +++ b/arch/sparc/mm/srmmu.c @@ -161,6 +161,9 @@ static inline int srmmu_pte_none(pte_t pte) static inline int srmmu_pte_present(pte_t pte) { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); } +static inline int srmmu_pte_read(pte_t pte) +{ return !(pte_val(pte) & SRMMU_NOREAD); } + static inline void srmmu_pte_clear(pte_t *ptep) { srmmu_set_pte(ptep, __pte(0)); } @@ -2166,6 +2169,7 @@ void __init ld_mmu_srmmu(void) BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0); + BTFIXUPSET_CALL(pte_read, srmmu_pte_read, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM); @@ -2196,7 +2200,6 @@ void __init ld_mmu_srmmu(void) BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM); - BTFIXUPSET_HALF(pte_readi, SRMMU_NOREAD); BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE); BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY); BTFIXUPSET_HALF(pte_youngi, SRMMU_REF); diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c index 03342120f1f85..1d560390e2821 100644 --- a/arch/sparc/mm/sun4c.c +++ b/arch/sparc/mm/sun4c.c @@ -1746,6 +1746,11 @@ static int sun4c_pte_present(pte_t pte) } static void sun4c_pte_clear(pte_t *ptep) { *ptep = __pte(0); } +static int sun4c_pte_read(pte_t pte) +{ + return (pte_val(pte) & _SUN4C_PAGE_READ); +} + static int sun4c_pmd_bad(pmd_t pmd) { return (((pmd_val(pmd) & ~PAGE_MASK) != PGD_TABLE) || @@ -2199,6 +2204,7 @@ void __init ld_mmu_sun4c(void) BTFIXUPSET_CALL(pte_present, sun4c_pte_present, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(pte_clear, sun4c_pte_clear, BTFIXUPCALL_STG0O0); + BTFIXUPSET_CALL(pte_read, sun4c_pte_read, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(pmd_bad, sun4c_pmd_bad, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(pmd_present, sun4c_pmd_present, BTFIXUPCALL_NORM); @@ -2225,7 +2231,6 @@ void __init ld_mmu_sun4c(void) BTFIXUPSET_CALL(free_pgd_fast, sun4c_free_pgd_fast, BTFIXUPCALL_NORM); BTFIXUPSET_CALL(get_pgd_fast, sun4c_get_pgd_fast, BTFIXUPCALL_NORM); - BTFIXUPSET_HALF(pte_readi, _SUN4C_PAGE_READ); BTFIXUPSET_HALF(pte_writei, _SUN4C_PAGE_WRITE); BTFIXUPSET_HALF(pte_dirtyi, _SUN4C_PAGE_MODIFIED); BTFIXUPSET_HALF(pte_youngi, _SUN4C_PAGE_ACCESSED); diff --git a/arch/sparc64/Kconfig b/arch/sparc64/Kconfig index b31687f3e7214..46a2436c9600c 100644 --- a/arch/sparc64/Kconfig +++ b/arch/sparc64/Kconfig @@ -16,6 +16,33 @@ config TIME_INTERPOLATION bool default y +choice + prompt "Kernel page size" + default SPARC64_PAGE_SIZE_8KB + +config SPARC64_PAGE_SIZE_8KB + bool "8KB" + help + This lets you select the page size of the kernel. + + 8KB and 64KB work quite well, since Sparc ELF sections + provide for up to 64KB alignment. + + Therefore, 512KB and 4MB are for expert hackers only. + + If you don't know what to do, choose 8KB. + +config SPARC64_PAGE_SIZE_64KB + bool "64KB" + +config SPARC64_PAGE_SIZE_512KB + bool "512KB" + +config SPARC64_PAGE_SIZE_4MB + bool "4MB" + +endchoice + source "init/Kconfig" config SYSVIPC_COMPAT @@ -198,9 +225,11 @@ config HUGETLB_PAGE_SIZE_4MB bool "4MB" config HUGETLB_PAGE_SIZE_512K + depends on !SPARC64_PAGE_SIZE_4MB bool "512K" config HUGETLB_PAGE_SIZE_64K + depends on !SPARC64_PAGE_SIZE_4MB && !SPARC64_PAGE_SIZE_512K bool "64K" endchoice diff --git a/arch/sparc64/Makefile b/arch/sparc64/Makefile index 61724880f20d3..43fe382da0789 100644 --- a/arch/sparc64/Makefile +++ b/arch/sparc64/Makefile @@ -41,10 +41,10 @@ endif ifneq ($(NEW_GCC),y) CFLAGS := $(CFLAGS) -pipe -mno-fpu -mtune=ultrasparc -mmedlow \ - -ffixed-g4 -fcall-used-g5 -fcall-used-g7 -Wno-sign-compare + -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare else CFLAGS := $(CFLAGS) -m64 -pipe -mno-fpu -mcpu=ultrasparc -mcmodel=medlow \ - -ffixed-g4 -fcall-used-g5 -fcall-used-g7 -Wno-sign-compare \ + -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare \ $(CC_UNDECL) AFLAGS += -m64 -mcpu=ultrasparc $(CC_UNDECL) endif diff --git a/arch/sparc64/kernel/cpu.c b/arch/sparc64/kernel/cpu.c index 9043e2e03a1f4..48756958116b5 100644 --- a/arch/sparc64/kernel/cpu.c +++ b/arch/sparc64/kernel/cpu.c @@ -38,6 +38,7 @@ struct cpu_fp_info linux_sparc_fpu[] = { { 0x3e, 0x14, 0, "UltraSparc III integrated FPU"}, { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"}, { 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"}, + { 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"}, }; #define NSPARCFPU (sizeof(linux_sparc_fpu)/sizeof(struct cpu_fp_info)) @@ -51,6 +52,7 @@ struct cpu_iu_info linux_sparc_chips[] = { { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"}, { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"}, { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"}, + { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"}, }; #define NSPARCCHIPS (sizeof(linux_sparc_chips)/sizeof(struct cpu_iu_info)) diff --git a/arch/sparc64/kernel/dtlb_backend.S b/arch/sparc64/kernel/dtlb_backend.S index e6bc4a26aeb9b..b73a3c8587704 100644 --- a/arch/sparc64/kernel/dtlb_backend.S +++ b/arch/sparc64/kernel/dtlb_backend.S @@ -7,60 +7,143 @@ */ #include <asm/pgtable.h> -#include <asm/mmu_context.h> +#include <asm/mmu.h> #if PAGE_SHIFT == 13 -#define FILL_VALID_SZ_BITS1(r1) \ - sllx %g2, 62, r1 -#define FILL_VALID_SZ_BITS2(r1) -#define FILL_VALID_SZ_BITS_NOP nop +#define SZ_BITS _PAGE_SZ8K #elif PAGE_SHIFT == 16 -#define FILL_VALID_SZ_BITS1(r1) \ - or %g0, 5, r1 -#define FILL_VALID_SZ_BITS2(r1) \ - sllx r1, 61, r1 -#define FILL_VALID_SZ_BITS_NOP -#else -#error unsupported PAGE_SIZE -#endif /* PAGE_SHIFT */ +#define SZ_BITS _PAGE_SZ64K +#elif PAGE_SHIFT == 19 +#define SZ_BITS _PAGE_SZ512K +#elif PAGE_SHIFT == 22 +#define SZ_BITS _PAGE_SZ4M +#endif + +#define VALID_SZ_BITS (_PAGE_VALID | SZ_BITS) #define VPTE_BITS (_PAGE_CP | _PAGE_CV | _PAGE_P ) #define VPTE_SHIFT (PAGE_SHIFT - 3) -#define TLB_PMD_SHIFT (PAGE_SHIFT - 3 + 3) -#define TLB_PGD_SHIFT (PMD_BITS + PAGE_SHIFT - 3 + 3) -#define TLB_PMD_MASK (((1 << PMD_BITS) - 1) << 1) -#define TLB_PGD_MASK (((1 << (VA_BITS - PAGE_SHIFT - (PAGE_SHIFT - 3) - PMD_BITS)) - 1) << 2) /* Ways we can get here: * * 1) Nucleus loads and stores to/from PA-->VA direct mappings at tl>1. * 2) Nucleus loads and stores to/from user/kernel window save areas. * 3) VPTE misses from dtlb_base and itlb_base. + * + * We need to extract out the PMD and PGDIR indexes from the + * linear virtual page table access address. The PTE index + * is at the bottom, but we are not concerned with it. Bits + * 0 to 2 are clear since each PTE is 8 bytes in size. Each + * PMD and PGDIR entry are 4 bytes in size. Thus, this + * address looks something like: + * + * |---------------------------------------------------------------| + * | ... | PGDIR index | PMD index | PTE index | | + * |---------------------------------------------------------------| + * 63 F E D C B A 3 2 0 <- bit nr + * + * The variable bits above are defined as: + * A --> 3 + (PAGE_SHIFT - log2(8)) + * --> 3 + (PAGE_SHIFT - 3) - 1 + * (ie. this is "bit 3" + PAGE_SIZE - size of PTE entry in bits - 1) + * B --> A + 1 + * C --> B + (PAGE_SHIFT - log2(4)) + * --> B + (PAGE_SHIFT - 2) - 1 + * (ie. this is "bit B" + PAGE_SIZE - size of PMD entry in bits - 1) + * D --> C + 1 + * E --> D + (PAGE_SHIFT - log2(4)) + * --> D + (PAGE_SHIFT - 2) - 1 + * (ie. this is "bit D" + PAGE_SIZE - size of PGDIR entry in bits - 1) + * F --> E + 1 + * + * (Note how "B" always evalutes to PAGE_SHIFT, all the other constants + * cancel out.) + * + * For 8K PAGE_SIZE (thus, PAGE_SHIFT of 13) the bit numbers are: + * A --> 12 + * B --> 13 + * C --> 23 + * D --> 24 + * E --> 34 + * F --> 35 + * + * For 64K PAGE_SIZE (thus, PAGE_SHIFT of 16) the bit numbers are: + * A --> 15 + * B --> 16 + * C --> 29 + * D --> 30 + * E --> 43 + * F --> 44 + * + * Because bits both above and below each PGDIR and PMD index need to + * be masked out, and the index can be as long as 14 bits (when using a + * 64K PAGE_SIZE, and thus a PAGE_SHIFT of 16), we need 3 instructions + * to extract each index out. + * + * Shifts do not pair very well on UltraSPARC-I, II, IIi, and IIe, so + * we try to avoid using them for the entire operation. We could setup + * a mask anywhere from bit 31 down to bit 10 using the sethi instruction. + * + * We need a mask covering bits B --> C and one covering D --> E. + * For 8K PAGE_SIZE these masks are 0x00ffe000 and 0x7ff000000. + * For 64K PAGE_SIZE these masks are 0x3fff0000 and 0xfffc0000000. + * The second in each set cannot be loaded with a single sethi + * instruction, because the upper bits are past bit 32. We would + * need to use a sethi + a shift. + * + * For the time being, we use 2 shifts and a simple "and" mask. + * We shift left to clear the bits above the index, we shift down + * to clear the bits below the index (sans the log2(4 or 8) bits) + * and a mask to clear the log2(4 or 8) bits. We need therefore + * define 4 shift counts, all of which are relative to PAGE_SHIFT. + * + * Although unsupportable for other reasons, this does mean that + * 512K and 4MB page sizes would be generaally supported by the + * kernel. (ELF binaries would break with > 64K PAGE_SIZE since + * the sections are only aligned that strongly). + * + * The operations performed for extraction are thus: + * + * ((X << FOO_SHIFT_LEFT) >> FOO_SHIFT_RIGHT) & ~0x3 + * */ +#define A (3 + (PAGE_SHIFT - 3) - 1) +#define B (A + 1) +#define C (B + (PAGE_SHIFT - 2) - 1) +#define D (C + 1) +#define E (D + (PAGE_SHIFT - 2) - 1) +#define F (E + 1) + +#define PMD_SHIFT_LEFT (64 - D) +#define PMD_SHIFT_RIGHT (64 - (D - B) - 2) +#define PGDIR_SHIFT_LEFT (64 - F) +#define PGDIR_SHIFT_RIGHT (64 - (F - D) - 2) +#define LOW_MASK_BITS 0x3 + /* TLB1 ** ICACHE line 1: tl1 DTLB and quick VPTE miss */ ldxa [%g1 + %g1] ASI_DMMU, %g4 ! Get TAG_ACCESS add %g3, %g3, %g5 ! Compute VPTE base cmp %g4, %g5 ! VPTE miss? bgeu,pt %xcc, 1f ! Continue here - andcc %g4, TAG_CONTEXT_BITS, %g5 ! From Nucleus? (for tl0 miss) - ba,pt %xcc, from_tl1_trap ! Fall to tl0 miss - rdpr %tl, %g5 ! For tl0 miss TL==3 test + andcc %g4, TAG_CONTEXT_BITS, %g5 ! tl0 miss Nucleus test + ba,a,pt %xcc, from_tl1_trap ! Fall to tl0 miss 1: sllx %g6, VPTE_SHIFT, %g4 ! Position TAG_ACCESS + or %g4, %g5, %g4 ! Prepare TAG_ACCESS /* TLB1 ** ICACHE line 2: Quick VPTE miss */ - or %g4, %g5, %g4 ! Prepare TAG_ACCESS mov TSB_REG, %g1 ! Grab TSB reg ldxa [%g1] ASI_DMMU, %g5 ! Doing PGD caching? - srlx %g6, (TLB_PMD_SHIFT - 1), %g1 ! Position PMD offset + sllx %g6, PMD_SHIFT_LEFT, %g1 ! Position PMD offset be,pn %xcc, sparc64_vpte_nucleus ! Is it from Nucleus? - and %g1, TLB_PMD_MASK, %g1 ! Mask PMD offset bits + srlx %g1, PMD_SHIFT_RIGHT, %g1 ! Mask PMD offset bits brnz,pt %g5, sparc64_vpte_continue ! Yep, go like smoke - add %g1, %g1, %g1 ! Position PMD offset some more + andn %g1, LOW_MASK_BITS, %g1 ! Final PMD mask + sllx %g6, PGDIR_SHIFT_LEFT, %g5 ! Position PGD offset /* TLB1 ** ICACHE line 3: Quick VPTE miss */ - srlx %g6, (TLB_PGD_SHIFT - 2), %g5 ! Position PGD offset - and %g5, TLB_PGD_MASK, %g5 ! Mask PGD offset + srlx %g5, PGDIR_SHIFT_RIGHT, %g5 ! Mask PGD offset bits + andn %g5, LOW_MASK_BITS, %g5 ! Final PGD mask lduwa [%g7 + %g5] ASI_PHYS_USE_EC, %g5! Load PGD brz,pn %g5, vpte_noent ! Valid? sparc64_kpte_continue: @@ -71,23 +154,28 @@ sparc64_vpte_continue: brz,pn %g5, vpte_noent ! Valid? /* TLB1 ** ICACHE line 4: Quick VPTE miss */ - FILL_VALID_SZ_BITS1(%g1) ! Put _PAGE_VALID into %g1 - FILL_VALID_SZ_BITS2(%g1) ! Put _PAGE_VALID into %g1 + mov (VALID_SZ_BITS >> 61), %g1 ! upper vpte into %g1 + sllx %g1, 61, %g1 ! finish calc or %g5, VPTE_BITS, %g5 ! Prepare VPTE data or %g5, %g1, %g5 ! ... mov TLB_SFSR, %g1 ! Restore %g1 value stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Load VPTE into TLB stxa %g4, [%g1 + %g1] ASI_DMMU ! Restore previous TAG_ACCESS retry ! Load PTE once again - FILL_VALID_SZ_BITS_NOP +#undef SZ_BITS +#undef VALID_SZ_BITS #undef VPTE_SHIFT -#undef TLB_PMD_SHIFT -#undef TLB_PGD_SHIFT #undef VPTE_BITS -#undef TLB_PMD_MASK -#undef TLB_PGD_MASK -#undef FILL_VALID_SZ_BITS1 -#undef FILL_VALID_SZ_BITS2 -#undef FILL_VALID_SZ_BITS_NOP +#undef A +#undef B +#undef C +#undef D +#undef E +#undef F +#undef PMD_SHIFT_LEFT +#undef PMD_SHIFT_RIGHT +#undef PGDIR_SHIFT_LEFT +#undef PGDIR_SHIFT_RIGHT +#undef LOW_MASK_BITS diff --git a/arch/sparc64/kernel/dtlb_base.S b/arch/sparc64/kernel/dtlb_base.S index 294fb44aeb2c9..ded2fed23fcc5 100644 --- a/arch/sparc64/kernel/dtlb_base.S +++ b/arch/sparc64/kernel/dtlb_base.S @@ -7,7 +7,7 @@ */ #include <asm/pgtable.h> -#include <asm/mmu_context.h> +#include <asm/mmu.h> /* %g1 TLB_SFSR (%g1 + %g1 == TLB_TAG_ACCESS) * %g2 (KERN_HIGHBITS | KERN_LOWBITS) @@ -68,8 +68,8 @@ /* DTLB ** ICACHE line 1: Quick user TLB misses */ ldxa [%g1 + %g1] ASI_DMMU, %g4 ! Get TAG_ACCESS andcc %g4, TAG_CONTEXT_BITS, %g0 ! From Nucleus? - mov 1, %g5 ! For TL==3 test from_tl1_trap: + rdpr %tl, %g5 ! For TL==3 test CREATE_VPTE_OFFSET1(%g4, %g6) ! Create VPTE offset be,pn %xcc, 3f ! Yep, special processing CREATE_VPTE_OFFSET2(%g4, %g6) ! Create VPTE offset diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S index c4b705d0e00ca..a47f2d0b1a29b 100644 --- a/arch/sparc64/kernel/entry.S +++ b/arch/sparc64/kernel/entry.S @@ -38,97 +38,150 @@ * range (note that this is only possible for instruction miss, data misses to * obp range do not use vpte). If so, go back directly to the faulting address. * This is because we want to read the tpc, otherwise we have no way of knowing - * the 8k aligned faulting address if we are using >8k kernel pagesize. This also - * ensures no vpte range addresses are dropped into tlb while obp is executing - * (see inherit_locked_prom_mappings() rant). + * the 8k aligned faulting address if we are using >8k kernel pagesize. This + * also ensures no vpte range addresses are dropped into tlb while obp is + * executing (see inherit_locked_prom_mappings() rant). */ sparc64_vpte_nucleus: + /* Load 0xf0000000, which is LOW_OBP_ADDRESS. */ mov 0xf, %g5 - sllx %g5, 28, %g5 ! Load 0xf0000000 - cmp %g4, %g5 ! Is addr >= LOW_OBP_ADDRESS? + sllx %g5, 28, %g5 + + /* Is addr >= LOW_OBP_ADDRESS? */ + cmp %g4, %g5 blu,pn %xcc, sparc64_vpte_patchme1 mov 0x1, %g5 - sllx %g5, 32, %g5 ! Load 0x100000000 - cmp %g4, %g5 ! Is addr < HI_OBP_ADDRESS? + + /* Load 0x100000000, which is HI_OBP_ADDRESS. */ + sllx %g5, 32, %g5 + + /* Is addr < HI_OBP_ADDRESS? */ + cmp %g4, %g5 blu,pn %xcc, obp_iaddr_patch nop + + /* These two instructions are patched by paginig_init(). */ sparc64_vpte_patchme1: - sethi %hi(0), %g5 ! This has to be patched + sethi %hi(0), %g5 sparc64_vpte_patchme2: - or %g5, %lo(0), %g5 ! This is patched too - ba,pt %xcc, sparc64_kpte_continue ! Part of dtlb_backend - add %g1, %g1, %g1 ! Finish PMD offset adjustment + or %g5, %lo(0), %g5 + + /* With kernel PGD in %g5, branch back into dtlb_backend. */ + ba,pt %xcc, sparc64_kpte_continue + andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */ vpte_noent: - mov TLB_SFSR, %g1 ! Restore %g1 value - stxa %g4, [%g1 + %g1] ASI_DMMU ! Restore previous TAG_ACCESS - done ! Slick trick + /* Restore previous TAG_ACCESS, %g5 is zero, and we will + * skip over the trap instruction so that the top level + * TLB miss handler will thing this %g5 value is just an + * invalid PTE, thus branching to full fault processing. + */ + mov TLB_SFSR, %g1 + stxa %g4, [%g1 + %g1] ASI_DMMU + done .globl obp_iaddr_patch - .globl obp_daddr_patch - obp_iaddr_patch: - sethi %hi(0), %g5 ! This and following is patched - or %g5, %lo(0), %g5 ! g5 now holds obp pmd base physaddr - wrpr %g0, 1, %tl ! Behave as if we are at TL0 - rdpr %tpc, %g4 ! Find original faulting iaddr - srlx %g4, 13, %g4 ! Throw out context bits - sllx %g4, 13, %g4 ! g4 has vpn + ctx0 now - mov TLB_SFSR, %g1 ! Restore %g1 value - stxa %g4, [%g1 + %g1] ASI_IMMU ! Restore previous TAG_ACCESS - srlx %g4, 23, %g6 ! Find pmd number - and %g6, 0x7ff, %g6 ! Find pmd number - sllx %g6, 2, %g6 ! Find pmd offset - lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pmd, ie pagetable physaddr - brz,pn %g5, longpath ! Kill the PROM ? :-) - sllx %g5, 11, %g5 ! Shift into place - srlx %g4, 13, %g6 ! find pte number in pagetable - and %g6, 0x3ff, %g6 ! find pte number in pagetable - sllx %g6, 3, %g6 ! find pte offset in pagetable - ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pte - brgez,pn %g5, longpath ! Kill the PROM ? :-) + /* These two instructions patched by inherit_prom_mappings(). */ + sethi %hi(0), %g5 + or %g5, %lo(0), %g5 + + /* Behave as if we are at TL0. */ + wrpr %g0, 1, %tl + rdpr %tpc, %g4 /* Find original faulting iaddr */ + srlx %g4, 13, %g4 /* Throw out context bits */ + sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */ + + /* Restore previous TAG_ACCESS. */ + mov TLB_SFSR, %g1 + stxa %g4, [%g1 + %g1] ASI_IMMU + + /* Get PMD offset. */ + srlx %g4, 23, %g6 + and %g6, 0x7ff, %g6 + sllx %g6, 2, %g6 + + /* Load PMD, is it valid? */ + lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5 + brz,pn %g5, longpath + sllx %g5, 11, %g5 + + /* Get PTE offset. */ + srlx %g4, 13, %g6 + and %g6, 0x3ff, %g6 + sllx %g6, 3, %g6 + + /* Load PTE. */ + ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5 + brgez,pn %g5, longpath nop - stxa %g5, [%g0] ASI_ITLB_DATA_IN ! put into tlb - retry ! go back to original fault + /* TLB load and return from trap. */ + stxa %g5, [%g0] ASI_ITLB_DATA_IN + retry + + .globl obp_daddr_patch obp_daddr_patch: - sethi %hi(0), %g5 ! This and following is patched - or %g5, %lo(0), %g5 ! g5 now holds obp pmd base physaddr - srlx %g4, 23, %g6 ! Find pmd number - and %g6, 0x7ff, %g6 ! Find pmd number - sllx %g6, 2, %g6 ! Find pmd offset - lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pmd, ie pagetable physaddr + /* These two instructions patched by inherit_prom_mappings(). */ + sethi %hi(0), %g5 + or %g5, %lo(0), %g5 + + /* Get PMD offset. */ + srlx %g4, 23, %g6 + and %g6, 0x7ff, %g6 + sllx %g6, 2, %g6 + + /* Load PMD, is it valid? */ + lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5 brz,pn %g5, longpath - sllx %g5, 11, %g5 ! Shift into place - srlx %g4, 13, %g6 ! find pte number in pagetable - and %g6, 0x3ff, %g6 ! find pte number in pagetable - sllx %g6, 3, %g6 ! find pte offset in pagetable - ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5! Load pte + sllx %g5, 11, %g5 + + /* Get PTE offset. */ + srlx %g4, 13, %g6 + and %g6, 0x3ff, %g6 + sllx %g6, 3, %g6 + + /* Load PTE. */ + ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5 brgez,pn %g5, longpath nop - stxa %g5, [%g0] ASI_DTLB_DATA_IN ! put into tlb + + /* TLB load and return from trap. */ + stxa %g5, [%g0] ASI_DTLB_DATA_IN retry /* - * On a first level data miss, check whether this is to the OBP range (note that - * such accesses can be made by prom, as well as by kernel using prom_getproperty - * on "address"), and if so, do not use vpte access ... rather, use information - * saved during inherit_prom_mappings() using 8k pagesize. + * On a first level data miss, check whether this is to the OBP range (note + * that such accesses can be made by prom, as well as by kernel using + * prom_getproperty on "address"), and if so, do not use vpte access ... + * rather, use information saved during inherit_prom_mappings() using 8k + * pagesize. */ kvmap: + /* Load 0xf0000000, which is LOW_OBP_ADDRESS. */ mov 0xf, %g5 - sllx %g5, 28, %g5 ! Load 0xf0000000 - cmp %g4, %g5 ! Is addr >= LOW_OBP_ADDRESS? + sllx %g5, 28, %g5 + + /* Is addr >= LOW_OBP_ADDRESS? */ + cmp %g4, %g5 blu,pn %xcc, vmalloc_addr mov 0x1, %g5 - sllx %g5, 32, %g5 ! Load 0x100000000 - cmp %g4, %g5 ! Is addr < HI_OBP_ADDRESS? + + /* Load 0x100000000, which is HI_OBP_ADDRESS. */ + sllx %g5, 32, %g5 + + /* Is addr < HI_OBP_ADDRESS? */ + cmp %g4, %g5 blu,pn %xcc, obp_daddr_patch nop -vmalloc_addr: ! vmalloc addr accessed - ldxa [%g3 + %g6] ASI_N, %g5 ! Yep, load k-vpte - brgez,pn %g5, longpath ! Valid, load into TLB + +vmalloc_addr: + /* If we get here, a vmalloc addr accessed, load kernel VPTE. */ + ldxa [%g3 + %g6] ASI_N, %g5 + brgez,pn %g5, longpath nop + + /* PTE is valid, load into TLB and return from trap. */ stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB retry @@ -199,9 +252,11 @@ do_fpdis: faddd %f0, %f2, %f4 fmuld %f0, %f2, %f6 ldxa [%g3] ASI_DMMU, %g5 - add %g6, TI_FPREGS + 0xc0, %g2 - stxa %g0, [%g3] ASI_DMMU +cplus_fptrap_insn_1: + sethi %hi(0), %g2 + stxa %g2, [%g3] ASI_DMMU membar #Sync + add %g6, TI_FPREGS + 0xc0, %g2 faddd %f0, %f2, %f8 fmuld %f0, %f2, %f10 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-( @@ -225,7 +280,9 @@ do_fpdis: fzero %f34 ldxa [%g3] ASI_DMMU, %g5 add %g6, TI_FPREGS, %g1 - stxa %g0, [%g3] ASI_DMMU +cplus_fptrap_insn_2: + sethi %hi(0), %g2 + stxa %g2, [%g3] ASI_DMMU membar #Sync add %g6, TI_FPREGS + 0x40, %g2 faddd %f32, %f34, %f36 @@ -249,9 +306,11 @@ do_fpdis: 3: mov SECONDARY_CONTEXT, %g3 add %g6, TI_FPREGS, %g1 ldxa [%g3] ASI_DMMU, %g5 - mov 0x40, %g2 - stxa %g0, [%g3] ASI_DMMU +cplus_fptrap_insn_3: + sethi %hi(0), %g2 + stxa %g2, [%g3] ASI_DMMU membar #Sync + mov 0x40, %g2 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-( ldda [%g1 + %g2] ASI_BLK_S, %f16 add %g1, 0x80, %g1 @@ -412,10 +471,12 @@ do_fptrap_after_fsr: rd %gsr, %g3 stx %g3, [%g6 + TI_GSR] mov SECONDARY_CONTEXT, %g3 - add %g6, TI_FPREGS, %g2 ldxa [%g3] ASI_DMMU, %g5 - stxa %g0, [%g3] ASI_DMMU +cplus_fptrap_insn_4: + sethi %hi(0), %g2 + stxa %g2, [%g3] ASI_DMMU membar #Sync + add %g6, TI_FPREGS, %g2 andcc %g1, FPRS_DL, %g0 be,pn %icc, 4f mov 0x40, %g3 @@ -433,6 +494,33 @@ do_fptrap_after_fsr: ba,pt %xcc, etrap wr %g0, 0, %fprs +cplus_fptrap_1: + sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 + + .globl cheetah_plus_patch_fpdis +cheetah_plus_patch_fpdis: + /* We configure the dTLB512_0 for 4MB pages and the + * dTLB512_1 for 8K pages when in context zero. + */ + sethi %hi(cplus_fptrap_1), %o0 + lduw [%o0 + %lo(cplus_fptrap_1)], %o1 + + set cplus_fptrap_insn_1, %o2 + stw %o1, [%o2] + flush %o2 + set cplus_fptrap_insn_2, %o2 + stw %o1, [%o2] + flush %o2 + set cplus_fptrap_insn_3, %o2 + stw %o1, [%o2] + flush %o2 + set cplus_fptrap_insn_4, %o2 + stw %o1, [%o2] + flush %o2 + + retl + nop + /* The registers for cross calls will be: * * DATA 0: [low 32-bits] Address of function to call, jmp to this @@ -1642,7 +1730,7 @@ ret_from_syscall: andn %o7, _TIF_NEWCHILD, %l0 stx %l0, [%g6 + TI_FLAGS] call schedule_tail - mov %g5, %o0 + mov %g7, %o0 andcc %l0, _TIF_PERFCTR, %g0 be,pt %icc, 1f nop diff --git a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S index d50b755c7e9c3..50d2af1d98aee 100644 --- a/arch/sparc64/kernel/etrap.S +++ b/arch/sparc64/kernel/etrap.S @@ -14,6 +14,7 @@ #include <asm/spitfire.h> #include <asm/head.h> #include <asm/processor.h> +#include <asm/mmu.h> #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ) #define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV) @@ -67,7 +68,13 @@ etrap_irq: wrpr %g3, 0, %otherwin wrpr %g2, 0, %wstate - stxa %g0, [%l4] ASI_DMMU +cplus_etrap_insn_1: + sethi %hi(0), %g3 + sllx %g3, 32, %g3 +cplus_etrap_insn_2: + sethi %hi(0), %g2 + or %g3, %g2, %g3 + stxa %g3, [%l4] ASI_DMMU flush %l6 wr %g0, ASI_AIUS, %asi 2: wrpr %g0, 0x0, %tl @@ -95,11 +102,12 @@ etrap_irq: stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] wrpr %g0, ETRAP_PSTATE2, %pstate mov %l6, %g6 +#ifdef CONFIG_SMP + mov TSB_REG, %g3 + ldxa [%g3] ASI_IMMU, %g5 +#endif jmpl %l2 + 0x4, %g0 ldx [%g6 + TI_TASK], %g4 - nop - nop - nop 3: ldub [%l6 + TI_FPDEPTH], %l5 add %l6, TI_FPSAVED + 1, %l4 @@ -207,7 +215,13 @@ scetrap: rdpr %pil, %g2 mov PRIMARY_CONTEXT, %l4 wrpr %g3, 0, %otherwin wrpr %g2, 0, %wstate - stxa %g0, [%l4] ASI_DMMU +cplus_etrap_insn_3: + sethi %hi(0), %g3 + sllx %g3, 32, %g3 +cplus_etrap_insn_4: + sethi %hi(0), %g2 + or %g3, %g2, %g3 + stxa %g3, [%l4] ASI_DMMU flush %l6 mov ASI_AIUS, %l7 @@ -241,11 +255,47 @@ scetrap: rdpr %pil, %g2 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6] mov %l6, %g6 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] +#ifdef CONFIG_SMP + mov TSB_REG, %g3 + ldxa [%g3] ASI_IMMU, %g5 +#endif ldx [%g6 + TI_TASK], %g4 done - nop - nop #undef TASK_REGOFF #undef ETRAP_PSTATE1 -#undef ETRAP_PSTATE2 + +cplus_einsn_1: + sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3 +cplus_einsn_2: + sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 + + .globl cheetah_plus_patch_etrap +cheetah_plus_patch_etrap: + /* We configure the dTLB512_0 for 4MB pages and the + * dTLB512_1 for 8K pages when in context zero. + */ + sethi %hi(cplus_einsn_1), %o0 + sethi %hi(cplus_etrap_insn_1), %o2 + lduw [%o0 + %lo(cplus_einsn_1)], %o1 + or %o2, %lo(cplus_etrap_insn_1), %o2 + stw %o1, [%o2] + flush %o2 + sethi %hi(cplus_etrap_insn_3), %o2 + or %o2, %lo(cplus_etrap_insn_3), %o2 + stw %o1, [%o2] + flush %o2 + + sethi %hi(cplus_einsn_2), %o0 + sethi %hi(cplus_etrap_insn_2), %o2 + lduw [%o0 + %lo(cplus_einsn_2)], %o1 + or %o2, %lo(cplus_etrap_insn_2), %o2 + stw %o1, [%o2] + flush %o2 + sethi %hi(cplus_etrap_insn_4), %o2 + or %o2, %lo(cplus_etrap_insn_4), %o2 + stw %o1, [%o2] + flush %o2 + + retl + nop diff --git a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S index 4a286a8000b07..8104a56ca2d8e 100644 --- a/arch/sparc64/kernel/head.S +++ b/arch/sparc64/kernel/head.S @@ -25,6 +25,7 @@ #include <asm/dcu.h> #include <asm/head.h> #include <asm/ttable.h> +#include <asm/mmu.h> /* This section from from _start to sparc64_boot_end should fit into * 0x0000.0000.0040.4000 to 0x0000.0000.0040.8000 and will be sharing space @@ -88,8 +89,8 @@ sparc_ramdisk_image64: * PROM entry point is on %o4 */ sparc64_boot: - BRANCH_IF_CHEETAH_BASE(g1,g5,cheetah_boot) - BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g5,cheetah_plus_boot) + BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot) + BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot) ba,pt %xcc, spitfire_boot nop @@ -102,11 +103,11 @@ cheetah_boot: mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1 wr %g1, %asr18 - sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5 - or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5 - sllx %g5, 32, %g5 - or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5 - stxa %g5, [%g0] ASI_DCU_CONTROL_REG + sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7 + or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7 + sllx %g7, 32, %g7 + or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7 + stxa %g7, [%g0] ASI_DCU_CONTROL_REG membar #Sync cheetah_generic_boot: @@ -491,7 +492,7 @@ sun4u_init: stxa %g3, [%g2] ASI_DMMU membar #Sync - BRANCH_IF_ANY_CHEETAH(g1,g5,cheetah_tlb_fixup) + BRANCH_IF_ANY_CHEETAH(g1,g7,cheetah_tlb_fixup) ba,pt %xcc, spitfire_tlb_fixup nop @@ -515,14 +516,31 @@ cheetah_tlb_fixup: membar #Sync mov 2, %g2 /* Set TLB type to cheetah+. */ - BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g5,g7,1f) + BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f) mov 1, %g2 /* Set TLB type to cheetah. */ -1: sethi %hi(tlb_type), %g5 - stw %g2, [%g5 + %lo(tlb_type)] +1: sethi %hi(tlb_type), %g1 + stw %g2, [%g1 + %lo(tlb_type)] - /* Patch copy/page operations to cheetah optimized versions. */ + BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f) + ba,pt %xcc, 2f + nop + +1: /* Patch context register writes to support nucleus page + * size correctly. + */ + call cheetah_plus_patch_etrap + nop + call cheetah_plus_patch_rtrap + nop + call cheetah_plus_patch_fpdis + nop + call cheetah_plus_patch_winfixup + nop + + +2: /* Patch copy/page operations to cheetah optimized versions. */ call cheetah_patch_copyops nop call cheetah_patch_cachetlbops @@ -549,8 +567,8 @@ spitfire_tlb_fixup: /* Set TLB type to spitfire. */ mov 0, %g2 - sethi %hi(tlb_type), %g5 - stw %g2, [%g5 + %lo(tlb_type)] + sethi %hi(tlb_type), %g1 + stw %g2, [%g1 + %lo(tlb_type)] tlb_fixup_done: sethi %hi(init_thread_union), %g6 @@ -578,12 +596,18 @@ tlb_fixup_done: #endif wr %g0, ASI_P, %asi - mov 1, %g5 - sllx %g5, THREAD_SHIFT, %g5 - sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5 - add %g6, %g5, %sp + mov 1, %g1 + sllx %g1, THREAD_SHIFT, %g1 + sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1 + add %g6, %g1, %sp mov 0, %fp + /* Set per-cpu pointer initially to zero, this makes + * the boot-cpu use the in-kernel-image per-cpu areas + * before setup_per_cpu_area() is invoked. + */ + clr %g5 + wrpr %g0, 0, %wstate wrpr %g0, 0x0, %tl @@ -619,8 +643,8 @@ setup_tba: /* i0 = is_starfire */ rdpr %pstate, %o1 mov %g6, %o2 wrpr %o1, (PSTATE_AG|PSTATE_IE), %pstate - sethi %hi(sparc64_ttable_tl0), %g5 - wrpr %g5, %tba + sethi %hi(sparc64_ttable_tl0), %g1 + wrpr %g1, %tba mov %o2, %g6 /* Set up MMU globals */ @@ -633,6 +657,8 @@ setup_tba: /* i0 = is_starfire */ mov TSB_REG, %g1 stxa %g0, [%g1] ASI_DMMU membar #Sync + stxa %g0, [%g1] ASI_IMMU + membar #Sync mov TLB_SFSR, %g1 sethi %uhi(KERN_HIGHBITS), %g2 or %g2, %ulo(KERN_HIGHBITS), %g2 @@ -685,10 +711,23 @@ spitfire_vpte_base: call init_irqwork_curcpu nop - sethi %hi(sparc64_ttable_tl0), %g5 call prom_set_trap_table - mov %g5, %o0 + sethi %hi(sparc64_ttable_tl0), %o0 + + BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f) + ba,pt %xcc, 2f + nop +1: /* Start using proper page size encodings in ctx register. */ + sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3 + mov PRIMARY_CONTEXT, %g1 + sllx %g3, 32, %g3 + sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 + or %g3, %g2, %g3 + stxa %g3, [%g1] ASI_DMMU + membar #Sync + +2: rdpr %pstate, %o1 or %o1, PSTATE_IE, %o1 wrpr %o1, 0, %pstate diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c index 41fe099138793..3567fa879e1fe 100644 --- a/arch/sparc64/kernel/pci_psycho.c +++ b/arch/sparc64/kernel/pci_psycho.c @@ -1133,7 +1133,7 @@ static void __init psycho_base_address_update(struct pci_dev *pdev, int resource (((u32)(res->start - root->start)) & ~size)); if (resource == PCI_ROM_RESOURCE) { reg |= PCI_ROM_ADDRESS_ENABLE; - res->flags |= PCI_ROM_ADDRESS_ENABLE; + res->flags |= IORESOURCE_ROM_ENABLE; } pci_write_config_dword(pdev, where, reg); diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c index 2bf247792fe5f..5525d1ec4af88 100644 --- a/arch/sparc64/kernel/pci_sabre.c +++ b/arch/sparc64/kernel/pci_sabre.c @@ -1100,7 +1100,7 @@ static void __init sabre_base_address_update(struct pci_dev *pdev, int resource) (((u32)(res->start - base)) & ~size)); if (resource == PCI_ROM_RESOURCE) { reg |= PCI_ROM_ADDRESS_ENABLE; - res->flags |= PCI_ROM_ADDRESS_ENABLE; + res->flags |= IORESOURCE_ROM_ENABLE; } pci_write_config_dword(pdev, where, reg); diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c index b495698858453..e93fcadc37229 100644 --- a/arch/sparc64/kernel/pci_schizo.c +++ b/arch/sparc64/kernel/pci_schizo.c @@ -1572,7 +1572,7 @@ static void __init schizo_base_address_update(struct pci_dev *pdev, int resource (((u32)(res->start - root->start)) & ~size)); if (resource == PCI_ROM_RESOURCE) { reg |= PCI_ROM_ADDRESS_ENABLE; - res->flags |= PCI_ROM_ADDRESS_ENABLE; + res->flags |= IORESOURCE_ROM_ENABLE; } pci_write_config_dword(pdev, where, reg); diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S index b7c3277bb92ac..0696ed4b9d644 100644 --- a/arch/sparc64/kernel/rtrap.S +++ b/arch/sparc64/kernel/rtrap.S @@ -223,7 +223,10 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5 - ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6 + mov TSB_REG, %g6 + brnz,a,pn %l3, 1f + ldxa [%g6] ASI_IMMU, %g5 +1: ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7 wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0 @@ -250,6 +253,10 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 brnz,pn %l3, kern_rtt mov PRIMARY_CONTEXT, %l7 ldxa [%l7 + %l7] ASI_DMMU, %l0 +cplus_rtrap_insn_1: + sethi %hi(0), %l1 + sllx %l1, 32, %l1 + or %l0, %l1, %l0 stxa %l0, [%l7] ASI_DMMU flush %g6 rdpr %wstate, %l1 @@ -298,10 +305,10 @@ kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5 andcc %l2, FPRS_FEF, %g0 be,pn %icc, 5f sll %o0, 3, %o5 - rd %fprs, %g5 + rd %fprs, %g1 - wr %g5, FPRS_FEF, %fprs - ldx [%o1 + %o5], %g5 + wr %g1, FPRS_FEF, %fprs + ldx [%o1 + %o5], %g1 add %g6, TI_XFSR, %o1 membar #StoreLoad | #LoadLoad sll %o0, 8, %o2 @@ -313,7 +320,7 @@ kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5 ldda [%o4 + %o2] ASI_BLK_P, %f16 1: andcc %l2, FPRS_DU, %g0 be,pn %icc, 1f - wr %g5, 0, %gsr + wr %g1, 0, %gsr add %o2, 0x80, %o2 ldda [%o3 + %o2] ASI_BLK_P, %f32 ldda [%o4 + %o2] ASI_BLK_P, %f48 @@ -335,3 +342,21 @@ kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5 wr %g0, FPRS_DU, %fprs ba,pt %xcc, rt_continue stb %l5, [%g6 + TI_FPDEPTH] + +cplus_rinsn_1: + sethi %uhi(CTX_CHEETAH_PLUS_NUC), %l1 + + .globl cheetah_plus_patch_rtrap +cheetah_plus_patch_rtrap: + /* We configure the dTLB512_0 for 4MB pages and the + * dTLB512_1 for 8K pages when in context zero. + */ + sethi %hi(cplus_rinsn_1), %o0 + sethi %hi(cplus_rtrap_insn_1), %o2 + lduw [%o0 + %lo(cplus_rinsn_1)], %o1 + or %o2, %lo(cplus_rtrap_insn_1), %o2 + stw %o1, [%o2] + flush %o2 + + retl + nop diff --git a/arch/sparc64/kernel/semaphore.c b/arch/sparc64/kernel/semaphore.c index 9ddfcb9a19001..63496c43fe173 100644 --- a/arch/sparc64/kernel/semaphore.c +++ b/arch/sparc64/kernel/semaphore.c @@ -65,30 +65,25 @@ void up(struct semaphore *sem) __asm__ __volatile__("\n" " ! up sem(%0)\n" " membar #StoreLoad | #LoadLoad\n" -"1: lduw [%0], %%g5\n" -" add %%g5, 1, %%g7\n" -" cas [%0], %%g5, %%g7\n" -" cmp %%g5, %%g7\n" +"1: lduw [%0], %%g1\n" +" add %%g1, 1, %%g7\n" +" cas [%0], %%g1, %%g7\n" +" cmp %%g1, %%g7\n" " bne,pn %%icc, 1b\n" " addcc %%g7, 1, %%g0\n" " ble,pn %%icc, 3f\n" " membar #StoreLoad | #StoreStore\n" "2:\n" " .subsection 2\n" -"3: mov %0, %%g5\n" +"3: mov %0, %%g1\n" " save %%sp, -160, %%sp\n" -" mov %%g1, %%l1\n" -" mov %%g2, %%l2\n" -" mov %%g3, %%l3\n" " call %1\n" -" mov %%g5, %%o0\n" -" mov %%l1, %%g1\n" -" mov %%l2, %%g2\n" +" mov %%g1, %%o0\n" " ba,pt %%xcc, 2b\n" -" restore %%l3, %%g0, %%g3\n" +" restore\n" " .previous\n" : : "r" (sem), "i" (__up) - : "g5", "g7", "memory", "cc"); + : "g1", "g2", "g3", "g7", "memory", "cc"); } static void __sched __down(struct semaphore * sem) @@ -127,30 +122,25 @@ void __sched down(struct semaphore *sem) __asm__ __volatile__("\n" " ! down sem(%0)\n" -"1: lduw [%0], %%g5\n" -" sub %%g5, 1, %%g7\n" -" cas [%0], %%g5, %%g7\n" -" cmp %%g5, %%g7\n" +"1: lduw [%0], %%g1\n" +" sub %%g1, 1, %%g7\n" +" cas [%0], %%g1, %%g7\n" +" cmp %%g1, %%g7\n" " bne,pn %%icc, 1b\n" " cmp %%g7, 1\n" " bl,pn %%icc, 3f\n" " membar #StoreLoad | #StoreStore\n" "2:\n" " .subsection 2\n" -"3: mov %0, %%g5\n" +"3: mov %0, %%g1\n" " save %%sp, -160, %%sp\n" -" mov %%g1, %%l1\n" -" mov %%g2, %%l2\n" -" mov %%g3, %%l3\n" " call %1\n" -" mov %%g5, %%o0\n" -" mov %%l1, %%g1\n" -" mov %%l2, %%g2\n" +" mov %%g1, %%o0\n" " ba,pt %%xcc, 2b\n" -" restore %%l3, %%g0, %%g3\n" +" restore\n" " .previous\n" : : "r" (sem), "i" (__down) - : "g5", "g7", "memory", "cc"); + : "g1", "g2", "g3", "g7", "memory", "cc"); } int down_trylock(struct semaphore *sem) @@ -175,20 +165,20 @@ int down_trylock(struct semaphore *sem) __asm__ __volatile__("\n" " ! down_trylock sem(%1) ret(%0)\n" -"1: lduw [%1], %%g5\n" -" sub %%g5, 1, %%g7\n" -" cmp %%g5, 1\n" +"1: lduw [%1], %%g1\n" +" sub %%g1, 1, %%g7\n" +" cmp %%g1, 1\n" " bl,pn %%icc, 2f\n" " mov 1, %0\n" -" cas [%1], %%g5, %%g7\n" -" cmp %%g5, %%g7\n" +" cas [%1], %%g1, %%g7\n" +" cmp %%g1, %%g7\n" " bne,pn %%icc, 1b\n" " mov 0, %0\n" " membar #StoreLoad | #StoreStore\n" "2:\n" : "=&r" (ret) : "r" (sem) - : "g5", "g7", "memory", "cc"); + : "g1", "g7", "memory", "cc"); return ret; } @@ -237,31 +227,25 @@ int __sched down_interruptible(struct semaphore *sem) __asm__ __volatile__("\n" " ! down_interruptible sem(%2) ret(%0)\n" -"1: lduw [%2], %%g5\n" -" sub %%g5, 1, %%g7\n" -" cas [%2], %%g5, %%g7\n" -" cmp %%g5, %%g7\n" +"1: lduw [%2], %%g1\n" +" sub %%g1, 1, %%g7\n" +" cas [%2], %%g1, %%g7\n" +" cmp %%g1, %%g7\n" " bne,pn %%icc, 1b\n" " cmp %%g7, 1\n" " bl,pn %%icc, 3f\n" " membar #StoreLoad | #StoreStore\n" "2:\n" " .subsection 2\n" -"3: mov %2, %%g5\n" +"3: mov %2, %%g1\n" " save %%sp, -160, %%sp\n" -" mov %%g1, %%l1\n" -" mov %%g2, %%l2\n" -" mov %%g3, %%l3\n" " call %3\n" -" mov %%g5, %%o0\n" -" mov %%l1, %%g1\n" -" mov %%l2, %%g2\n" -" mov %%l3, %%g3\n" +" mov %%g1, %%o0\n" " ba,pt %%xcc, 2b\n" -" restore %%o0, %%g0, %0\n" +" restore\n" " .previous\n" : "=r" (ret) : "0" (ret), "r" (sem), "i" (__down_interruptible) - : "g5", "g7", "memory", "cc"); + : "g1", "g2", "g3", "g7", "memory", "cc"); return ret; } diff --git a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c index 0c9ce2bb5100a..12c3d84b7460c 100644 --- a/arch/sparc64/kernel/setup.c +++ b/arch/sparc64/kernel/setup.c @@ -47,6 +47,7 @@ #include <asm/timer.h> #include <asm/sections.h> #include <asm/setup.h> +#include <asm/mmu.h> #ifdef CONFIG_IP_PNP #include <net/ipconfig.h> @@ -157,11 +158,11 @@ int prom_callback(long *args) for_each_process(p) { mm = p->mm; - if (CTX_HWBITS(mm->context) == ctx) + if (CTX_NRBITS(mm->context) == ctx) break; } if (!mm || - CTX_HWBITS(mm->context) != ctx) + CTX_NRBITS(mm->context) != ctx) goto done; pgdp = pgd_offset(mm, va); @@ -187,12 +188,19 @@ int prom_callback(long *args) } if ((va >= KERNBASE) && (va < (KERNBASE + (4 * 1024 * 1024)))) { + unsigned long kernel_pctx = 0; + + if (tlb_type == cheetah_plus) + kernel_pctx |= (CTX_CHEETAH_PLUS_NUC | + CTX_CHEETAH_PLUS_CTX0); + /* Spitfire Errata #32 workaround */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ - : "r" (0), - "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); + : "r" (kernel_pctx), + "r" (PRIMARY_CONTEXT), + "i" (ASI_DMMU)); /* * Locked down tlb entry. diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c index 1441ef81b8abe..57f7f0f45d097 100644 --- a/arch/sparc64/kernel/smp.c +++ b/arch/sparc64/kernel/smp.c @@ -3,6 +3,7 @@ * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) */ +#include <linux/module.h> #include <linux/kernel.h> #include <linux/sched.h> #include <linux/mm.h> @@ -20,6 +21,7 @@ #include <linux/cache.h> #include <linux/jiffies.h> #include <linux/profile.h> +#include <linux/bootmem.h> #include <asm/head.h> #include <asm/ptrace.h> @@ -89,7 +91,6 @@ void __init smp_store_cpu_info(int id) cpu_data(id).pgcache_size = 0; cpu_data(id).pte_cache[0] = NULL; cpu_data(id).pte_cache[1] = NULL; - cpu_data(id).pgdcache_size = 0; cpu_data(id).pgd_cache = NULL; cpu_data(id).idle_volume = 1; } @@ -100,6 +101,16 @@ static volatile unsigned long callin_flag = 0; extern void inherit_locked_prom_mappings(int save_p); +static inline void cpu_setup_percpu_base(unsigned long cpu_id) +{ + __asm__ __volatile__("mov %0, %%g5\n\t" + "stxa %0, [%1] %2\n\t" + "membar #Sync" + : /* no outputs */ + : "r" (__per_cpu_offset(cpu_id)), + "r" (TSB_REG), "i" (ASI_IMMU)); +} + void __init smp_callin(void) { int cpuid = hard_smp_processor_id(); @@ -108,6 +119,8 @@ void __init smp_callin(void) __flush_tlb_all(); + cpu_setup_percpu_base(cpuid); + smp_setup_percpu_timer(); local_irq_enable(); @@ -627,7 +640,10 @@ extern unsigned long xcall_flush_tlb_all_spitfire; extern unsigned long xcall_flush_tlb_all_cheetah; extern unsigned long xcall_report_regs; extern unsigned long xcall_receive_signal; + +#ifdef DCACHE_ALIASING_POSSIBLE extern unsigned long xcall_flush_dcache_page_cheetah; +#endif extern unsigned long xcall_flush_dcache_page_spitfire; #ifdef CONFIG_DEBUG_DCFLUSH @@ -637,7 +653,7 @@ extern atomic_t dcpage_flushes_xcall; static __inline__ void __local_flush_dcache_page(struct page *page) { -#if (L1DCACHE_SIZE > PAGE_SIZE) +#ifdef DCACHE_ALIASING_POSSIBLE __flush_dcache_page(page_address(page), ((tlb_type == spitfire) && page_mapping(page) != NULL)); @@ -672,11 +688,13 @@ void smp_flush_dcache_page_impl(struct page *page, int cpu) (u64) pg_addr, mask); } else { +#ifdef DCACHE_ALIASING_POSSIBLE data0 = ((u64)&xcall_flush_dcache_page_cheetah); cheetah_xcall_deliver(data0, __pa(pg_addr), 0, mask); +#endif } #ifdef CONFIG_DEBUG_DCFLUSH atomic_inc(&dcpage_flushes_xcall); @@ -709,10 +727,12 @@ void flush_dcache_page_all(struct mm_struct *mm, struct page *page) (u64) pg_addr, mask); } else { +#ifdef DCACHE_ALIASING_POSSIBLE data0 = ((u64)&xcall_flush_dcache_page_cheetah); cheetah_xcall_deliver(data0, __pa(pg_addr), 0, mask); +#endif } #ifdef CONFIG_DEBUG_DCFLUSH atomic_inc(&dcpage_flushes_xcall); @@ -1055,74 +1075,6 @@ void __init smp_tick_init(void) prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1; } -extern unsigned long cheetah_tune_scheduling(void); - -static void __init smp_tune_scheduling(void) -{ - unsigned long orig_flush_base, flush_base, flags, *p; - unsigned int ecache_size, order; - cycles_t tick1, tick2, raw; - int cpu_node; - - /* Approximate heuristic for SMP scheduling. It is an - * estimation of the time it takes to flush the L2 cache - * on the local processor. - * - * The ia32 chooses to use the L1 cache flush time instead, - * and I consider this complete nonsense. The Ultra can service - * a miss to the L1 with a hit to the L2 in 7 or 8 cycles, and - * L2 misses are what create extra bus traffic (ie. the "cost" - * of moving a process from one cpu to another). - */ - printk("SMP: Calibrating ecache flush... "); - if (tlb_type == cheetah || tlb_type == cheetah_plus) - return; - - cpu_find_by_instance(0, &cpu_node, NULL); - ecache_size = prom_getintdefault(cpu_node, - "ecache-size", (512 * 1024)); - if (ecache_size > (4 * 1024 * 1024)) - ecache_size = (4 * 1024 * 1024); - orig_flush_base = flush_base = - __get_free_pages(GFP_KERNEL, order = get_order(ecache_size)); - - if (flush_base != 0UL) { - local_irq_save(flags); - - /* Scan twice the size once just to get the TLB entries - * loaded and make sure the second scan measures pure misses. - */ - for (p = (unsigned long *)flush_base; - ((unsigned long)p) < (flush_base + (ecache_size<<1)); - p += (64 / sizeof(unsigned long))) - *((volatile unsigned long *)p); - - tick1 = tick_ops->get_tick(); - - __asm__ __volatile__("1:\n\t" - "ldx [%0 + 0x000], %%g1\n\t" - "ldx [%0 + 0x040], %%g2\n\t" - "ldx [%0 + 0x080], %%g3\n\t" - "ldx [%0 + 0x0c0], %%g5\n\t" - "add %0, 0x100, %0\n\t" - "cmp %0, %2\n\t" - "bne,pt %%xcc, 1b\n\t" - " nop" - : "=&r" (flush_base) - : "0" (flush_base), - "r" (flush_base + ecache_size) - : "g1", "g2", "g3", "g5"); - - tick2 = tick_ops->get_tick(); - - local_irq_restore(flags); - - raw = (tick2 - tick1); - - free_pages(orig_flush_base, order); - } -} - /* /proc/profile writes can call this, don't __init it please. */ static DEFINE_SPINLOCK(prof_setup_lock); @@ -1177,6 +1129,7 @@ void __devinit smp_prepare_boot_cpu(void) } current_thread_info()->cpu = hard_smp_processor_id(); + cpu_set(smp_processor_id(), cpu_online_map); cpu_set(smp_processor_id(), phys_cpu_present_map); } @@ -1212,11 +1165,6 @@ void __init smp_cpus_done(unsigned int max_cpus) (long) num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100); - - /* We want to run this with all the other cpus spinning - * in the kernel. - */ - smp_tune_scheduling(); } /* This needn't do anything as we do not sleep the cpu @@ -1242,3 +1190,43 @@ void smp_send_stop(void) { } +unsigned long __per_cpu_base; +unsigned long __per_cpu_shift; + +EXPORT_SYMBOL(__per_cpu_base); +EXPORT_SYMBOL(__per_cpu_shift); + +void __init setup_per_cpu_areas(void) +{ + unsigned long goal, size, i; + char *ptr; + /* Created by linker magic */ + extern char __per_cpu_start[], __per_cpu_end[]; + + /* Copy section for each CPU (we discard the original) */ + goal = ALIGN(__per_cpu_end - __per_cpu_start, PAGE_SIZE); + +#ifdef CONFIG_MODULES + if (goal < PERCPU_ENOUGH_ROOM) + goal = PERCPU_ENOUGH_ROOM; +#endif + __per_cpu_shift = 0; + for (size = 1UL; size < goal; size <<= 1UL) + __per_cpu_shift++; + + ptr = alloc_bootmem_pages(size * NR_CPUS); + + __per_cpu_base = ptr - __per_cpu_start; + + for (i = 0; i < NR_CPUS; i++, ptr += size) + memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start); + + /* Finally, load in the boot cpu's base value. + * We abuse the IMMU TSB register for trap handler + * entry and exit loading of %g5. That is why it + * has to be page aligned. + */ + BUG_ON((__per_cpu_shift < PAGE_SHIFT) || + (__per_cpu_base & ~PAGE_MASK)); + cpu_setup_percpu_base(hard_smp_processor_id()); +} diff --git a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c index 3cec1ebb083b0..cad5a11228006 100644 --- a/arch/sparc64/kernel/sparc64_ksyms.c +++ b/arch/sparc64/kernel/sparc64_ksyms.c @@ -59,6 +59,7 @@ #include <asm/ns87303.h> #include <asm/timer.h> #include <asm/cpudata.h> +#include <asm/rwsem.h> struct poll { int fd; @@ -174,6 +175,15 @@ EXPORT_SYMBOL(down_trylock); EXPORT_SYMBOL(down_interruptible); EXPORT_SYMBOL(up); +/* RW semaphores */ +EXPORT_SYMBOL(__down_read); +EXPORT_SYMBOL(__down_read_trylock); +EXPORT_SYMBOL(__down_write); +EXPORT_SYMBOL(__down_write_trylock); +EXPORT_SYMBOL(__up_read); +EXPORT_SYMBOL(__up_write); +EXPORT_SYMBOL(__downgrade_write); + /* Atomic counter implementation. */ EXPORT_SYMBOL(atomic_add); EXPORT_SYMBOL(atomic_add_ret); @@ -209,8 +219,11 @@ EXPORT_SYMBOL(__flushw_user); EXPORT_SYMBOL(tlb_type); EXPORT_SYMBOL(get_fb_unmapped_area); EXPORT_SYMBOL(flush_icache_range); + EXPORT_SYMBOL(flush_dcache_page); +#ifdef DCACHE_ALIASING_POSSIBLE EXPORT_SYMBOL(__flush_dcache_range); +#endif EXPORT_SYMBOL(mostek_lock); EXPORT_SYMBOL(mstk48t02_regs); @@ -350,7 +363,9 @@ EXPORT_SYMBOL(__memset); EXPORT_SYMBOL(memchr); EXPORT_SYMBOL(csum_partial); -EXPORT_SYMBOL(csum_partial_copy_sparc64); +EXPORT_SYMBOL(csum_partial_copy_nocheck); +EXPORT_SYMBOL(__csum_partial_copy_from_user); +EXPORT_SYMBOL(__csum_partial_copy_to_user); EXPORT_SYMBOL(ip_fast_csum); /* Moving data to/from/in userspace. */ diff --git a/arch/sparc64/kernel/sys_sparc32.c b/arch/sparc64/kernel/sys_sparc32.c index a9fa9a47074d8..567c91c77b20e 100644 --- a/arch/sparc64/kernel/sys_sparc32.c +++ b/arch/sparc64/kernel/sys_sparc32.c @@ -264,7 +264,7 @@ asmlinkage long compat_sys_ipc(u32 call, u32 first, u32 second, u32 third, compa switch (call) { case SEMTIMEDOP: - if (third) + if (fifth) /* sign extend semid */ return compat_sys_semtimedop((int)first, compat_ptr(ptr), second, diff --git a/arch/sparc64/kernel/trampoline.S b/arch/sparc64/kernel/trampoline.S index f1d764b2d39b5..2c8f9344b4eea 100644 --- a/arch/sparc64/kernel/trampoline.S +++ b/arch/sparc64/kernel/trampoline.S @@ -15,6 +15,7 @@ #include <asm/spitfire.h> #include <asm/processor.h> #include <asm/thread_info.h> +#include <asm/mmu.h> .data .align 8 @@ -334,6 +335,20 @@ do_unlock: call init_irqwork_curcpu nop + BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f) + ba,pt %xcc, 2f + nop + +1: /* Start using proper page size encodings in ctx register. */ + sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3 + mov PRIMARY_CONTEXT, %g1 + sllx %g3, 32, %g3 + sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 + or %g3, %g2, %g3 + stxa %g3, [%g1] ASI_DMMU + membar #Sync + +2: rdpr %pstate, %o1 or %o1, PSTATE_IE, %o1 wrpr %o1, 0, %pstate diff --git a/arch/sparc64/kernel/traps.c b/arch/sparc64/kernel/traps.c index 7d0e96f00bd00..56b203a2af696 100644 --- a/arch/sparc64/kernel/traps.c +++ b/arch/sparc64/kernel/traps.c @@ -806,48 +806,6 @@ static void cheetah_flush_ecache_line(unsigned long physaddr) "i" (ASI_PHYS_USE_EC)); } -#ifdef CONFIG_SMP -unsigned long __init cheetah_tune_scheduling(void) -{ - unsigned long tick1, tick2, raw; - unsigned long flush_base = ecache_flush_physbase; - unsigned long flush_linesize = ecache_flush_linesize; - unsigned long flush_size = ecache_flush_size; - - /* Run through the whole cache to guarantee the timed loop - * is really displacing cache lines. - */ - __asm__ __volatile__("1: subcc %0, %4, %0\n\t" - " bne,pt %%xcc, 1b\n\t" - " ldxa [%2 + %0] %3, %%g0\n\t" - : "=&r" (flush_size) - : "0" (flush_size), "r" (flush_base), - "i" (ASI_PHYS_USE_EC), "r" (flush_linesize)); - - /* The flush area is 2 X Ecache-size, so cut this in half for - * the timed loop. - */ - flush_base = ecache_flush_physbase; - flush_linesize = ecache_flush_linesize; - flush_size = ecache_flush_size >> 1; - - tick1 = tick_ops->get_tick(); - - __asm__ __volatile__("1: subcc %0, %4, %0\n\t" - " bne,pt %%xcc, 1b\n\t" - " ldxa [%2 + %0] %3, %%g0\n\t" - : "=&r" (flush_size) - : "0" (flush_size), "r" (flush_base), - "i" (ASI_PHYS_USE_EC), "r" (flush_linesize)); - - tick2 = tick_ops->get_tick(); - - raw = (tick2 - tick1); - - return (raw - (raw >> 2)); -} -#endif - /* Unfortunately, the diagnostic access to the I-cache tags we need to * use to clear the thing interferes with I-cache coherency transactions. * diff --git a/arch/sparc64/kernel/unaligned.c b/arch/sparc64/kernel/unaligned.c index 8a9d3b6bfe5c9..4372bf32ecf6f 100644 --- a/arch/sparc64/kernel/unaligned.c +++ b/arch/sparc64/kernel/unaligned.c @@ -379,8 +379,8 @@ void kernel_mna_trap_fault(struct pt_regs *regs, unsigned int insn) printk(KERN_ALERT "Unable to handle kernel paging request in mna handler"); printk(KERN_ALERT " at virtual address %016lx\n",address); printk(KERN_ALERT "current->{mm,active_mm}->context = %016lx\n", - (current->mm ? current->mm->context : - current->active_mm->context)); + (current->mm ? CTX_HWBITS(current->mm->context) : + CTX_HWBITS(current->active_mm->context))); printk(KERN_ALERT "current->{mm,active_mm}->pgd = %016lx\n", (current->mm ? (unsigned long) current->mm->pgd : (unsigned long) current->active_mm->pgd)); @@ -413,7 +413,7 @@ asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn, u : : "r" (regs), "r" (insn) : "o0", "o1", "o2", "o3", "o4", "o5", "o7", - "g1", "g2", "g3", "g4", "g5", "g7", "cc"); + "g1", "g2", "g3", "g4", "g7", "cc"); } else { unsigned long addr = compute_effective_address(regs, insn, ((insn >> 25) & 0x1f)); diff --git a/arch/sparc64/kernel/vmlinux.lds.S b/arch/sparc64/kernel/vmlinux.lds.S index a710d38d1a91f..382fd6798bb95 100644 --- a/arch/sparc64/kernel/vmlinux.lds.S +++ b/arch/sparc64/kernel/vmlinux.lds.S @@ -72,7 +72,7 @@ SECTIONS __initramfs_start = .; .init.ramfs : { *(.init.ramfs) } __initramfs_end = .; - . = ALIGN(32); + . = ALIGN(8192); __per_cpu_start = .; .data.percpu : { *(.data.percpu) } __per_cpu_end = .; diff --git a/arch/sparc64/kernel/winfixup.S b/arch/sparc64/kernel/winfixup.S index 3427d7a743e1f..dfbc7e0dcf70f 100644 --- a/arch/sparc64/kernel/winfixup.S +++ b/arch/sparc64/kernel/winfixup.S @@ -14,6 +14,25 @@ #include <asm/thread_info.h> .text + +set_pcontext: +cplus_winfixup_insn_1: + sethi %hi(0), %l1 + mov PRIMARY_CONTEXT, %g1 + sllx %l1, 32, %l1 +cplus_winfixup_insn_2: + sethi %hi(0), %g2 + or %l1, %g2, %l1 + stxa %l1, [%g1] ASI_DMMU + flush %g6 + retl + nop + +cplus_wfinsn_1: + sethi %uhi(CTX_CHEETAH_PLUS_NUC), %l1 +cplus_wfinsn_2: + sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2 + .align 32 /* Here are the rules, pay attention. @@ -62,9 +81,8 @@ fill_fixup: wrpr %g0, 0x0, %canrestore ! Standard etrap stuff. wrpr %g2, 0x0, %wstate ! This must be consistent. wrpr %g0, 0x0, %otherwin ! We know this. - mov PRIMARY_CONTEXT, %g1 ! Change contexts... - stxa %g0, [%g1] ASI_DMMU ! Back into the nucleus. - flush %g6 ! Flush instruction buffers + call set_pcontext ! Change contexts... + nop rdpr %pstate, %l1 ! Prepare to change globals. mov %g6, %o7 ! Get current. @@ -75,6 +93,10 @@ fill_fixup: wrpr %l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate mov %o7, %g6 ldx [%g6 + TI_TASK], %g4 +#ifdef CONFIG_SMP + mov TSB_REG, %g1 + ldxa [%g1] ASI_IMMU, %g5 +#endif /* This is the same as below, except we handle this a bit special * since we must preserve %l5 and %l6, see comment above. @@ -183,9 +205,8 @@ fill_fixup_mna: wrpr %g2, 0x0, %wstate ! This must be consistent. wrpr %g0, 0x0, %otherwin ! We know this. - mov PRIMARY_CONTEXT, %g1 ! Change contexts... - stxa %g0, [%g1] ASI_DMMU ! Back into the nucleus. - flush %g6 ! Flush instruction buffers + call set_pcontext ! Change contexts... + nop rdpr %pstate, %l1 ! Prepare to change globals. mov %g4, %o2 ! Setup args for mov %g5, %o1 ! final call to mem_address_unaligned. @@ -196,6 +217,10 @@ fill_fixup_mna: wrpr %l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate mov %o7, %g6 ! Get current back. ldx [%g6 + TI_TASK], %g4 ! Finish it. +#ifdef CONFIG_SMP + mov TSB_REG, %g1 + ldxa [%g1] ASI_IMMU, %g5 +#endif call mem_address_unaligned add %sp, PTREGS_OFF, %o0 @@ -289,9 +314,8 @@ fill_fixup_dax: wrpr %g2, 0x0, %wstate ! This must be consistent. wrpr %g0, 0x0, %otherwin ! We know this. - mov PRIMARY_CONTEXT, %g1 ! Change contexts... - stxa %g0, [%g1] ASI_DMMU ! Back into the nucleus. - flush %g6 ! Flush instruction buffers + call set_pcontext ! Change contexts... + nop rdpr %pstate, %l1 ! Prepare to change globals. mov %g4, %o1 ! Setup args for mov %g5, %o2 ! final call to data_access_exception. @@ -302,6 +326,10 @@ fill_fixup_dax: wrpr %l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate mov %o7, %g6 ! Get current back. ldx [%g6 + TI_TASK], %g4 ! Finish it. +#ifdef CONFIG_SMP + mov TSB_REG, %g1 + ldxa [%g1] ASI_IMMU, %g5 +#endif call data_access_exception add %sp, PTREGS_OFF, %o0 @@ -368,3 +396,22 @@ window_dax_from_user_common: ba,pt %xcc, rtrap clr %l6 + + .globl cheetah_plus_patch_winfixup +cheetah_plus_patch_winfixup: + sethi %hi(cplus_wfinsn_1), %o0 + sethi %hi(cplus_winfixup_insn_1), %o2 + lduw [%o0 + %lo(cplus_wfinsn_1)], %o1 + or %o2, %lo(cplus_winfixup_insn_1), %o2 + stw %o1, [%o2] + flush %o2 + + sethi %hi(cplus_wfinsn_2), %o0 + sethi %hi(cplus_winfixup_insn_2), %o2 + lduw [%o0 + %lo(cplus_wfinsn_2)], %o1 + or %o2, %lo(cplus_winfixup_insn_2), %o2 + stw %o1, [%o2] + flush %o2 + + retl + nop diff --git a/arch/sparc64/lib/Makefile b/arch/sparc64/lib/Makefile index 3cf408cb1695e..40dbeec7e5d6a 100644 --- a/arch/sparc64/lib/Makefile +++ b/arch/sparc64/lib/Makefile @@ -7,8 +7,8 @@ EXTRA_CFLAGS := -Werror lib-y := PeeCeeI.o copy_page.o clear_page.o strlen.o strncmp.o \ memscan.o strncpy_from_user.o strlen_user.o memcmp.o checksum.o \ - VISbzero.o VISmemset.o VIScsum.o VIScsumcopy.o \ - VIScsumcopyusr.o VISsave.o atomic.o bitops.o \ + bzero.o csum_copy.o csum_copy_from_user.o csum_copy_to_user.o \ + VISsave.o atomic.o bitops.o \ U1memcpy.o U1copy_from_user.o U1copy_to_user.o \ U3memcpy.o U3copy_from_user.o U3copy_to_user.o U3patch.o \ copy_in_user.o user_fixup.o memmove.o \ diff --git a/arch/sparc64/lib/U1memcpy.S b/arch/sparc64/lib/U1memcpy.S index fffec2e3cef8e..da9b520c71894 100644 --- a/arch/sparc64/lib/U1memcpy.S +++ b/arch/sparc64/lib/U1memcpy.S @@ -7,7 +7,9 @@ #ifdef __KERNEL__ #include <asm/visasm.h> #include <asm/asi.h> +#define GLOBAL_SPARE g7 #else +#define GLOBAL_SPARE g5 #define ASI_BLK_P 0xf0 #define FPRS_FEF 0x04 #ifdef MEMCPY_DEBUG @@ -123,7 +125,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ cmp %g2, 0 tne %xcc, 5 PREAMBLE - mov %o0, %g5 + mov %o0, %o4 cmp %o2, 0 be,pn %XCC, 85f or %o0, %o1, %o3 @@ -146,7 +148,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ * of bytes to copy to make 'dst' 64-byte aligned. We pre- * subtract this from 'len'. */ - sub %o0, %o1, %o4 + sub %o0, %o1, %GLOBAL_SPARE sub %g2, 0x40, %g2 sub %g0, %g2, %g2 sub %o2, %g2, %o2 @@ -156,11 +158,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ 1: subcc %g1, 0x1, %g1 EX_LD(LOAD(ldub, %o1 + 0x00, %o3)) - EX_ST(STORE(stb, %o3, %o1 + %o4)) + EX_ST(STORE(stb, %o3, %o1 + %GLOBAL_SPARE)) bgu,pt %XCC, 1b add %o1, 0x1, %o1 - add %o1, %o4, %o0 + add %o1, %GLOBAL_SPARE, %o0 2: cmp %g2, 0x0 and %o1, 0x7, %g1 @@ -188,19 +190,19 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ 3: membar #LoadStore | #StoreStore | #StoreLoad - subcc %o2, 0x40, %o4 + subcc %o2, 0x40, %GLOBAL_SPARE add %o1, %g1, %g1 - andncc %o4, (0x40 - 1), %o4 + andncc %GLOBAL_SPARE, (0x40 - 1), %GLOBAL_SPARE srl %g1, 3, %g2 - sub %o2, %o4, %g3 + sub %o2, %GLOBAL_SPARE, %g3 andn %o1, (0x40 - 1), %o1 and %g2, 7, %g2 andncc %g3, 0x7, %g3 fmovd %f0, %f2 sub %g3, 0x8, %g3 - sub %o2, %o4, %o2 + sub %o2, %GLOBAL_SPARE, %o2 - add %g1, %o4, %g1 + add %g1, %GLOBAL_SPARE, %g1 subcc %o2, %g3, %o2 EX_LD(LOAD_BLK(%o1, %f0)) @@ -208,7 +210,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ add %g1, %g3, %g1 EX_LD(LOAD_BLK(%o1, %f16)) add %o1, 0x40, %o1 - sub %o4, 0x80, %o4 + sub %GLOBAL_SPARE, 0x80, %GLOBAL_SPARE EX_LD(LOAD_BLK(%o1, %f32)) add %o1, 0x40, %o1 @@ -229,11 +231,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ .align 64 1: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16) - LOOP_CHUNK1(o1, o0, o4, 1f) + LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) - LOOP_CHUNK2(o1, o0, o4, 2f) + LOOP_CHUNK2(o1, o0, GLOBAL_SPARE, 2f) FREG_FROB(f32,f34,f36,f38,f40,f42,f44,f46,f0) - LOOP_CHUNK3(o1, o0, o4, 3f) + LOOP_CHUNK3(o1, o0, GLOBAL_SPARE, 3f) ba,pt %xcc, 1b+4 faligndata %f0, %f2, %f48 1: FREG_FROB(f16,f18,f20,f22,f24,f26,f28,f30,f32) @@ -250,11 +252,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ STORE_JUMP(o0, f48, 56f) membar #Sync 1: FREG_FROB(f2, f4, f6, f8, f10,f12,f14,f16,f18) - LOOP_CHUNK1(o1, o0, o4, 1f) + LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) - LOOP_CHUNK2(o1, o0, o4, 2f) + LOOP_CHUNK2(o1, o0, GLOBAL_SPARE, 2f) FREG_FROB(f34,f36,f38,f40,f42,f44,f46,f0, f2) - LOOP_CHUNK3(o1, o0, o4, 3f) + LOOP_CHUNK3(o1, o0, GLOBAL_SPARE, 3f) ba,pt %xcc, 1b+4 faligndata %f2, %f4, %f48 1: FREG_FROB(f18,f20,f22,f24,f26,f28,f30,f32,f34) @@ -271,11 +273,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ STORE_JUMP(o0, f48, 57f) membar #Sync 1: FREG_FROB(f4, f6, f8, f10,f12,f14,f16,f18,f20) - LOOP_CHUNK1(o1, o0, o4, 1f) + LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) - LOOP_CHUNK2(o1, o0, o4, 2f) + LOOP_CHUNK2(o1, o0, GLOBAL_SPARE, 2f) FREG_FROB(f36,f38,f40,f42,f44,f46,f0, f2, f4) - LOOP_CHUNK3(o1, o0, o4, 3f) + LOOP_CHUNK3(o1, o0, GLOBAL_SPARE, 3f) ba,pt %xcc, 1b+4 faligndata %f4, %f6, %f48 1: FREG_FROB(f20,f22,f24,f26,f28,f30,f32,f34,f36) @@ -292,11 +294,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ STORE_JUMP(o0, f48, 58f) membar #Sync 1: FREG_FROB(f6, f8, f10,f12,f14,f16,f18,f20,f22) - LOOP_CHUNK1(o1, o0, o4, 1f) + LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) - LOOP_CHUNK2(o1, o0, o4, 2f) + LOOP_CHUNK2(o1, o0, GLOBAL_SPARE, 2f) FREG_FROB(f38,f40,f42,f44,f46,f0, f2, f4, f6) - LOOP_CHUNK3(o1, o0, o4, 3f) + LOOP_CHUNK3(o1, o0, GLOBAL_SPARE, 3f) ba,pt %xcc, 1b+4 faligndata %f6, %f8, %f48 1: FREG_FROB(f22,f24,f26,f28,f30,f32,f34,f36,f38) @@ -313,11 +315,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ STORE_JUMP(o0, f48, 59f) membar #Sync 1: FREG_FROB(f8, f10,f12,f14,f16,f18,f20,f22,f24) - LOOP_CHUNK1(o1, o0, o4, 1f) + LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) - LOOP_CHUNK2(o1, o0, o4, 2f) + LOOP_CHUNK2(o1, o0, GLOBAL_SPARE, 2f) FREG_FROB(f40,f42,f44,f46,f0, f2, f4, f6, f8) - LOOP_CHUNK3(o1, o0, o4, 3f) + LOOP_CHUNK3(o1, o0, GLOBAL_SPARE, 3f) ba,pt %xcc, 1b+4 faligndata %f8, %f10, %f48 1: FREG_FROB(f24,f26,f28,f30,f32,f34,f36,f38,f40) @@ -334,11 +336,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ STORE_JUMP(o0, f48, 60f) membar #Sync 1: FREG_FROB(f10,f12,f14,f16,f18,f20,f22,f24,f26) - LOOP_CHUNK1(o1, o0, o4, 1f) + LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) - LOOP_CHUNK2(o1, o0, o4, 2f) + LOOP_CHUNK2(o1, o0, GLOBAL_SPARE, 2f) FREG_FROB(f42,f44,f46,f0, f2, f4, f6, f8, f10) - LOOP_CHUNK3(o1, o0, o4, 3f) + LOOP_CHUNK3(o1, o0, GLOBAL_SPARE, 3f) ba,pt %xcc, 1b+4 faligndata %f10, %f12, %f48 1: FREG_FROB(f26,f28,f30,f32,f34,f36,f38,f40,f42) @@ -355,11 +357,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ STORE_JUMP(o0, f48, 61f) membar #Sync 1: FREG_FROB(f12,f14,f16,f18,f20,f22,f24,f26,f28) - LOOP_CHUNK1(o1, o0, o4, 1f) + LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) - LOOP_CHUNK2(o1, o0, o4, 2f) + LOOP_CHUNK2(o1, o0, GLOBAL_SPARE, 2f) FREG_FROB(f44,f46,f0, f2, f4, f6, f8, f10,f12) - LOOP_CHUNK3(o1, o0, o4, 3f) + LOOP_CHUNK3(o1, o0, GLOBAL_SPARE, 3f) ba,pt %xcc, 1b+4 faligndata %f12, %f14, %f48 1: FREG_FROB(f28,f30,f32,f34,f36,f38,f40,f42,f44) @@ -376,11 +378,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ STORE_JUMP(o0, f48, 62f) membar #Sync 1: FREG_FROB(f14,f16,f18,f20,f22,f24,f26,f28,f30) - LOOP_CHUNK1(o1, o0, o4, 1f) + LOOP_CHUNK1(o1, o0, GLOBAL_SPARE, 1f) FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) - LOOP_CHUNK2(o1, o0, o4, 2f) + LOOP_CHUNK2(o1, o0, GLOBAL_SPARE, 2f) FREG_FROB(f46,f0, f2, f4, f6, f8, f10,f12,f14) - LOOP_CHUNK3(o1, o0, o4, 3f) + LOOP_CHUNK3(o1, o0, GLOBAL_SPARE, 3f) ba,pt %xcc, 1b+4 faligndata %f14, %f16, %f48 1: FREG_FROB(f30,f32,f34,f36,f38,f40,f42,f44,f46) @@ -449,18 +451,18 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ 2: membar #StoreLoad | #StoreStore VISExit retl - mov EX_RETVAL(%g5), %o0 + mov EX_RETVAL(%o4), %o0 .align 64 70: /* 16 < len <= (5 * 64) */ bne,pn %XCC, 75f sub %o0, %o1, %o3 -72: andn %o2, 0xf, %o4 +72: andn %o2, 0xf, %GLOBAL_SPARE and %o2, 0xf, %o2 1: EX_LD(LOAD(ldx, %o1 + 0x00, %o5)) EX_LD(LOAD(ldx, %o1 + 0x08, %g1)) - subcc %o4, 0x10, %o4 + subcc %GLOBAL_SPARE, 0x10, %GLOBAL_SPARE EX_ST(STORE(stx, %o5, %o1 + %o3)) add %o1, 0x8, %o1 EX_ST(STORE(stx, %g1, %o1 + %o3)) @@ -512,10 +514,10 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ andn %o1, 0x7, %o1 EX_LD(LOAD(ldx, %o1, %g2)) sub %o3, %g1, %o3 - andn %o2, 0x7, %o4 + andn %o2, 0x7, %GLOBAL_SPARE sllx %g2, %g1, %g2 1: EX_LD(LOAD(ldx, %o1 + 0x8, %g3)) - subcc %o4, 0x8, %o4 + subcc %GLOBAL_SPARE, 0x8, %GLOBAL_SPARE add %o1, 0x8, %o1 srlx %g3, %o3, %o5 or %o5, %g2, %o5 @@ -544,7 +546,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ add %o1, 4, %o1 85: retl - mov EX_RETVAL(%g5), %o0 + mov EX_RETVAL(%o4), %o0 .align 32 90: EX_LD(LOAD(ldub, %o1, %g1)) @@ -553,6 +555,6 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ bgu,pt %XCC, 90b add %o1, 1, %o1 retl - mov EX_RETVAL(%g5), %o0 + mov EX_RETVAL(%o4), %o0 .size FUNC_NAME, .-FUNC_NAME diff --git a/arch/sparc64/lib/U3memcpy.S b/arch/sparc64/lib/U3memcpy.S index 8fe195a10bbad..7cae9cc6a204a 100644 --- a/arch/sparc64/lib/U3memcpy.S +++ b/arch/sparc64/lib/U3memcpy.S @@ -6,6 +6,7 @@ #ifdef __KERNEL__ #include <asm/visasm.h> #include <asm/asi.h> +#define GLOBAL_SPARE %g7 #else #define ASI_BLK_P 0xf0 #define FPRS_FEF 0x04 @@ -17,6 +18,7 @@ #define VISEntryHalf rd %fprs, %o5; wr %g0, FPRS_FEF, %fprs #define VISExitHalf and %o5, FPRS_FEF, %o5; wr %o5, 0x0, %fprs #endif +#define GLOBAL_SPARE %g5 #endif #ifndef EX_LD @@ -84,7 +86,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ cmp %g2, 0 tne %xcc, 5 PREAMBLE - mov %o0, %g5 + mov %o0, %o4 cmp %o2, 0 be,pn %XCC, 85f or %o0, %o1, %o3 @@ -109,7 +111,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ * of bytes to copy to make 'dst' 64-byte aligned. We pre- * subtract this from 'len'. */ - sub %o0, %o1, %o4 + sub %o0, %o1, GLOBAL_SPARE sub %g2, 0x40, %g2 sub %g0, %g2, %g2 sub %o2, %g2, %o2 @@ -119,11 +121,11 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ 1: subcc %g1, 0x1, %g1 EX_LD(LOAD(ldub, %o1 + 0x00, %o3)) - EX_ST(STORE(stb, %o3, %o1 + %o4)) + EX_ST(STORE(stb, %o3, %o1 + GLOBAL_SPARE)) bgu,pt %XCC, 1b add %o1, 0x1, %o1 - add %o1, %o4, %o0 + add %o1, GLOBAL_SPARE, %o0 2: cmp %g2, 0x0 and %o1, 0x7, %g1 @@ -149,7 +151,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ 3: LOAD(prefetch, %o1 + 0x000, #one_read) LOAD(prefetch, %o1 + 0x040, #one_read) - andn %o2, (0x40 - 1), %o4 + andn %o2, (0x40 - 1), GLOBAL_SPARE LOAD(prefetch, %o1 + 0x080, #one_read) LOAD(prefetch, %o1 + 0x0c0, #one_read) LOAD(prefetch, %o1 + 0x100, #one_read) @@ -173,10 +175,10 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ faligndata %f10, %f12, %f26 EX_LD(LOAD(ldd, %o1 + 0x040, %f0)) - subcc %o4, 0x80, %o4 + subcc GLOBAL_SPARE, 0x80, GLOBAL_SPARE add %o1, 0x40, %o1 bgu,pt %XCC, 1f - srl %o4, 6, %o3 + srl GLOBAL_SPARE, 6, %o3 ba,pt %xcc, 2f nop @@ -315,9 +317,9 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ sub %o0, %o1, %o3 72: - andn %o2, 0xf, %o4 + andn %o2, 0xf, GLOBAL_SPARE and %o2, 0xf, %o2 -1: subcc %o4, 0x10, %o4 +1: subcc GLOBAL_SPARE, 0x10, GLOBAL_SPARE EX_LD(LOAD(ldx, %o1 + 0x00, %o5)) EX_LD(LOAD(ldx, %o1 + 0x08, %g1)) EX_ST(STORE(stx, %o5, %o1 + %o3)) @@ -372,10 +374,10 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ andn %o1, 0x7, %o1 EX_LD(LOAD(ldx, %o1, %g2)) sub %o3, %g1, %o3 - andn %o2, 0x7, %o4 + andn %o2, 0x7, GLOBAL_SPARE sllx %g2, %g1, %g2 1: EX_LD(LOAD(ldx, %o1 + 0x8, %g3)) - subcc %o4, 0x8, %o4 + subcc GLOBAL_SPARE, 0x8, GLOBAL_SPARE add %o1, 0x8, %o1 srlx %g3, %o3, %o5 or %o5, %g2, %o5 @@ -405,7 +407,7 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ add %o1, 4, %o1 85: retl - mov EX_RETVAL(%g5), %o0 + mov EX_RETVAL(%o4), %o0 .align 32 90: @@ -415,6 +417,6 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */ bgu,pt %XCC, 90b add %o1, 1, %o1 retl - mov EX_RETVAL(%g5), %o0 + mov EX_RETVAL(%o4), %o0 .size FUNC_NAME, .-FUNC_NAME diff --git a/arch/sparc64/lib/VIS.h b/arch/sparc64/lib/VIS.h deleted file mode 100644 index 9d93a70e7081f..0000000000000 --- a/arch/sparc64/lib/VIS.h +++ /dev/null @@ -1,128 +0,0 @@ -/* $Id: VIS.h,v 1.4 1999/05/25 16:52:50 jj Exp $ - * VIS.h: High speed copy/clear operations utilizing the UltraSparc - * Visual Instruction Set. - * - * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 1996, 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz) - */ - - /* VIS code can be used for numerous copy/set operation variants. - * It can be made to work in the kernel, one single instance, - * for all of memcpy, copy_to_user, and copy_from_user by setting - * the ASI src/dest globals correctly. Furthermore it can - * be used for kernel-->kernel page copies as well, a hook label - * is put in here just for this purpose. - * - * For userland, compiling this without __KERNEL__ defined makes - * it work just fine as a generic libc bcopy and memcpy. - * If for userland it is compiled with a 32bit gcc (but you need - * -Wa,-Av9a), the code will just rely on lower 32bits of - * IEU registers, if you compile it with 64bit gcc (ie. define - * __sparc_v9__), the code will use full 64bit. - */ - -#ifndef __VIS_H -#define __VIS_H - -#ifdef __KERNEL__ -#include <asm/head.h> -#include <asm/asi.h> -#else -#define ASI_AIUS 0x11 /* Secondary, user */ -#define ASI_BLK_AIUS 0x71 /* Secondary, user, blk ld/st */ -#define ASI_P 0x80 /* Primary, implicit */ -#define ASI_S 0x81 /* Secondary, implicit */ -#define ASI_BLK_COMMIT_P 0xe0 /* Primary, blk store commit */ -#define ASI_BLK_COMMIT_S 0xe1 /* Secondary, blk store commit */ -#define ASI_BLK_P 0xf0 /* Primary, blk ld/st */ -#define ASI_BLK_S 0xf1 /* Secondary, blk ld/st */ -#define FPRS_FEF 0x04 -#endif - - /* I'm telling you, they really did this chip right. - * Perhaps the SunSoft folks should visit some of the - * people in Sun Microelectronics and start some brain - * cell exchange program... - */ -#define ASI_BLK_XOR (ASI_P ^ ASI_BLK_P) - /* Well, things get more hairy if we use ASI_AIUS as - * USER_DS and ASI_P as KERNEL_DS, we'd reach - * commit block stores this way which is not what we want... - */ - /* ASI_P->ASI_BLK_P && ASI_AIUS->ASI_BLK_AIUS transitions can be done - * as blkasi = asi | ASI_BLK_OR - */ -#define ASI_BLK_OR (ASI_BLK_P & ~ASI_P) - /* Transition back from ASI_BLK_P->ASI_P && ASI_BLK_AIUS->ASI_AIUS is - * more complicated: - * asi = blkasi ^ (blkasi >> 3) ^ ASI_BLK_XOR1 - */ -#define ASI_BLK_XOR1 (ASI_BLK_P ^ (ASI_BLK_P >> 3) ^ ASI_P) - -#define asi_src %o3 -#define asi_dest %o4 - -#ifdef __KERNEL__ -#define ASI_SETSRC_BLK wr asi_src, 0, %asi; -#define ASI_SETSRC_NOBLK wr asi_src, 0, %asi; -#define ASI_SETDST_BLK wr asi_dest, 0, %asi; -#define ASI_SETDST_NOBLK wr asi_dest, 0, %asi; -#define ASIBLK %asi -#define ASINORMAL %asi -#define LDUB lduba -#define LDUH lduha -#define LDUW lduwa -#define LDX ldxa -#define LDD ldda -#define LDDF ldda -#define LDBLK ldda -#define STB stba -#define STH stha -#define STW stwa -#define STD stda -#define STX stxa -#define STDF stda -#define STBLK stda -#else -#define ASI_SETSRC_BLK -#define ASI_SETSRC_NOBLK -#define ASI_SETDST_BLK -#define ASI_SETDST_NOBLK -#define ASI_SETDST_SPECIAL -#define ASIBLK %asi -#define ASINORMAL -#define LDUB ldub -#define LDUH lduh -#define LDUW lduw -#define LDD ldd -#define LDX ldx -#define LDDF ldd -#define LDBLK ldda -#define STB stb -#define STH sth -#define STW stw -#define STD std -#define STX stx -#define STDF std -#define STBLK stda -#endif - -#ifdef __KERNEL__ - -#define REGS_64BIT - -#else - -#ifndef REGS_64BIT -#ifdef __sparc_v9__ -#define REGS_64BIT -#endif -#endif - -#endif - -#ifndef REGS_64BIT -#define xcc icc -#endif - -#endif diff --git a/arch/sparc64/lib/VISbzero.S b/arch/sparc64/lib/VISbzero.S deleted file mode 100644 index 06b697bab974b..0000000000000 --- a/arch/sparc64/lib/VISbzero.S +++ /dev/null @@ -1,274 +0,0 @@ -/* $Id: VISbzero.S,v 1.11 2001/03/15 08:51:24 anton Exp $ - * VISbzero.S: High speed clear operations utilizing the UltraSparc - * Visual Instruction Set. - * - * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 1996, 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz) - */ - -#include "VIS.h" - -#ifdef __KERNEL__ -#include <asm/visasm.h> - -#define EXN(x,y,a,b,z) \ -98: x,y; \ - .section .fixup; \ - .align 4; \ -99: ba VISbzerofixup_ret##z; \ - a, b, %o0; \ - .section __ex_table; \ - .align 4; \ - .word 98b, 99b; \ - .text; \ - .align 4; -#define EXC(x,y,a,b,c...) \ -98: x,y; \ - .section .fixup; \ - .align 4; \ -99: c; \ - ba VISbzerofixup_ret0; \ - a, b, %o0; \ - .section __ex_table; \ - .align 4; \ - .word 98b, 99b; \ - .text; \ - .align 4; -#define EXO1(x,y) \ -98: x,y; \ - .section __ex_table; \ - .align 4; \ - .word 98b, VISbzerofixup_reto1; \ - .text; \ - .align 4; -#define EX(x,y,a,b) EXN(x,y,a,b,0) -#define EX1(x,y,a,b) EXN(x,y,a,b,1) -#define EX2(x,y,a,b) EXN(x,y,a,b,2) -#define EXT(start,end,handler) \ - .section __ex_table; \ - .align 4; \ - .word start, 0, end, handler; \ - .text; \ - .align 4 -#else -#define EX(x,y,a,b) x,y -#define EX1(x,y,a,b) x,y -#define EX2(x,y,a,b) x,y -#define EXC(x,y,a,b,c...) x,y -#define EXO1(x,y) x,y -#define EXT(a,b,c) -#endif - -#define ZERO_BLOCKS(base, offset, source) \ - STX source, [base - offset - 0x38] ASINORMAL; \ - STX source, [base - offset - 0x30] ASINORMAL; \ - STX source, [base - offset - 0x28] ASINORMAL; \ - STX source, [base - offset - 0x20] ASINORMAL; \ - STX source, [base - offset - 0x18] ASINORMAL; \ - STX source, [base - offset - 0x10] ASINORMAL; \ - STX source, [base - offset - 0x08] ASINORMAL; \ - STX source, [base - offset - 0x00] ASINORMAL; - -#ifdef __KERNEL__ -#define RETL clr %o0 -#else -#define RETL mov %g3, %o0 -#endif - - /* Well, bzero is a lot easier to get right than bcopy... */ -#ifdef __KERNEL__ - .section __ex_table,#alloc - .section .fixup,#alloc,#execinstr -#endif - .text - .align 32 -#ifdef __KERNEL__ - .globl __bzero, __bzero_noasi -__bzero_noasi: - rd %asi, %g5 - ba,pt %xcc, __bzero+12 - mov %g5, %o4 -__bzero: - rd %asi, %g5 - wr %g0, ASI_P, %asi ! LSU Group - mov ASI_P, %o4 -#else - .globl bzero -bzero_private: -bzero: -#ifndef REGS_64BIT - srl %o1, 0, %o1 -#endif - mov %o0, %g3 -#endif - cmp %o1, 7 - bleu,pn %xcc, 17f - andcc %o0, 3, %o2 - be,a,pt %xcc, 4f - andcc %o0, 4, %g0 - cmp %o2, 3 - be,pn %xcc, 2f - EXO1(STB %g0, [%o0 + 0x00] ASINORMAL) - cmp %o2, 2 - be,pt %xcc, 2f - EX(STB %g0, [%o0 + 0x01] ASINORMAL, sub %o1, 1) - EX(STB %g0, [%o0 + 0x02] ASINORMAL, sub %o1, 2) -2: sub %o2, 4, %o2 - sub %o0, %o2, %o0 - add %o1, %o2, %o1 - andcc %o0, 4, %g0 -4: be,pt %xcc, 2f - cmp %o1, 128 - EXO1(STW %g0, [%o0] ASINORMAL) - sub %o1, 4, %o1 - add %o0, 4, %o0 -2: blu,pn %xcc, 9f - andcc %o0, 0x38, %o2 - be,pn %icc, 6f - mov 64, %o5 - andcc %o0, 8, %g0 - be,pn %icc, 1f - sub %o5, %o2, %o5 - EX(STX %g0, [%o0] ASINORMAL, sub %o1, 0) - add %o0, 8, %o0 -1: andcc %o5, 16, %g0 - be,pn %icc, 1f - sub %o1, %o5, %o1 - EX1(STX %g0, [%o0] ASINORMAL, add %g0, 0) - EX1(STX %g0, [%o0 + 8] ASINORMAL, sub %g0, 8) - add %o0, 16, %o0 -1: andcc %o5, 32, %g0 - be,pn %icc, 7f - andncc %o1, 0x3f, %o3 - EX(STX %g0, [%o0] ASINORMAL, add %o1, 32) - EX(STX %g0, [%o0 + 8] ASINORMAL, add %o1, 24) - EX(STX %g0, [%o0 + 16] ASINORMAL, add %o1, 16) - EX(STX %g0, [%o0 + 24] ASINORMAL, add %o1, 8) - add %o0, 32, %o0 -6: andncc %o1, 0x3f, %o3 -7: be,pn %xcc, 9f -#ifdef __KERNEL__ - or %o4, ASI_BLK_OR, %g7 - wr %g7, %g0, %asi - VISEntryHalf -#else - wr %g0, ASI_BLK_P, %asi -#endif - membar #StoreLoad | #StoreStore | #LoadStore - fzero %f0 - andcc %o3, 0xc0, %o2 - and %o1, 0x3f, %o1 - fzero %f2 - andn %o3, 0xff, %o3 - faddd %f0, %f2, %f4 - fmuld %f0, %f2, %f6 - cmp %o2, 64 - faddd %f0, %f2, %f8 - fmuld %f0, %f2, %f10 - faddd %f0, %f2, %f12 - brz,pn %o2, 10f - fmuld %f0, %f2, %f14 - be,pn %icc, 2f - EXC(STBLK %f0, [%o0 + 0x00] ASIBLK, add %o3, %o2, add %o2, %o1, %o2) - cmp %o2, 128 - be,pn %icc, 2f - EXC(STBLK %f0, [%o0 + 0x40] ASIBLK, add %o3, %o2, add %o2, %o1, %o2; sub %o2, 64, %o2) - EXC(STBLK %f0, [%o0 + 0x80] ASIBLK, add %o3, %o2, add %o2, %o1, %o2; sub %o2, 128, %o2) -2: brz,pn %o3, 12f - add %o0, %o2, %o0 -10: EX(STBLK %f0, [%o0 + 0x00] ASIBLK, add %o3, %o1) - EXC(STBLK %f0, [%o0 + 0x40] ASIBLK, add %o3, %o1, sub %o1, 64, %o1) - EXC(STBLK %f0, [%o0 + 0x80] ASIBLK, add %o3, %o1, sub %o1, 128, %o1) - EXC(STBLK %f0, [%o0 + 0xc0] ASIBLK, add %o3, %o1, sub %o1, 192, %o1) -11: subcc %o3, 256, %o3 - bne,pt %xcc, 10b - add %o0, 256, %o0 -12: -#ifdef __KERNEL__ - VISExitHalf - wr %o4, 0x0, %asi -#else -#ifndef REGS_64BIT - wr %g0, FPRS_FEF, %fprs -#endif -#endif - membar #StoreLoad | #StoreStore -9: andcc %o1, 0xf8, %o2 - be,pn %xcc, 13f - andcc %o1, 7, %o1 -#ifdef __KERNEL__ -14: sethi %hi(13f), %o4 - srl %o2, 1, %o3 - sub %o4, %o3, %o4 - jmpl %o4 + %lo(13f), %g0 - add %o0, %o2, %o0 -#else -14: rd %pc, %o4 - srl %o2, 1, %o3 - sub %o4, %o3, %o4 - jmpl %o4 + (13f - 14b), %g0 - add %o0, %o2, %o0 -#endif -12: ZERO_BLOCKS(%o0, 0xc8, %g0) - ZERO_BLOCKS(%o0, 0x88, %g0) - ZERO_BLOCKS(%o0, 0x48, %g0) - ZERO_BLOCKS(%o0, 0x08, %g0) - EXT(12b,13f,VISbzerofixup_zb) -13: be,pn %xcc, 8f - andcc %o1, 4, %g0 - be,pn %xcc, 1f - andcc %o1, 2, %g0 - EX(STW %g0, [%o0] ASINORMAL, and %o1, 7) - add %o0, 4, %o0 -1: be,pn %xcc, 1f - andcc %o1, 1, %g0 - EX(STH %g0, [%o0] ASINORMAL, and %o1, 3) - add %o0, 2, %o0 -1: bne,a,pn %xcc, 8f - EX(STB %g0, [%o0] ASINORMAL, add %g0, 1) -8: -#ifdef __KERNEL__ - wr %g5, %g0, %asi -#endif - retl - RETL -17: be,pn %xcc, 13b - orcc %o1, 0, %g0 - be,pn %xcc, 0f -8: add %o0, 1, %o0 - subcc %o1, 1, %o1 - bne,pt %xcc, 8b - EX(STB %g0, [%o0 - 1] ASINORMAL, add %o1, 1) -0: -#ifdef __KERNEL__ - wr %g5, %g0, %asi -#endif - retl - RETL - -#ifdef __KERNEL__ - .section .fixup - .align 4 -VISbzerofixup_reto1: - mov %o1, %o0 -VISbzerofixup_ret0: - wr %g5, %g0, %asi - retl - wr %g0, 0, %fprs -VISbzerofixup_ret1: - and %o5, 0x30, %o5 - add %o5, %o1, %o5 - ba,pt %xcc, VISbzerofixup_ret0 - add %o0, %o5, %o0 -VISbzerofixup_ret2: - and %o5, 0x20, %o5 - add %o5, %o1, %o5 - ba,pt %xcc, VISbzerofixup_ret0 - add %o0, %o5, %o0 -VISbzerofixup_zb: - andcc %o1, 7, %o1 - sll %g2, 3, %g2 - add %o1, 256, %o1 - ba,pt %xcc, VISbzerofixup_ret0 - sub %o1, %g2, %o0 -#endif diff --git a/arch/sparc64/lib/VIScsum.S b/arch/sparc64/lib/VIScsum.S deleted file mode 100644 index ae00e9fb17e6e..0000000000000 --- a/arch/sparc64/lib/VIScsum.S +++ /dev/null @@ -1,546 +0,0 @@ -/* $Id: VIScsum.S,v 1.7 2002/02/09 19:49:30 davem Exp $ - * VIScsum.S: High bandwidth IP checksumming utilizing the UltraSparc - * Visual Instruction Set. - * - * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) - * Copyright (C) 2000 David S. Miller (davem@redhat.com) - * - * Based on older sparc32/sparc64 checksum.S, which is: - * - * Copyright(C) 1995 Linus Torvalds - * Copyright(C) 1995 Miguel de Icaza - * Copyright(C) 1996, 1997 David S. Miller - * derived from: - * Linux/Alpha checksum c-code - * Linux/ix86 inline checksum assembly - * RFC1071 Computing the Internet Checksum (esp. Jacobsons m68k code) - * David Mosberger-Tang for optimized reference c-code - * BSD4.4 portable checksum routine - */ - -#ifdef __sparc_v9__ -#define STACKOFF 2175 -#else -#define STACKOFF 64 -#endif - -#ifdef __KERNEL__ -#include <asm/head.h> -#include <asm/asi.h> -#include <asm/visasm.h> -#include <asm/thread_info.h> -#else -#define ASI_BLK_P 0xf0 -#define FRPS_FEF 0x04 -#endif - -/* Dobrou noc, SunSoft engineers. Spete sladce. - * This has a couple of tricks in and those - * tricks are UltraLinux trade secrets :)) - */ - -#define START_THE_TRICK(fz,f0,f2,f4,f6,f8,f10) \ - fcmpgt32 %fz, %f0, %g1 /* FPM Group */; \ - fcmpgt32 %fz, %f2, %g2 /* FPM Group */; \ - fcmpgt32 %fz, %f4, %g3 /* FPM Group */; \ - inc %g1 /* IEU0 Group */; \ - fcmpgt32 %fz, %f6, %g5 /* FPM */; \ - srl %g1, 1, %g1 /* IEU0 Group */; \ - fcmpgt32 %fz, %f8, %g7 /* FPM */; \ - inc %g2 /* IEU0 Group */; \ - fcmpgt32 %fz, %f10, %o3 /* FPM */; \ - srl %g2, 1, %g2 /* IEU0 Group */; \ - inc %g3 /* IEU1 */; \ - srl %g3, 1, %g3 /* IEU0 Group */; \ - add %o2, %g1, %o2 /* IEU1 */; \ - add %o2, %g2, %o2 /* IEU0 Group */; \ - inc %g5 /* IEU1 */; \ - add %o2, %g3, %o2 /* IEU0 Group */; - -#define DO_THE_TRICK(O12,O14,f0,f2,f4,f6,f8,f10,f12,f14,F0,F2,F4,F6,F8,F10,F12,F14) \ - srl %g5, 1, %g5 /* IEU0 Group */; \ - fpadd32 %F0, %f0, %F0 /* FPA */; \ - fcmpgt32 %O12, %f12, %o4 /* FPM */; \ - inc %g7 /* IEU0 Group */; \ - fpadd32 %F2, %f2, %F2 /* FPA */; \ - fcmpgt32 %O14, %f14, %o5 /* FPM */; \ - add %o2, %g5, %o2 /* IEU1 Group */; \ - fpadd32 %F4, %f4, %F4 /* FPA */; \ - fcmpgt32 %f0, %F0, %g1 /* FPM */; \ - srl %g7, 1, %g7 /* IEU0 Group */; \ - fpadd32 %F6, %f6, %F6 /* FPA */; \ - fcmpgt32 %f2, %F2, %g2 /* FPM */; \ - add %o2, %g7, %o2 /* IEU0 Group */; \ - fpadd32 %F8, %f8, %F8 /* FPA */; \ - fcmpgt32 %f4, %F4, %g3 /* FPM */; \ - inc %o3 /* IEU0 Group */; \ - fpadd32 %F10, %f10, %F10 /* FPA */; \ - fcmpgt32 %f6, %F6, %g5 /* FPM */; \ - srl %o3, 1, %o3 /* IEU0 Group */; \ - fpadd32 %F12, %f12, %F12 /* FPA */; \ - fcmpgt32 %f8, %F8, %g7 /* FPM */; \ - add %o2, %o3, %o2 /* IEU0 Group */; \ - fpadd32 %F14, %f14, %F14 /* FPA */; \ - fcmpgt32 %f10, %F10, %o3 /* FPM */; \ - inc %o4 /* IEU0 Group */; \ - inc %o5 /* IEU1 */; \ - srl %o4, 1, %o4 /* IEU0 Group */; \ - inc %g1 /* IEU1 */; \ - srl %o5, 1, %o5 /* IEU0 Group */; \ - add %o2, %o4, %o2 /* IEU1 */; \ - srl %g1, 1, %g1 /* IEU0 Group */; \ - add %o2, %o5, %o2 /* IEU1 */; \ - inc %g2 /* IEU0 Group */; \ - add %o2, %g1, %o2 /* IEU1 */; \ - srl %g2, 1, %g2 /* IEU0 Group */; \ - inc %g3 /* IEU1 */; \ - srl %g3, 1, %g3 /* IEU0 Group */; \ - add %o2, %g2, %o2 /* IEU1 */; \ - inc %g5 /* IEU0 Group */; \ - add %o2, %g3, %o2 /* IEU0 */; - -#define END_THE_TRICK(O12,O14,f0,f2,f4,f6,f8,f10,f12,f14,S0,S1,S2,S3,T0,T1,U0,fz) \ - srl %g5, 1, %g5 /* IEU0 Group */; \ - fpadd32 %f2, %f0, %S0 /* FPA */; \ - fcmpgt32 %O12, %f12, %o4 /* FPM */; \ - inc %g7 /* IEU0 Group */; \ - fpadd32 %f6, %f4, %S1 /* FPA */; \ - fcmpgt32 %O14, %f14, %o5 /* FPM */; \ - srl %g7, 1, %g7 /* IEU0 Group */; \ - fpadd32 %f10, %f8, %S2 /* FPA */; \ - fcmpgt32 %f0, %S0, %g1 /* FPM */; \ - inc %o3 /* IEU0 Group */; \ - fpadd32 %f14, %f12, %S3 /* FPA */; \ - fcmpgt32 %f4, %S1, %g2 /* FPM */; \ - add %o2, %g5, %o2 /* IEU0 Group */; \ - fpadd32 %S0, %S1, %T0 /* FPA */; \ - fcmpgt32 %f8, %S2, %g3 /* FPM */; \ - add %o2, %g7, %o2 /* IEU0 Group */; \ - fzero %fz /* FPA */; \ - fcmpgt32 %f12, %S3, %g5 /* FPM */; \ - srl %o3, 1, %o3 /* IEU0 Group */; \ - fpadd32 %S2, %S3, %T1 /* FPA */; \ - fcmpgt32 %S0, %T0, %g7 /* FPM */; \ - add %o2, %o3, %o2 /* IEU0 Group */; \ - fpadd32 %T0, %T1, %U0 /* FPA */; \ - fcmpgt32 %S2, %T1, %o3 /* FPM */; \ - inc %o4 /* IEU0 Group */; \ - inc %o5 /* IEU1 */; \ - srl %o4, 1, %o4 /* IEU0 Group */; \ - inc %g1 /* IEU1 */; \ - add %o2, %o4, %o2 /* IEU0 Group */; \ - fcmpgt32 %fz, %f2, %o4 /* FPM */; \ - srl %o5, 1, %o5 /* IEU0 Group */; \ - inc %g2 /* IEU1 */; \ - add %o2, %o5, %o2 /* IEU0 Group */; \ - fcmpgt32 %fz, %f6, %o5 /* FPM */; \ - srl %g1, 1, %g1 /* IEU0 Group */; \ - inc %g3 /* IEU1 */; \ - add %o2, %g1, %o2 /* IEU0 Group */; \ - fcmpgt32 %fz, %f10, %g1 /* FPM */; \ - srl %g2, 1, %g2 /* IEU0 Group */; \ - inc %g5 /* IEU1 */; \ - add %o2, %g2, %o2 /* IEU0 Group */; \ - fcmpgt32 %fz, %f14, %g2 /* FPM */; \ - srl %g3, 1, %g3 /* IEU0 Group */; \ - inc %g7 /* IEU1 */; \ - add %o2, %g3, %o2 /* IEU0 Group */; \ - fcmpgt32 %fz, %S1, %g3 /* FPM */; \ - srl %g5, 1, %g5 /* IEU0 Group */; \ - inc %o3 /* IEU1 */; \ - add %o2, %g5, %o2 /* IEU0 Group */; \ - fcmpgt32 %fz, %S3, %g5 /* FPM */; \ - srl %g7, 1, %g7 /* IEU0 Group */; \ - inc %o4 /* IEU1 */; \ - add %o2, %g7, %o2 /* IEU0 Group */; \ - fcmpgt32 %fz, %T1, %g7 /* FPM */; \ - srl %o3, 1, %o3 /* IEU0 Group */; \ - inc %o5 /* IEU1 */; \ - add %o2, %o3, %o2 /* IEU0 Group */; \ - fcmpgt32 %T0, %U0, %o3 /* FPM */; \ - srl %o4, 1, %o4 /* IEU0 Group */; \ - inc %g1 /* IEU1 */; \ - sub %o2, %o4, %o2 /* IEU0 Group */; \ - fcmpgt32 %fz, %U0, %o4 /* FPM */; \ - srl %o5, 1, %o5 /* IEU0 Group */; \ - inc %g2 /* IEU1 */; \ - srl %g1, 1, %g1 /* IEU0 Group */; \ - sub %o2, %o5, %o2 /* IEU1 */; \ - std %U0, [%sp + STACKOFF] /* Store */; \ - srl %g2, 1, %g2 /* IEU0 Group */; \ - sub %o2, %g1, %o2 /* IEU1 */; \ - inc %g3 /* IEU0 Group */; \ - sub %o2, %g2, %o2 /* IEU1 */; \ - srl %g3, 1, %g3 /* IEU0 Group */; \ - inc %g5 /* IEU1 */; \ - srl %g5, 1, %g5 /* IEU0 Group */; \ - sub %o2, %g3, %o2 /* IEU1 */; \ - ldx [%sp + STACKOFF], %o5 /* Load Group */; \ - inc %g7 /* IEU0 */; \ - sub %o2, %g5, %o2 /* IEU1 */; \ - srl %g7, 1, %g7 /* IEU0 Group */; \ - inc %o3 /* IEU1 */; \ - srl %o3, 1, %o3 /* IEU0 Group */; \ - sub %o2, %g7, %o2 /* IEU1 */; \ - inc %o4 /* IEU0 Group */; \ - add %o2, %o3, %o2 /* IEU1 */; \ - srl %o4, 1, %o4 /* IEU0 Group */; \ - sub %o2, %o4, %o2 /* IEU0 Group */; \ - addcc %o2, %o5, %o2 /* IEU1 Group */; \ - bcs,a,pn %xcc, 33f /* CTI */; \ - add %o2, 1, %o2 /* IEU0 */; \ -33: /* That's it */; - -#define CSUM_LASTCHUNK(offset) \ - ldx [%o0 - offset - 0x10], %g2; \ - ldx [%o0 - offset - 0x08], %g3; \ - addcc %g2, %o2, %o2; \ - bcs,a,pn %xcc, 31f; \ - add %o2, 1, %o2; \ -31: addcc %g3, %o2, %o2; \ - bcs,a,pn %xcc, 32f; \ - add %o2, 1, %o2; \ -32: - - .text - .globl csum_partial - .align 32 -csum_partial: - andcc %o0, 7, %g0 /* IEU1 Group */ - be,pt %icc, 4f /* CTI */ - andcc %o0, 0x38, %g3 /* IEU1 */ - mov 1, %g5 /* IEU0 Group */ - cmp %o1, 6 /* IEU1 */ - bl,pn %icc, 21f /* CTI */ - andcc %o0, 1, %g0 /* IEU1 Group */ - bne,pn %icc, csump_really_slow /* CTI */ - andcc %o0, 2, %g0 /* IEU1 Group */ - be,pt %icc, 1f /* CTI */ - and %o0, 4, %g7 /* IEU0 */ - lduh [%o0], %g2 /* Load */ - sub %o1, 2, %o1 /* IEU0 Group */ - add %o0, 2, %o0 /* IEU1 */ - andcc %o0, 4, %g7 /* IEU1 Group */ - sll %g5, 16, %g5 /* IEU0 */ - sll %g2, 16, %g2 /* IEU0 Group */ - addcc %g2, %o2, %o2 /* IEU1 Group (regdep) */ - bcs,a,pn %icc, 1f /* CTI */ - add %o2, %g5, %o2 /* IEU0 */ -1: ld [%o0], %g2 /* Load */ - brz,a,pn %g7, 4f /* CTI+IEU1 Group */ - and %o0, 0x38, %g3 /* IEU0 */ - add %o0, 4, %o0 /* IEU0 Group */ - sub %o1, 4, %o1 /* IEU1 */ - addcc %g2, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %icc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: and %o0, 0x38, %g3 /* IEU1 Group */ -4: srl %o2, 0, %o2 /* IEU0 Group */ - mov 0x40, %g1 /* IEU1 */ - brz,pn %g3, 3f /* CTI+IEU1 Group */ - sub %g1, %g3, %g1 /* IEU0 */ - cmp %o1, 56 /* IEU1 Group */ - blu,pn %icc, 20f /* CTI */ - andcc %o0, 8, %g0 /* IEU1 Group */ - be,pn %icc, 1f /* CTI */ - ldx [%o0], %g2 /* Load */ - add %o0, 8, %o0 /* IEU0 Group */ - sub %o1, 8, %o1 /* IEU1 */ - addcc %g2, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: andcc %g1, 0x10, %g0 /* IEU1 Group */ - be,pn %icc, 2f /* CTI */ - and %g1, 0x20, %g1 /* IEU0 */ - ldx [%o0], %g2 /* Load */ - ldx [%o0+8], %g3 /* Load Group */ - add %o0, 16, %o0 /* IEU0 */ - sub %o1, 16, %o1 /* IEU1 */ - addcc %g2, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: addcc %g3, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %xcc, 2f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -2: brz,pn %g1, 3f /* CTI+IEU1 Group */ - ldx [%o0], %g2 /* Load */ - ldx [%o0+8], %g3 /* Load Group */ - ldx [%o0+16], %g5 /* Load Group */ - ldx [%o0+24], %g7 /* Load Group */ - add %o0, 32, %o0 /* IEU0 */ - sub %o1, 32, %o1 /* IEU1 */ - addcc %g2, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: addcc %g3, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: addcc %g5, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: addcc %g7, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %xcc, 3f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -3: cmp %o1, 0xc0 /* IEU1 Group */ - blu,pn %icc, 20f /* CTI */ - sllx %o2, 32, %g5 /* IEU0 */ -#ifdef __KERNEL__ - VISEntry -#endif - addcc %o2, %g5, %o2 /* IEU1 Group */ - sub %o1, 0xc0, %o1 /* IEU0 */ - wr %g0, ASI_BLK_P, %asi /* LSU Group */ - membar #StoreLoad /* LSU Group */ - srlx %o2, 32, %o2 /* IEU0 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU1 */ -1: andcc %o1, 0x80, %g0 /* IEU1 Group */ - bne,pn %icc, 7f /* CTI */ - andcc %o1, 0x40, %g0 /* IEU1 Group */ - be,pn %icc, 6f /* CTI */ - fzero %f12 /* FPA */ - fzero %f14 /* FPA Group */ - ldda [%o0 + 0x000] %asi, %f16 - ldda [%o0 + 0x040] %asi, %f32 - ldda [%o0 + 0x080] %asi, %f48 - START_THE_TRICK(f12,f16,f18,f20,f22,f24,f26) - ba,a,pt %xcc, 3f -6: sub %o0, 0x40, %o0 /* IEU0 Group */ - fzero %f28 /* FPA */ - fzero %f30 /* FPA Group */ - ldda [%o0 + 0x040] %asi, %f32 - ldda [%o0 + 0x080] %asi, %f48 - ldda [%o0 + 0x0c0] %asi, %f0 - START_THE_TRICK(f28,f32,f34,f36,f38,f40,f42) - ba,a,pt %xcc, 4f -7: bne,pt %icc, 8f /* CTI */ - fzero %f44 /* FPA */ - add %o0, 0x40, %o0 /* IEU0 Group */ - fzero %f60 /* FPA */ - fzero %f62 /* FPA Group */ - ldda [%o0 - 0x040] %asi, %f0 - ldda [%o0 + 0x000] %asi, %f16 - ldda [%o0 + 0x040] %asi, %f32 - START_THE_TRICK(f60,f0,f2,f4,f6,f8,f10) - ba,a,pt %xcc, 2f -8: add %o0, 0x80, %o0 /* IEU0 Group */ - fzero %f46 /* FPA */ - ldda [%o0 - 0x080] %asi, %f48 - ldda [%o0 - 0x040] %asi, %f0 - ldda [%o0 + 0x000] %asi, %f16 - START_THE_TRICK(f44,f48,f50,f52,f54,f56,f58) -1: DO_THE_TRICK(f44,f46,f48,f50,f52,f54,f56,f58,f60,f62,f0,f2,f4,f6,f8,f10,f12,f14) - ldda [%o0 + 0x040] %asi, %f32 -2: DO_THE_TRICK(f60,f62,f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30) - ldda [%o0 + 0x080] %asi, %f48 -3: DO_THE_TRICK(f12,f14,f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46) - ldda [%o0 + 0x0c0] %asi, %f0 -4: DO_THE_TRICK(f28,f30,f32,f34,f36,f38,f40,f42,f44,f46,f48,f50,f52,f54,f56,f58,f60,f62) - add %o0, 0x100, %o0 /* IEU0 Group */ - subcc %o1, 0x100, %o1 /* IEU1 */ - bgeu,a,pt %icc, 1b /* CTI */ - ldda [%o0 + 0x000] %asi, %f16 - membar #Sync /* LSU Group */ - DO_THE_TRICK(f44,f46,f48,f50,f52,f54,f56,f58,f60,f62,f0,f2,f4,f6,f8,f10,f12,f14) - END_THE_TRICK(f60,f62,f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30) -#ifdef __KERNEL__ - ldub [%g6 + TI_CURRENT_DS], %g7 -#endif - and %o1, 0x3f, %o1 /* IEU0 Group */ -#ifdef __KERNEL__ - VISExit - wr %g7, %g0, %asi -#endif -20: andcc %o1, 0xf0, %g1 /* IEU1 Group */ - be,pn %icc, 23f /* CTI */ - and %o1, 0xf, %o3 /* IEU0 */ -#ifdef __KERNEL__ -22: sll %g1, 1, %o4 /* IEU0 Group */ - sethi %hi(23f), %g7 /* IEU1 */ - sub %g7, %o4, %g7 /* IEU0 Group */ - jmpl %g7 + %lo(23f), %g0 /* CTI Group brk forced*/ - add %o0, %g1, %o0 /* IEU0 */ -#else -22: rd %pc, %g7 /* LSU Group+4bubbles */ - sll %g1, 1, %o4 /* IEU0 Group */ - sub %g7, %o4, %g7 /* IEU0 Group (regdep) */ - jmpl %g7 + (23f - 22b), %g0 /* CTI Group brk forced*/ - add %o0, %g1, %o0 /* IEU0 */ -#endif - CSUM_LASTCHUNK(0xe0) - CSUM_LASTCHUNK(0xd0) - CSUM_LASTCHUNK(0xc0) - CSUM_LASTCHUNK(0xb0) - CSUM_LASTCHUNK(0xa0) - CSUM_LASTCHUNK(0x90) - CSUM_LASTCHUNK(0x80) - CSUM_LASTCHUNK(0x70) - CSUM_LASTCHUNK(0x60) - CSUM_LASTCHUNK(0x50) - CSUM_LASTCHUNK(0x40) - CSUM_LASTCHUNK(0x30) - CSUM_LASTCHUNK(0x20) - CSUM_LASTCHUNK(0x10) - CSUM_LASTCHUNK(0x00) -23: brnz,pn %o3, 26f /* CTI+IEU1 Group */ -24: sllx %o2, 32, %g1 /* IEU0 */ -25: addcc %o2, %g1, %o0 /* IEU1 Group */ - srlx %o0, 32, %o0 /* IEU0 Group (regdep) */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o0, 1, %o0 /* IEU1 */ -1: retl /* CTI Group brk forced*/ - srl %o0, 0, %o0 /* IEU0 */ -26: andcc %o1, 8, %g0 /* IEU1 Group */ - be,pn %icc, 1f /* CTI */ - ldx [%o0], %g3 /* Load */ - add %o0, 8, %o0 /* IEU0 Group */ - addcc %g3, %o2, %o2 /* IEU1 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: andcc %o1, 4, %g0 /* IEU1 Group */ - be,a,pn %icc, 1f /* CTI */ - clr %g2 /* IEU0 */ - ld [%o0], %g2 /* Load */ - add %o0, 4, %o0 /* IEU0 Group */ - sllx %g2, 32, %g2 /* IEU0 Group */ -1: andcc %o1, 2, %g0 /* IEU1 */ - be,a,pn %icc, 1f /* CTI */ - clr %o4 /* IEU0 Group */ - lduh [%o0], %o4 /* Load */ - add %o0, 2, %o0 /* IEU1 */ - sll %o4, 16, %o4 /* IEU0 Group */ -1: andcc %o1, 1, %g0 /* IEU1 */ - be,a,pn %icc, 1f /* CTI */ - clr %o5 /* IEU0 Group */ - ldub [%o0], %o5 /* Load */ - sll %o5, 8, %o5 /* IEU0 Group */ -1: or %g2, %o4, %o4 /* IEU1 */ - or %o5, %o4, %o4 /* IEU0 Group (regdep) */ - addcc %o4, %o2, %o2 /* IEU1 Group (regdep) */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: ba,pt %xcc, 25b /* CTI Group */ - sllx %o2, 32, %g1 /* IEU0 */ -21: srl %o2, 0, %o2 /* IEU0 Group */ - cmp %o1, 0 /* IEU1 */ - be,pn %icc, 24b /* CTI */ - andcc %o1, 4, %g0 /* IEU1 Group */ - be,a,pn %icc, 1f /* CTI */ - clr %g2 /* IEU0 */ - lduh [%o0], %g3 /* Load */ - lduh [%o0+2], %g2 /* Load Group */ - add %o0, 4, %o0 /* IEU0 Group */ - sllx %g3, 48, %g3 /* IEU0 Group */ - sllx %g2, 32, %g2 /* IEU0 Group */ - or %g3, %g2, %g2 /* IEU0 Group */ -1: andcc %o1, 2, %g0 /* IEU1 */ - be,a,pn %icc, 1f /* CTI */ - clr %o4 /* IEU0 Group */ - lduh [%o0], %o4 /* Load */ - add %o0, 2, %o0 /* IEU1 */ - sll %o4, 16, %o4 /* IEU0 Group */ -1: andcc %o1, 1, %g0 /* IEU1 */ - be,a,pn %icc, 1f /* CTI */ - clr %o5 /* IEU0 Group */ - ldub [%o0], %o5 /* Load */ - sll %o5, 8, %o5 /* IEU0 Group */ -1: or %g2, %o4, %o4 /* IEU1 */ - or %o5, %o4, %o4 /* IEU0 Group (regdep) */ - addcc %o4, %o2, %o2 /* IEU1 Group (regdep) */ - bcs,a,pn %xcc, 1f /* CTI */ - add %o2, 1, %o2 /* IEU0 */ -1: ba,pt %xcc, 25b /* CTI Group */ - sllx %o2, 32, %g1 /* IEU0 */ - - /* When buff is byte aligned and len is large, we backoff to - * this really slow handling. The issue is that we cannot do - * the VIS stuff when buff is byte aligned as unaligned.c will - * not fix it up. - */ -csump_really_slow: - mov %o0, %o3 - mov %o1, %o4 - cmp %o1, 0 - ble,pn %icc, 9f - mov 0, %o0 - andcc %o3, 1, %o5 - be,pt %icc, 1f - sra %o4, 1, %g3 - add %o1, -1, %o4 - ldub [%o3], %o0 - add %o3, 1, %o3 - sra %o4, 1, %g3 -1: - cmp %g3, 0 - be,pt %icc, 3f - and %o4, 1, %g2 - and %o3, 2, %g2 - brz,a,pt %g2, 1f - sra %g3, 1, %g3 - add %g3, -1, %g3 - add %o4, -2, %o4 - lduh [%o3], %g2 - add %o3, 2, %o3 - add %o0, %g2, %o0 - sra %g3, 1, %g3 -1: - cmp %g3, 0 - be,pt %icc, 2f - and %o4, 2, %g2 -1: - ld [%o3], %g2 - addcc %o0, %g2, %o0 - addx %o0, %g0, %o0 - addcc %g3, -1, %g3 - bne,pt %icc, 1b - add %o3, 4, %o3 - srl %o0, 16, %o1 - sethi %hi(64512), %g2 - or %g2, 1023, %g2 - and %o0, %g2, %g3 - add %g3, %o1, %g3 - srl %g3, 16, %o0 - and %g3, %g2, %g2 - add %g2, %o0, %g3 - sll %g3, 16, %g3 - srl %g3, 16, %o0 - and %o4, 2, %g2 -2: - cmp %g2, 0 - be,pt %icc, 3f - and %o4, 1, %g2 - lduh [%o3], %g2 - add %o3, 2, %o3 - add %o0, %g2, %o0 - and %o4, 1, %g2 -3: - cmp %g2, 0 - be,pt %icc, 1f - srl %o0, 16, %o1 - ldub [%o3], %g2 - sll %g2, 8, %g2 - add %o0, %g2, %o0 - srl %o0, 16, %o1 -1: - sethi %hi(64512), %g2 - or %g2, 1023, %g2 - cmp %o5, 0 - and %o0, %g2, %g3 - add %g3, %o1, %g3 - srl %g3, 16, %o0 - and %g3, %g2, %g2 - add %g2, %o0, %g3 - sll %g3, 16, %g3 - srl %g3, 16, %o0 - srl %g3, 24, %g3 - and %o0, 255, %g2 - sll %g2, 8, %g2 - bne,pt %icc, 1f - or %g3, %g2, %g2 -9: - mov %o0, %g2 -1: - addcc %g2, %o2, %g2 - addx %g2, %g0, %g2 - retl - srl %g2, 0, %o0 diff --git a/arch/sparc64/lib/VIScsumcopy.S b/arch/sparc64/lib/VIScsumcopy.S deleted file mode 100644 index d4caa955ea738..0000000000000 --- a/arch/sparc64/lib/VIScsumcopy.S +++ /dev/null @@ -1,897 +0,0 @@ -/* $Id: VIScsumcopy.S,v 1.8 2000/02/20 23:21:39 davem Exp $ - * VIScsumcopy.S: High bandwidth IP checksumming with simultaneous - * copying utilizing the UltraSparc Visual Instruction Set. - * - * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz) - * - * Based on older sparc32/sparc64 checksum.S, which is: - * - * Copyright(C) 1995 Linus Torvalds - * Copyright(C) 1995 Miguel de Icaza - * Copyright(C) 1996,1997 David S. Miller - * derived from: - * Linux/Alpha checksum c-code - * Linux/ix86 inline checksum assembly - * RFC1071 Computing the Internet Checksum (esp. Jacobsons m68k code) - * David Mosberger-Tang for optimized reference c-code - * BSD4.4 portable checksum routine - */ - -#ifdef __sparc_v9__ -#define STACKOFF 0x7ff+128 -#else -#define STACKOFF 64 -#endif - -#ifdef __KERNEL__ -#include <asm/head.h> -#include <asm/asi.h> -#include <asm/page.h> -#include <asm/visasm.h> -#include <asm/thread_info.h> -#define ASI_BLK_XOR 0 -#define ASI_BLK_XOR1 (ASI_BLK_P ^ (ASI_BLK_P >> 3) ^ ASI_P) -#define ASI_BLK_OR (ASI_BLK_P & ~ASI_P) -#else -#define ASI_P 0x80 -#define ASI_BLK_P 0xf0 -#define FRPS_FEF 0x04 -#define FPRS_DU 0x02 -#define FPRS_DL 0x01 -#define ASI_BLK_XOR (ASI_BLK_P ^ ASI_P) -#endif - -#define src o0 -#define dst o1 -#define len o2 -#define sum o3 -#define x1 g1 -#define x2 g2 -#define x3 o4 -#define x4 g4 -#define x5 g5 -#define x6 g7 -#define x7 g3 -#define x8 o5 - -/* Dobrou noc, SunSoft engineers. Spete sladce. - * This has a couple of tricks in and those - * tricks are UltraLinux trade secrets :)) - * Once AGAIN, the SunSoft engineers are caught - * asleep at the keyboard :)). - * The main loop does about 20 superscalar cycles - * per 64bytes checksummed/copied. - */ - -#define LDBLK(O0) \ - ldda [%src] %asi, %O0 /* Load Group */ - -#define STBLK \ - stda %f48, [%dst] ASI_BLK_P /* Store */ - -#define ST(fx,off) \ - std %fx, [%dst + off] /* Store */ - -#define SYNC \ - membar #Sync - - -#define DO_THE_TRICK(f0,f2,f4,f6,f8,f10,f12,f14,F0,F2,F4,F6,F8,F10,F12,F14,DUMMY1,A0,A2,A4,A6,A8,A10,A12,A14,B14,DUMMY2,LOAD,STORE1,STORE2,STORE3,STORE4,STORE5,STORE6,STORE7,STORE8,DUMMY3,BRANCH...) \ - LOAD /* Load (Group) */; \ - faligndata %A14, %F0, %A14 /* FPA Group */; \ - inc %x5 /* IEU0 */; \ - STORE1 /* Store (optional) */; \ - faligndata %F0, %F2, %A0 /* FPA Group */; \ - srl %x5, 1, %x5 /* IEU0 */; \ - add %sum, %x4, %sum /* IEU1 */; \ - fpadd32 %F0, %f0, %F0 /* FPA Group */; \ - inc %x6 /* IEU0 */; \ - STORE2 /* Store (optional) */; \ - faligndata %F2, %F4, %A2 /* FPA Group */; \ - srl %x6, 1, %x6 /* IEU0 */; \ - add %sum, %x5, %sum /* IEU1 */; \ - fpadd32 %F2, %f2, %F2 /* FPA Group */; \ - add %src, 64, %src /* IEU0 */; \ - fcmpgt32 %f0, %F0, %x1 /* FPM */; \ - add %dst, 64, %dst /* IEU1 Group */; \ - inc %x7 /* IEU0 */; \ - STORE3 /* Store (optional) */; \ - faligndata %F4, %F6, %A4 /* FPA */; \ - fpadd32 %F4, %f4, %F4 /* FPA Group */; \ - add %sum, %x6, %sum /* IEU1 */; \ - fcmpgt32 %f2, %F2, %x2 /* FPM */; \ - srl %x7, 1, %x7 /* IEU0 Group */; \ - inc %x8 /* IEU1 */; \ - STORE4 /* Store (optional) */; \ - faligndata %F6, %F8, %A6 /* FPA */; \ - fpadd32 %F6, %f6, %F6 /* FPA Group */; \ - srl %x8, 1, %x8 /* IEU0 */; \ - fcmpgt32 %f4, %F4, %x3 /* FPM */; \ - add %sum, %x7, %sum /* IEU0 Group */; \ - inc %x1 /* IEU1 */; \ - STORE5 /* Store (optional) */; \ - faligndata %F8, %F10, %A8 /* FPA */; \ - fpadd32 %F8, %f8, %F8 /* FPA Group */; \ - srl %x1, 1, %x1 /* IEU0 */; \ - fcmpgt32 %f6, %F6, %x4 /* FPM */; \ - add %sum, %x8, %sum /* IEU0 Group */; \ - inc %x2 /* IEU1 */; \ - STORE6 /* Store (optional) */; \ - faligndata %F10, %F12, %A10 /* FPA */; \ - fpadd32 %F10, %f10, %F10 /* FPA Group */; \ - srl %x2, 1, %x2 /* IEU0 */; \ - fcmpgt32 %f8, %F8, %x5 /* FPM */; \ - add %sum, %x1, %sum /* IEU0 Group */; \ - inc %x3 /* IEU1 */; \ - STORE7 /* Store (optional) */; \ - faligndata %F12, %F14, %A12 /* FPA */; \ - fpadd32 %F12, %f12, %F12 /* FPA Group */; \ - srl %x3, 1, %x3 /* IEU0 */; \ - fcmpgt32 %f10, %F10, %x6 /* FPM */; \ - add %sum, %x2, %sum /* IEU0 Group */; \ - inc %x4 /* IEU1 */; \ - STORE8 /* Store (optional) */; \ - fmovd %F14, %B14 /* FPA */; \ - fpadd32 %F14, %f14, %F14 /* FPA Group */; \ - srl %x4, 1, %x4 /* IEU0 */; \ - fcmpgt32 %f12, %F12, %x7 /* FPM */; \ - add %sum, %x3, %sum /* IEU0 Group */; \ - subcc %len, 64, %len /* IEU1 */; \ - BRANCH /* CTI */; \ - fcmpgt32 %f14, %F14, %x8 /* FPM Group */; - -#define END_THE_TRICK(f0,f2,f4,f6,f8,f10,f12,f14,FA,FB,S0,S1,S2,S3,T0,T1,U0,fz) \ - inc %x5 /* IEU0 Group */; \ - fpadd32 %f2, %f0, %S0 /* FPA */; \ - add %sum, %x4, %sum /* IEU1 */; \ - srl %x5, 1, %x5 /* IEU0 Group */; \ - fpadd32 %f6, %f4, %S1 /* FPA */; \ - inc %x6 /* IEU1 */; \ - fpadd32 %f10, %f8, %S2 /* FPA Group */; \ - add %sum, %x5, %sum /* IEU0 */; \ - fcmpgt32 %f0, %S0, %x1 /* FPM */; \ - fpadd32 %f14, %f12, %S3 /* FPA Group */; \ - srl %x6, 1, %x6 /* IEU0 */; \ - fcmpgt32 %f4, %S1, %x2 /* FPM */; \ - add %sum, %x6, %sum /* IEU0 Group */; \ - fzero %fz /* FPA */; \ - fcmpgt32 %f8, %S2, %x3 /* FPM */; \ - inc %x7 /* IEU0 Group */; \ - inc %x8 /* IEU1 */; \ - srl %x7, 1, %x7 /* IEU0 Group */; \ - inc %x1 /* IEU1 */; \ - fpadd32 %S0, %S1, %T0 /* FPA */; \ - fpadd32 %S2, %S3, %T1 /* FPA Group */; \ - add %sum, %x7, %sum /* IEU0 */; \ - fcmpgt32 %f12, %S3, %x4 /* FPM */; \ - srl %x8, 1, %x8 /* IEU0 Group */; \ - inc %x2 /* IEU1 */; \ - srl %x1, 1, %x1 /* IEU0 Group */; \ - add %sum, %x8, %sum /* IEU1 */; \ - add %sum, %x1, %sum /* IEU0 Group */; \ - fcmpgt32 %S0, %T0, %x5 /* FPM */; \ - srl %x2, 1, %x2 /* IEU0 Group */; \ - fcmpgt32 %S2, %T1, %x6 /* FPM */; \ - inc %x3 /* IEU0 Group */; \ - add %sum, %x2, %sum /* IEU1 */; \ - srl %x3, 1, %x3 /* IEU0 Group */; \ - inc %x4 /* IEU1 */; \ - fpadd32 %T0, %T1, %U0 /* FPA Group */; \ - add %sum, %x3, %sum /* IEU0 */; \ - fcmpgt32 %fz, %f2, %x7 /* FPM */; \ - srl %x4, 1, %x4 /* IEU0 Group */; \ - fcmpgt32 %fz, %f6, %x8 /* FPM */; \ - inc %x5 /* IEU0 Group */; \ - add %sum, %x4, %sum /* IEU1 */; \ - srl %x5, 1, %x5 /* IEU0 Group */; \ - fcmpgt32 %fz, %f10, %x1 /* FPM */; \ - inc %x6 /* IEU0 Group */; \ - add %sum, %x5, %sum /* IEU1 */; \ - fmovd %FA, %FB /* FPA Group */; \ - fcmpgt32 %fz, %f14, %x2 /* FPM */; \ - srl %x6, 1, %x6 /* IEU0 Group */; \ - ba,pt %xcc, ett /* CTI */; \ - inc %x7 /* IEU1 */; - -#define END_THE_TRICK1(f0,f2,f4,f6,f8,f10,f12,f14,FA,FB) \ - END_THE_TRICK(f0,f2,f4,f6,f8,f10,f12,f14,FA,FB,f48,f50,f52,f54,f56,f58,f60,f62) - -#define END_THE_TRICK2(S0,S1,S2,S3,T0,T1,U0,U1,V0,fz) \ - fpadd32 %U0, %U1, %V0 /* FPA Group */; \ - srl %x7, 1, %x7 /* IEU0 */; \ - add %sum, %x6, %sum /* IEU1 */; \ - std %V0, [%sp + STACKOFF] /* Store Group */; \ - inc %x8 /* IEU0 */; \ - sub %sum, %x7, %sum /* IEU1 */; \ - srl %x8, 1, %x8 /* IEU0 Group */; \ - fcmpgt32 %fz, %S1, %x3 /* FPM */; \ - inc %x1 /* IEU0 Group */; \ - fcmpgt32 %fz, %S3, %x4 /* FPM */; \ - srl %x1, 1, %x1 /* IEU0 Group */; \ - sub %sum, %x8, %sum /* IEU1 */; \ - ldx [%sp + STACKOFF], %x8 /* Load Group */; \ - inc %x2 /* IEU0 */; \ - sub %sum, %x1, %sum /* IEU1 */; \ - srl %x2, 1, %x2 /* IEU0 Group */; \ - fcmpgt32 %fz, %T1, %x5 /* FPM */; \ - inc %x3 /* IEU0 Group */; \ - fcmpgt32 %T0, %U0, %x6 /* FPM */; \ - srl %x3, 1, %x3 /* IEU0 Group */; \ - sub %sum, %x2, %sum /* IEU1 */; \ - inc %x4 /* IEU0 Group */; \ - sub %sum, %x3, %sum /* IEU1 */; \ - srl %x4, 1, %x4 /* IEU0 Group */; \ - fcmpgt32 %fz, %U1, %x7 /* FPM */; \ - inc %x5 /* IEU0 Group */; \ - fcmpgt32 %U0, %V0, %x1 /* FPM */; \ - srl %x5, 1, %x5 /* IEU0 Group */; \ - sub %sum, %x4, %sum /* IEU1 */; \ - sub %sum, %x5, %sum /* IEU0 Group */; \ - fcmpgt32 %fz, %V0, %x2 /* FPM */; \ - inc %x6 /* IEU0 Group */; \ - inc %x7 /* IEU1 */; \ - srl %x6, 1, %x6 /* IEU0 Group */; \ - inc %x1 /* IEU1 */; \ - srl %x7, 1, %x7 /* IEU0 Group */; \ - add %sum, %x6, %sum /* IEU1 */; \ - srl %x1, 1, %x1 /* IEU0 Group */; \ - sub %sum, %x7, %sum /* IEU1 */; \ - inc %x2 /* IEU0 Group */; \ - add %sum, %x1, %sum /* IEU1 */; \ - srl %x2, 1, %x2 /* IEU0 Group */; \ - sub %sum, %x2, %sum /* IEU0 Group */; \ - addcc %sum, %x8, %sum /* IEU1 Group */; \ - bcs,a,pn %xcc, 33f /* CTI */; \ - add %sum, 1, %sum /* IEU0 (Group) */; \ -33: /* That's it */; - - .text - .globl csum_partial_copy_vis - .align 32 -/* %asi should be either ASI_P or ASI_AIUS for csum_partial_copy resp. - * csum_partial_copy_from_user - * This assumes that !((%src^%dst)&3) && !((%src|%dst)&1) && %len >= 256 - */ -csum_partial_copy_vis: - andcc %dst, 7, %g0 /* IEU1 Group */ - be,pt %icc, 4f /* CTI */ - and %dst, 0x38, %o4 /* IEU0 */ - mov 1, %g5 /* IEU0 Group */ - andcc %dst, 2, %g0 /* IEU1 */ - be,pt %icc, 1f /* CTI */ - and %dst, 4, %g7 /* IEU0 Group */ - lduha [%src] %asi, %g2 /* Load */ - sub %len, 2, %len /* IEU0 Group */ - add %dst, 2, %dst /* IEU1 */ - andcc %dst, 4, %g7 /* IEU1 Group */ - sll %g5, 16, %g5 /* IEU0 */ - sth %g2, [%dst - 2] /* Store Group */ - sll %g2, 16, %g2 /* IEU0 */ - add %src, 2, %src /* IEU1 */ - addcc %g2, %sum, %sum /* IEU1 Group */ - bcs,a,pn %icc, 1f /* CTI */ - add %sum, %g5, %sum /* IEU0 */ -1: lduwa [%src] %asi, %g2 /* Load */ - brz,a,pn %g7, 4f /* CTI+IEU1 Group */ - and %dst, 0x38, %o4 /* IEU0 */ - add %dst, 4, %dst /* IEU0 Group */ - sub %len, 4, %len /* IEU1 */ - addcc %g2, %sum, %sum /* IEU1 Group */ - bcs,a,pn %icc, 1f /* CTI */ - add %sum, 1, %sum /* IEU0 */ -1: and %dst, 0x38, %o4 /* IEU0 Group */ - stw %g2, [%dst - 4] /* Store */ - add %src, 4, %src /* IEU1 */ -4: -#ifdef __KERNEL__ - VISEntry -#endif - mov %src, %g7 /* IEU1 Group */ - fzero %f48 /* FPA */ - alignaddr %src, %g0, %src /* Single Group */ - subcc %g7, %src, %g7 /* IEU1 Group */ - be,pt %xcc, 1f /* CTI */ - mov 0x40, %g1 /* IEU0 */ - lduwa [%src] %asi, %g2 /* Load Group */ - subcc %sum, %g2, %sum /* IEU1 Group+load stall*/ - bcs,a,pn %icc, 1f /* CTI */ - sub %sum, 1, %sum /* IEU0 */ -1: srl %sum, 0, %sum /* IEU0 Group */ - clr %g5 /* IEU1 */ - brz,pn %o4, 3f /* CTI+IEU1 Group */ - sub %g1, %o4, %g1 /* IEU0 */ - ldda [%src] %asi, %f0 /* Load */ - clr %o4 /* IEU0 Group */ - andcc %dst, 8, %g0 /* IEU1 */ - be,pn %icc, 1f /* CTI */ - ldda [%src + 8] %asi, %f2 /* Load Group */ - add %src, 8, %src /* IEU0 */ - sub %len, 8, %len /* IEU1 */ - fpadd32 %f0, %f48, %f50 /* FPA */ - addcc %dst, 8, %dst /* IEU1 Group */ - faligndata %f0, %f2, %f16 /* FPA */ - fcmpgt32 %f48, %f50, %o4 /* FPM Group */ - fmovd %f2, %f0 /* FPA Group */ - ldda [%src + 8] %asi, %f2 /* Load */ - std %f16, [%dst - 8] /* Store */ - fmovd %f50, %f48 /* FPA */ -1: andcc %g1, 0x10, %g0 /* IEU1 Group */ - be,pn %icc, 1f /* CTI */ - and %g1, 0x20, %g1 /* IEU0 */ - fpadd32 %f0, %f48, %f50 /* FPA */ - ldda [%src + 16] %asi, %f4 /* Load Group */ - add %src, 16, %src /* IEU0 */ - add %dst, 16, %dst /* IEU1 */ - faligndata %f0, %f2, %f16 /* FPA */ - fcmpgt32 %f48, %f50, %g5 /* FPM Group */ - sub %len, 16, %len /* IEU0 */ - inc %o4 /* IEU1 */ - std %f16, [%dst - 16] /* Store Group */ - fpadd32 %f2, %f50, %f48 /* FPA */ - srl %o4, 1, %o5 /* IEU0 */ - faligndata %f2, %f4, %f18 /* FPA Group */ - std %f18, [%dst - 8] /* Store */ - fcmpgt32 %f50, %f48, %o4 /* FPM Group */ - add %o5, %sum, %sum /* IEU0 */ - ldda [%src + 8] %asi, %f2 /* Load */ - fmovd %f4, %f0 /* FPA */ -1: brz,a,pn %g1, 4f /* CTI+IEU1 Group */ - rd %asi, %g2 /* LSU Group + 4 bubbles*/ - inc %g5 /* IEU0 */ - fpadd32 %f0, %f48, %f50 /* FPA */ - ldda [%src + 16] %asi, %f4 /* Load Group */ - srl %g5, 1, %g5 /* IEU0 */ - add %dst, 32, %dst /* IEU1 */ - faligndata %f0, %f2, %f16 /* FPA */ - fcmpgt32 %f48, %f50, %o5 /* FPM Group */ - inc %o4 /* IEU0 */ - ldda [%src + 24] %asi, %f6 /* Load */ - srl %o4, 1, %o4 /* IEU0 Group */ - add %g5, %sum, %sum /* IEU1 */ - ldda [%src + 32] %asi, %f8 /* Load */ - fpadd32 %f2, %f50, %f48 /* FPA */ - faligndata %f2, %f4, %f18 /* FPA Group */ - sub %len, 32, %len /* IEU0 */ - std %f16, [%dst - 32] /* Store */ - fcmpgt32 %f50, %f48, %g3 /* FPM Group */ - inc %o5 /* IEU0 */ - add %o4, %sum, %sum /* IEU1 */ - fpadd32 %f4, %f48, %f50 /* FPA */ - faligndata %f4, %f6, %f20 /* FPA Group */ - srl %o5, 1, %o5 /* IEU0 */ - fcmpgt32 %f48, %f50, %g5 /* FPM Group */ - add %o5, %sum, %sum /* IEU0 */ - std %f18, [%dst - 24] /* Store */ - fpadd32 %f6, %f50, %f48 /* FPA */ - inc %g3 /* IEU0 Group */ - std %f20, [%dst - 16] /* Store */ - add %src, 32, %src /* IEU1 */ - faligndata %f6, %f8, %f22 /* FPA */ - fcmpgt32 %f50, %f48, %o4 /* FPM Group */ - srl %g3, 1, %g3 /* IEU0 */ - std %f22, [%dst - 8] /* Store */ - add %g3, %sum, %sum /* IEU0 Group */ -3: rd %asi, %g2 /* LSU Group + 4 bubbles*/ -#ifdef __KERNEL__ -4: sethi %hi(vis0s), %g7 /* IEU0 Group */ - or %g2, ASI_BLK_OR, %g2 /* IEU1 */ -#else -4: rd %pc, %g7 /* LSU Group + 4 bubbles*/ -#endif - inc %g5 /* IEU0 Group */ - and %src, 0x38, %g3 /* IEU1 */ - membar #StoreLoad /* LSU Group */ - srl %g5, 1, %g5 /* IEU0 */ - inc %o4 /* IEU1 */ - sll %g3, 8, %g3 /* IEU0 Group */ - sub %len, 0xc0, %len /* IEU1 */ - addcc %g5, %sum, %sum /* IEU1 Group */ - srl %o4, 1, %o4 /* IEU0 */ - add %g7, %g3, %g7 /* IEU0 Group */ - add %o4, %sum, %sum /* IEU1 */ -#ifdef __KERNEL__ - jmpl %g7 + %lo(vis0s), %g0 /* CTI+IEU1 Group */ -#else - jmpl %g7 + (vis0s - 4b), %g0 /* CTI+IEU1 Group */ -#endif - fzero %f32 /* FPA */ - - .align 2048 -vis0s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - add %src, 128, %src /* IEU0 Group */ - ldda [%src-128] %asi, %f0 /* Load Group */ - ldda [%src-64] %asi, %f16 /* Load Group */ - fmovd %f48, %f62 /* FPA Group f0 available*/ - faligndata %f0, %f2, %f48 /* FPA Group f2 available*/ - fcmpgt32 %f32, %f2, %x1 /* FPM Group f4 available*/ - fpadd32 %f0, %f62, %f0 /* FPA */ - fcmpgt32 %f32, %f4, %x2 /* FPM Group f6 available*/ - faligndata %f2, %f4, %f50 /* FPA */ - fcmpgt32 %f62, %f0, %x3 /* FPM Group f8 available*/ - faligndata %f4, %f6, %f52 /* FPA */ - fcmpgt32 %f32, %f6, %x4 /* FPM Group f10 available*/ - inc %x1 /* IEU0 */ - faligndata %f6, %f8, %f54 /* FPA */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group f12 available*/ - srl %x1, 1, %x1 /* IEU0 */ - inc %x2 /* IEU1 */ - faligndata %f8, %f10, %f56 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group f14 available*/ - srl %x2, 1, %x2 /* IEU0 */ - add %sum, %x1, %sum /* IEU1 */ - faligndata %f10, %f12, %f58 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - inc %x3 /* IEU0 */ - add %sum, %x2, %sum /* IEU1 */ - faligndata %f12, %f14, %f60 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - srl %x3, 1, %x3 /* IEU0 */ - inc %x4 /* IEU1 */ - fmovd %f14, %f62 /* FPA */ - srl %x4, 1, %x4 /* IEU0 Group */ - add %sum, %x3, %sum /* IEU1 */ -vis0: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f48,f50,f52,f54,f56,f58,f60,f62,f62, - ,LDBLK(f32), STBLK,,,,,,,, - ,bcs,pn %icc, vis0e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f48,f50,f52,f54,f56,f58,f60,f62,f62, - ,LDBLK(f0), STBLK,,,,,,,, - ,bcs,pn %icc, vis0e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f48,f50,f52,f54,f56,f58,f60,f62,f62, - ,LDBLK(f16), STBLK,,,,,,,, - ,bcc,pt %icc, vis0) -vis0e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f48,f50,f52,f54,f56,f58,f60,f62,f32, - ,SYNC, STBLK,ST(f48,64),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40),ST(f60,48), - ,add %dst, 56, %dst; add %len, 192 - 8*8, %len; ba,pt %icc, e2) -vis0e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f48,f50,f52,f54,f56,f58,f60,f62,f0, - ,SYNC, STBLK,ST(f48,64),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40),ST(f60,48), - ,add %dst, 56, %dst; add %len, 192 - 8*8, %len; ba,pt %icc, e3) -vis0e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f48,f50,f52,f54,f56,f58,f60,f62,f16, - ,SYNC, STBLK,ST(f48,64),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40),ST(f60,48), - ,add %dst, 56, %dst; add %len, 192 - 8*8, %len; ba,pt %icc, e1) - .align 2048 -vis1s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - add %src, 128 - 8, %src /* IEU0 Group */ - ldda [%src-128] %asi, %f0 /* Load Group */ - ldda [%src-64] %asi, %f16 /* Load Group */ - fmovd %f0, %f58 /* FPA Group */ - fmovd %f48, %f0 /* FPA Group */ - fcmpgt32 %f32, %f2, %x2 /* FPM Group */ - faligndata %f2, %f4, %f48 /* FPA */ - fcmpgt32 %f32, %f4, %x3 /* FPM Group */ - faligndata %f4, %f6, %f50 /* FPA */ - fcmpgt32 %f32, %f6, %x4 /* FPM Group */ - faligndata %f6, %f8, %f52 /* FPA */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group */ - inc %x2 /* IEU1 */ - faligndata %f8, %f10, %f54 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - srl %x2, 1, %x2 /* IEU0 */ - faligndata %f10, %f12, %f56 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - inc %x3 /* IEU0 */ - add %sum, %x2, %sum /* IEU1 */ - faligndata %f12, %f14, %f58 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - srl %x3, 1, %x3 /* IEU0 */ - inc %x4 /* IEU1 */ - fmovd %f14, %f60 /* FPA */ - srl %x4, 1, %x4 /* IEU0 Group */ - add %sum, %x3, %sum /* IEU1 */ -vis1: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f62,f48,f50,f52,f54,f56,f58,f60,f60, - ,LDBLK(f32), ,STBLK,,,,,,, - ,bcs,pn %icc, vis1e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f62,f48,f50,f52,f54,f56,f58,f60,f60, - ,LDBLK(f0), ,STBLK,,,,,,, - ,bcs,pn %icc, vis1e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f62,f48,f50,f52,f54,f56,f58,f60,f60, - ,LDBLK(f16), ,STBLK,,,,,,, - ,bcc,pt %icc, vis1) -vis1e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f62,f48,f50,f52,f54,f56,f58,f60,f32, - ,SYNC, ,STBLK,ST(f48,0),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40), - ,add %dst, 48, %dst; add %len, 192 - 7*8, %len; ba,pt %icc, e2) -vis1e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f62,f48,f50,f52,f54,f56,f58,f60,f0, - ,SYNC, ,STBLK,ST(f48,0),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40), - ,add %dst, 48, %dst; add %len, 192 - 7*8, %len; ba,pt %icc, e3) -vis1e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f62,f48,f50,f52,f54,f56,f58,f60,f16, - ,SYNC, ,STBLK,ST(f48,0),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40), - ,add %dst, 48, %dst; add %len, 192 - 7*8, %len; ba,pt %icc, e1) - .align 2048 -vis2s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - add %src, 128 - 16, %src /* IEU0 Group */ - ldda [%src-128] %asi, %f0 /* Load Group */ - ldda [%src-64] %asi, %f16 /* Load Group */ - fmovd %f0, %f56 /* FPA Group */ - fmovd %f48, %f0 /* FPA Group */ - sub %dst, 64, %dst /* IEU0 */ - fpsub32 %f2, %f2, %f2 /* FPA Group */ - fcmpgt32 %f32, %f4, %x3 /* FPM Group */ - faligndata %f4, %f6, %f48 /* FPA */ - fcmpgt32 %f32, %f6, %x4 /* FPM Group */ - faligndata %f6, %f8, %f50 /* FPA */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group */ - faligndata %f8, %f10, %f52 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - faligndata %f10, %f12, %f54 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - inc %x3 /* IEU0 */ - faligndata %f12, %f14, %f56 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - srl %x3, 1, %x3 /* IEU0 */ - inc %x4 /* IEU1 */ - fmovd %f14, %f58 /* FPA */ - srl %x4, 1, %x4 /* IEU0 Group */ - add %sum, %x3, %sum /* IEU1 */ -vis2: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f60,f62,f48,f50,f52,f54,f56,f58,f58, - ,LDBLK(f32), ,,STBLK,,,,,, - ,bcs,pn %icc, vis2e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f60,f62,f48,f50,f52,f54,f56,f58,f58, - ,LDBLK(f0), ,,STBLK,,,,,, - ,bcs,pn %icc, vis2e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f60,f62,f48,f50,f52,f54,f56,f58,f58, - ,LDBLK(f16), ,,STBLK,,,,,, - ,bcc,pt %icc, vis2) -vis2e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f60,f62,f48,f50,f52,f54,f56,f58,f32, - ,SYNC, ,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88),ST(f56,96), - ,add %dst, 104, %dst; add %len, 192 - 6*8, %len; ba,pt %icc, e2) -vis2e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f60,f62,f48,f50,f52,f54,f56,f58,f0, - ,SYNC, ,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88),ST(f56,96), - ,add %dst, 104, %dst; add %len, 192 - 6*8, %len; ba,pt %icc, e3) -vis2e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f60,f62,f48,f50,f52,f54,f56,f58,f16, - ,SYNC, ,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88),ST(f56,96), - ,add %dst, 104, %dst; add %len, 192 - 6*8, %len; ba,pt %icc, e1) - .align 2048 -vis3s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - add %src, 128 - 24, %src /* IEU0 Group */ - ldda [%src-128] %asi, %f0 /* Load Group */ - ldda [%src-64] %asi, %f16 /* Load Group */ - fmovd %f0, %f54 /* FPA Group */ - fmovd %f48, %f0 /* FPA Group */ - sub %dst, 64, %dst /* IEU0 */ - fpsub32 %f2, %f2, %f2 /* FPA Group */ - fpsub32 %f4, %f4, %f4 /* FPA Group */ - fcmpgt32 %f32, %f6, %x4 /* FPM Group */ - faligndata %f6, %f8, %f48 /* FPA */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group */ - faligndata %f8, %f10, %f50 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - faligndata %f10, %f12, %f52 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - faligndata %f12, %f14, %f54 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - fmovd %f14, %f56 /* FPA */ - inc %x4 /* IEU0 */ - srl %x4, 1, %x4 /* IEU0 Group */ -vis3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f58,f60,f62,f48,f50,f52,f54,f56,f56, - ,LDBLK(f32), ,,,STBLK,,,,, - ,bcs,pn %icc, vis3e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f58,f60,f62,f48,f50,f52,f54,f56,f56, - ,LDBLK(f0), ,,,STBLK,,,,, - ,bcs,pn %icc, vis3e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f58,f60,f62,f48,f50,f52,f54,f56,f56, - ,LDBLK(f16), ,,,STBLK,,,,, - ,bcc,pt %icc, vis3) -vis3e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f58,f60,f62,f48,f50,f52,f54,f56,f32, - ,SYNC, ,,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88), - ,add %dst, 96, %dst; add %len, 192 - 5*8, %len; ba,pt %icc, e2) -vis3e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f58,f60,f62,f48,f50,f52,f54,f56,f0, - ,SYNC, ,,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88), - ,add %dst, 96, %dst; add %len, 192 - 5*8, %len; ba,pt %icc, e3) -vis3e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f58,f60,f62,f48,f50,f52,f54,f56,f16, - ,SYNC, ,,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88), - ,add %dst, 96, %dst; add %len, 192 - 5*8, %len; ba,pt %icc, e1) - .align 2048 -vis4s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - add %src, 128 - 32, %src /* IEU0 Group */ - ldda [%src-128] %asi, %f0 /* Load Group */ - ldda [%src-64] %asi, %f16 /* Load Group */ - fmovd %f0, %f52 /* FPA Group */ - fmovd %f48, %f0 /* FPA Group */ - sub %dst, 64, %dst /* IEU0 */ - fpsub32 %f2, %f2, %f2 /* FPA Group */ - fpsub32 %f4, %f4, %f4 /* FPA Group */ - fpsub32 %f6, %f6, %f6 /* FPA Group */ - clr %x4 /* IEU0 */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group */ - faligndata %f8, %f10, %f48 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - faligndata %f10, %f12, %f50 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - faligndata %f12, %f14, %f52 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - fmovd %f14, %f54 /* FPA */ -vis4: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f56,f58,f60,f62,f48,f50,f52,f54,f54, - ,LDBLK(f32), ,,,,STBLK,,,, - ,bcs,pn %icc, vis4e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f56,f58,f60,f62,f48,f50,f52,f54,f54, - ,LDBLK(f0), ,,,,STBLK,,,, - ,bcs,pn %icc, vis4e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f56,f58,f60,f62,f48,f50,f52,f54,f54, - ,LDBLK(f16), ,,,,STBLK,,,, - ,bcc,pt %icc, vis4) -vis4e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f56,f58,f60,f62,f48,f50,f52,f54,f32, - ,SYNC, ,,,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80), - ,add %dst, 88, %dst; add %len, 192 - 4*8, %len; ba,pt %icc, e2) -vis4e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f56,f58,f60,f62,f48,f50,f52,f54,f0, - ,SYNC, ,,,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80), - ,add %dst, 88, %dst; add %len, 192 - 4*8, %len; ba,pt %icc, e3) -vis4e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f56,f58,f60,f62,f48,f50,f52,f54,f16, - ,SYNC, ,,,,STBLK,ST(f48,64),ST(f50,72),ST(f52,80), - ,add %dst, 88, %dst; add %len, 192 - 4*8, %len; ba,pt %icc, e1) - .align 2048 -vis5s: add %src, 128 - 40, %src /* IEU0 Group */ - ldda [%src-88] %asi, %f10 /* Load Group */ - ldda [%src-80] %asi, %f12 /* Load Group */ - ldda [%src-72] %asi, %f14 /* Load Group */ - wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - ldda [%src-64] %asi, %f16 /* Load Group */ - fmovd %f48, %f0 /* FPA Group */ - fmuld %f32, %f32, %f2 /* FPM */ - clr %x4 /* IEU0 */ - faddd %f32, %f32, %f4 /* FPA Group */ - fmuld %f32, %f32, %f6 /* FPM */ - clr %x5 /* IEU0 */ - faddd %f32, %f32, %f8 /* FPA Group */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - sub %dst, 64, %dst /* IEU0 */ - faligndata %f10, %f12, %f48 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - faligndata %f12, %f14, %f50 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - fmovd %f14, %f52 /* FPA */ -vis5: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f54,f56,f58,f60,f62,f48,f50,f52,f52, - ,LDBLK(f32), ,,,,,STBLK,,, - ,bcs,pn %icc, vis5e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f54,f56,f58,f60,f62,f48,f50,f52,f52, - ,LDBLK(f0), ,,,,,STBLK,,, - ,bcs,pn %icc, vis5e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f54,f56,f58,f60,f62,f48,f50,f52,f52, - ,LDBLK(f16), ,,,,,STBLK,,, - ,bcc,pt %icc, vis5) -vis5e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f54,f56,f58,f60,f62,f48,f50,f52,f32, - ,SYNC, ,,,,,STBLK,ST(f48,64),ST(f50,72), - ,add %dst, 80, %dst; add %len, 192 - 3*8, %len; ba,pt %icc, e2) -vis5e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f54,f56,f58,f60,f62,f48,f50,f52,f0, - ,SYNC, ,,,,,STBLK,ST(f48,64),ST(f50,72), - ,add %dst, 80, %dst; add %len, 192 - 3*8, %len; ba,pt %icc, e3) -vis5e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f54,f56,f58,f60,f62,f48,f50,f52,f16, - ,SYNC, ,,,,,STBLK,ST(f48,64),ST(f50,72), - ,add %dst, 80, %dst; add %len, 192 - 3*8, %len; ba,pt %icc, e1) - .align 2048 -vis6s: add %src, 128 - 48, %src /* IEU0 Group */ - ldda [%src-80] %asi, %f12 /* Load Group */ - ldda [%src-72] %asi, %f14 /* Load Group */ - wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - ldda [%src-64] %asi, %f16 /* Load Group */ - fmovd %f48, %f0 /* FPA Group */ - fmuld %f32, %f32, %f2 /* FPM */ - clr %x4 /* IEU0 */ - faddd %f32, %f32, %f4 /* FPA Group */ - fmuld %f32, %f32, %f6 /* FPM */ - clr %x5 /* IEU0 */ - faddd %f32, %f32, %f8 /* FPA Group */ - fmuld %f32, %f32, %f10 /* FPM */ - clr %x6 /* IEU0 */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - sub %dst, 64, %dst /* IEU0 */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - faligndata %f12, %f14, %f48 /* FPA */ - fmovd %f14, %f50 /* FPA Group */ -vis6: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f52,f54,f56,f58,f60,f62,f48,f50,f50, - ,LDBLK(f32), ,,,,,,STBLK,, - ,bcs,pn %icc, vis6e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f52,f54,f56,f58,f60,f62,f48,f50,f50, - ,LDBLK(f0), ,,,,,,STBLK,, - ,bcs,pn %icc, vis6e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f52,f54,f56,f58,f60,f62,f48,f50,f50, - ,LDBLK(f16), ,,,,,,STBLK,, - ,bcc,pt %icc, vis6) -vis6e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f52,f54,f56,f58,f60,f62,f48,f50,f32, - ,SYNC, ,,,,,,STBLK,ST(f48,64), - ,add %dst, 72, %dst; add %len, 192 - 2*8, %len; ba,pt %icc, e2) -vis6e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f52,f54,f56,f58,f60,f62,f48,f50,f0, - ,SYNC, ,,,,,,STBLK,ST(f48,64), - ,add %dst, 72, %dst; add %len, 192 - 2*8, %len; ba,pt %icc, e3) -vis6e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f52,f54,f56,f58,f60,f62,f48,f50,f16, - ,SYNC, ,,,,,,STBLK,ST(f48,64), - ,add %dst, 72, %dst; add %len, 192 - 2*8, %len; ba,pt %icc, e1) - .align 2048 -vis7s: add %src, 128 - 56, %src /* IEU0 Group */ - ldda [%src-72] %asi, %f14 /* Load Group */ - wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - ldda [%src-64] %asi, %f16 /* Load Group */ - fmovd %f48, %f0 /* FPA Group */ - fmuld %f32, %f32, %f2 /* FPM */ - clr %x4 /* IEU0 */ - faddd %f32, %f32, %f4 /* FPA Group */ - fmuld %f32, %f32, %f6 /* FPM */ - clr %x5 /* IEU0 */ - faddd %f32, %f32, %f8 /* FPA Group */ - fmuld %f32, %f32, %f10 /* FPM */ - clr %x6 /* IEU0 */ - faddd %f32, %f32, %f12 /* FPA Group */ - clr %x7 /* IEU0 */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - sub %dst, 64, %dst /* IEU0 */ - fmovd %f14, %f48 /* FPA */ -vis7: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f50,f52,f54,f56,f58,f60,f62,f48,f48, - ,LDBLK(f32), ,,,,,,,STBLK, - ,bcs,pn %icc, vis7e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f50,f52,f54,f56,f58,f60,f62,f48,f48, - ,LDBLK(f0), ,,,,,,,STBLK, - ,bcs,pn %icc, vis7e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f50,f52,f54,f56,f58,f60,f62,f48,f48, - ,LDBLK(f16), ,,,,,,,STBLK, - ,bcc,pt %icc, vis7) -vis7e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f50,f52,f54,f56,f58,f60,f62,f48,f32, - ,SYNC, ,,,,,,,STBLK, - ,add %dst, 64, %dst; add %len, 192 - 1*8, %len; ba,pt %icc, e2) -vis7e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f50,f52,f54,f56,f58,f60,f62,f48,f0, - ,SYNC, ,,,,,,,STBLK, - ,add %dst, 64, %dst; add %len, 192 - 1*8, %len; ba,pt %icc, e3) -vis7e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f50,f52,f54,f56,f58,f60,f62,f48,f16, - ,SYNC, ,,,,,,,STBLK, - ,add %dst, 64, %dst; add %len, 192 - 1*8, %len; ba,pt %icc, e1) -e1: END_THE_TRICK1( f0,f2,f4,f6,f8,f10,f12,f14,f16,f6) -e2: END_THE_TRICK1( f16,f18,f20,f22,f24,f26,f28,f30,f32,f6) -e3: END_THE_TRICK1( f32,f34,f36,f38,f40,f42,f44,f46,f0,f6) -ett: rd %asi, %x4 /* LSU Group+4bubbles */ - rd %gsr, %x3 /* LSU Group+4bubbles */ -#ifdef __KERNEL__ - srl %x4, 3, %x5 /* IEU0 Group */ - xor %x4, ASI_BLK_XOR1, %x4 /* IEU1 */ - wr %x4, %x5, %asi /* LSU Group+4bubbles */ -#else - wr %x4, ASI_BLK_XOR, %asi /* LSU Group+4bubbles */ -#endif - andcc %x3, 7, %x3 /* IEU1 Group */ - add %dst, 8, %dst /* IEU0 */ - bne,pn %icc, 1f /* CTI */ - fzero %f10 /* FPA */ - brz,a,pn %len, 2f /* CTI+IEU1 Group */ - std %f6, [%dst - 8] /* Store */ -1: cmp %len, 8 /* IEU1 */ - blu,pn %icc, 3f /* CTI */ - sub %src, 64, %src /* IEU0 Group */ -1: ldda [%src] %asi, %f2 /* Load Group */ - fpadd32 %f10, %f2, %f12 /* FPA Group+load stall*/ - add %src, 8, %src /* IEU0 */ - add %dst, 8, %dst /* IEU1 */ - faligndata %f6, %f2, %f14 /* FPA Group */ - fcmpgt32 %f10, %f12, %x5 /* FPM Group */ - std %f14, [%dst - 16] /* Store */ - fmovd %f2, %f6 /* FPA */ - fmovd %f12, %f10 /* FPA Group */ - sub %len, 8, %len /* IEU1 */ - fzero %f16 /* FPA Group - FPU nop */ - fzero %f18 /* FPA Group - FPU nop */ - inc %x5 /* IEU0 */ - srl %x5, 1, %x5 /* IEU0 Group (regdep) */ - cmp %len, 8 /* IEU1 */ - bgeu,pt %icc, 1b /* CTI */ - add %x5, %sum, %sum /* IEU0 Group */ -3: brz,a,pt %x3, 2f /* CTI+IEU1 */ - std %f6, [%dst - 8] /* Store Group */ - st %f7, [%dst - 8] /* Store Group */ - sub %dst, 4, %dst /* IEU0 */ - add %len, 4, %len /* IEU1 */ -2: -#ifdef __KERNEL__ - sub %sp, 8, %sp /* IEU0 Group */ -#endif - END_THE_TRICK2( f48,f50,f52,f54,f56,f58,f60,f10,f12,f62) - membar #Sync /* LSU Group */ -#ifdef __KERNEL__ - VISExit - add %sp, 8, %sp /* IEU0 Group */ -#endif -23: brnz,pn %len, 26f /* CTI+IEU1 Group */ -24: sllx %sum, 32, %g1 /* IEU0 */ -25: addcc %sum, %g1, %src /* IEU1 Group */ - srlx %src, 32, %src /* IEU0 Group (regdep) */ - bcs,a,pn %xcc, 1f /* CTI */ - add %src, 1, %src /* IEU1 */ -#ifndef __KERNEL__ -1: retl /* CTI Group brk forced*/ - srl %src, 0, %src /* IEU0 */ -#else -1: retl /* CTI Group brk forced*/ - ldx [%g6 + TI_TASK], %g4 /* Load */ -#endif -26: andcc %len, 8, %g0 /* IEU1 Group */ - be,pn %icc, 1f /* CTI */ - lduwa [%src] %asi, %o4 /* Load */ - lduwa [%src+4] %asi, %g2 /* Load Group */ - add %src, 8, %src /* IEU0 */ - add %dst, 8, %dst /* IEU1 */ - sllx %o4, 32, %g5 /* IEU0 Group */ - stw %o4, [%dst - 8] /* Store */ - or %g5, %g2, %g5 /* IEU0 Group */ - stw %g2, [%dst - 4] /* Store */ - addcc %g5, %sum, %sum /* IEU1 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %sum, 1, %sum /* IEU0 */ -1: andcc %len, 4, %g0 /* IEU1 Group */ - be,a,pn %icc, 1f /* CTI */ - clr %g2 /* IEU0 */ - lduwa [%src] %asi, %g7 /* Load */ - add %src, 4, %src /* IEU0 Group */ - add %dst, 4, %dst /* IEU1 */ - sllx %g7, 32, %g2 /* IEU0 Group */ - stw %g7, [%dst - 4] /* Store */ -1: andcc %len, 2, %g0 /* IEU1 */ - be,a,pn %icc, 1f /* CTI */ - clr %g3 /* IEU0 Group */ - lduha [%src] %asi, %g7 /* Load */ - add %src, 2, %src /* IEU1 */ - add %dst, 2, %dst /* IEU0 Group */ - sll %g7, 16, %g3 /* IEU0 Group */ - sth %g7, [%dst - 2] /* Store */ -1: andcc %len, 1, %g0 /* IEU1 */ - be,a,pn %icc, 1f /* CTI */ - clr %o5 /* IEU0 Group */ - lduba [%src] %asi, %g7 /* Load */ - sll %g7, 8, %o5 /* IEU0 Group */ - stb %g7, [%dst] /* Store */ -1: or %g2, %g3, %g3 /* IEU1 */ - or %o5, %g3, %g3 /* IEU0 Group (regdep) */ - addcc %g3, %sum, %sum /* IEU1 Group (regdep) */ - bcs,a,pn %xcc, 1f /* CTI */ - add %sum, 1, %sum /* IEU0 */ -1: ba,pt %xcc, 25b /* CTI Group */ - sllx %sum, 32, %g1 /* IEU0 */ - -#ifdef __KERNEL__ -end: - - .section __ex_table - .align 4 - .word csum_partial_copy_vis, 0, end, cpc_handler -#endif diff --git a/arch/sparc64/lib/VIScsumcopyusr.S b/arch/sparc64/lib/VIScsumcopyusr.S deleted file mode 100644 index fc27b7fa4117e..0000000000000 --- a/arch/sparc64/lib/VIScsumcopyusr.S +++ /dev/null @@ -1,916 +0,0 @@ -/* $Id: VIScsumcopyusr.S,v 1.2 2000/02/20 23:21:40 davem Exp $ - * VIScsumcopyusr.S: High bandwidth IP checksumming with simultaneous - * copying utilizing the UltraSparc Visual Instruction Set. - * - * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz) - * Copyright (C) 2000 David S. Miller (davem@redhat.com) - * - * Based on older sparc32/sparc64 checksum.S, which is: - * - * Copyright(C) 1995 Linus Torvalds - * Copyright(C) 1995 Miguel de Icaza - * Copyright(C) 1996,1997 David S. Miller - * derived from: - * Linux/Alpha checksum c-code - * Linux/ix86 inline checksum assembly - * RFC1071 Computing the Internet Checksum (esp. Jacobsons m68k code) - * David Mosberger-Tang for optimized reference c-code - * BSD4.4 portable checksum routine - */ - -#ifdef __sparc_v9__ -#define STACKOFF 0x7ff+128 -#else -#define STACKOFF 64 -#endif - -#ifdef __KERNEL__ -#include <asm/head.h> -#include <asm/asi.h> -#include <asm/page.h> -#include <asm/visasm.h> -#include <asm/thread_info.h> -#define ASI_BLK_XOR 0 -#define ASI_BLK_XOR1 (ASI_BLK_P ^ (ASI_BLK_P >> 3) ^ ASI_P) -#define ASI_BLK_OR (ASI_BLK_P & ~ASI_P) -#else -#define ASI_P 0x80 -#define ASI_BLK_P 0xf0 -#define FRPS_FEF 0x04 -#define FPRS_DU 0x02 -#define FPRS_DL 0x01 -#define ASI_BLK_XOR (ASI_BLK_P ^ ASI_P) -#endif - -#define src o0 -#define dst o1 -#define len o2 -#define sum o3 -#define x1 g1 -#define x2 g2 -#define x3 o4 -#define x4 g4 -#define x5 g5 -#define x6 g7 -#define x7 g3 -#define x8 o5 - -/* Dobrou noc, SunSoft engineers. Spete sladce. - * This has a couple of tricks in and those - * tricks are UltraLinux trade secrets :)) - * Once AGAIN, the SunSoft engineers are caught - * asleep at the keyboard :)). - * The main loop does about 20 superscalar cycles - * per 64bytes checksummed/copied. - */ - -#define LDBLK(O0) \ - ldda [%src] ASI_BLK_P, %O0 /* Load Group */ - -#define STBLK \ - stda %f48, [%dst] %asi /* Store */ - -#ifdef __KERNEL__ -#define STBLK_XORASI(tmpreg1,tmpreg2) \ - stda %f48, [%dst] %asi /* Store */; \ - rd %asi, %tmpreg1; \ - srl %tmpreg1, 3, %tmpreg2; \ - xor %tmpreg1, ASI_BLK_XOR1, %tmpreg1; \ - wr %tmpreg1, %tmpreg2, %asi; -#else -#define STBLK_XORASI(tmpreg1,tmpreg2) \ - stda %f48, [%dst] %asi /* Store */; \ - rd %asi, %tmpreg1; \ - wr %tmpreg1, ASI_BLK_XOR, %asi; -#endif - -#define ST(fx,off) \ - stda %fx, [%dst + off] %asi /* Store */ - -#define SYNC \ - membar #Sync - - -#define DO_THE_TRICK(f0,f2,f4,f6,f8,f10,f12,f14,F0,F2,F4,F6,F8,F10,F12,F14,DUMMY1,A0,A2,A4,A6,A8,A10,A12,A14,B14,DUMMY2,LOAD,STORE1,STORE2,STORE3,STORE4,STORE5,STORE6,STORE7,STORE8,DUMMY3,BRANCH...) \ - LOAD /* Load (Group) */; \ - faligndata %A14, %F0, %A14 /* FPA Group */; \ - inc %x5 /* IEU0 */; \ - STORE1 /* Store (optional) */; \ - faligndata %F0, %F2, %A0 /* FPA Group */; \ - srl %x5, 1, %x5 /* IEU0 */; \ - add %sum, %x4, %sum /* IEU1 */; \ - fpadd32 %F0, %f0, %F0 /* FPA Group */; \ - inc %x6 /* IEU0 */; \ - STORE2 /* Store (optional) */; \ - faligndata %F2, %F4, %A2 /* FPA Group */; \ - srl %x6, 1, %x6 /* IEU0 */; \ - add %sum, %x5, %sum /* IEU1 */; \ - fpadd32 %F2, %f2, %F2 /* FPA Group */; \ - add %src, 64, %src /* IEU0 */; \ - fcmpgt32 %f0, %F0, %x1 /* FPM */; \ - add %dst, 64, %dst /* IEU1 Group */; \ - inc %x7 /* IEU0 */; \ - STORE3 /* Store (optional) */; \ - faligndata %F4, %F6, %A4 /* FPA */; \ - fpadd32 %F4, %f4, %F4 /* FPA Group */; \ - add %sum, %x6, %sum /* IEU1 */; \ - fcmpgt32 %f2, %F2, %x2 /* FPM */; \ - srl %x7, 1, %x7 /* IEU0 Group */; \ - inc %x8 /* IEU1 */; \ - STORE4 /* Store (optional) */; \ - faligndata %F6, %F8, %A6 /* FPA */; \ - fpadd32 %F6, %f6, %F6 /* FPA Group */; \ - srl %x8, 1, %x8 /* IEU0 */; \ - fcmpgt32 %f4, %F4, %x3 /* FPM */; \ - add %sum, %x7, %sum /* IEU0 Group */; \ - inc %x1 /* IEU1 */; \ - STORE5 /* Store (optional) */; \ - faligndata %F8, %F10, %A8 /* FPA */; \ - fpadd32 %F8, %f8, %F8 /* FPA Group */; \ - srl %x1, 1, %x1 /* IEU0 */; \ - fcmpgt32 %f6, %F6, %x4 /* FPM */; \ - add %sum, %x8, %sum /* IEU0 Group */; \ - inc %x2 /* IEU1 */; \ - STORE6 /* Store (optional) */; \ - faligndata %F10, %F12, %A10 /* FPA */; \ - fpadd32 %F10, %f10, %F10 /* FPA Group */; \ - srl %x2, 1, %x2 /* IEU0 */; \ - fcmpgt32 %f8, %F8, %x5 /* FPM */; \ - add %sum, %x1, %sum /* IEU0 Group */; \ - inc %x3 /* IEU1 */; \ - STORE7 /* Store (optional) */; \ - faligndata %F12, %F14, %A12 /* FPA */; \ - fpadd32 %F12, %f12, %F12 /* FPA Group */; \ - srl %x3, 1, %x3 /* IEU0 */; \ - fcmpgt32 %f10, %F10, %x6 /* FPM */; \ - add %sum, %x2, %sum /* IEU0 Group */; \ - inc %x4 /* IEU1 */; \ - STORE8 /* Store (optional) */; \ - fmovd %F14, %B14 /* FPA */; \ - fpadd32 %F14, %f14, %F14 /* FPA Group */; \ - srl %x4, 1, %x4 /* IEU0 */; \ - fcmpgt32 %f12, %F12, %x7 /* FPM */; \ - add %sum, %x3, %sum /* IEU0 Group */; \ - subcc %len, 64, %len /* IEU1 */; \ - BRANCH /* CTI */; \ - fcmpgt32 %f14, %F14, %x8 /* FPM Group */; - -#define END_THE_TRICK(f0,f2,f4,f6,f8,f10,f12,f14,FA,FB,S0,S1,S2,S3,T0,T1,U0,fz) \ - inc %x5 /* IEU0 Group */; \ - fpadd32 %f2, %f0, %S0 /* FPA */; \ - add %sum, %x4, %sum /* IEU1 */; \ - srl %x5, 1, %x5 /* IEU0 Group */; \ - fpadd32 %f6, %f4, %S1 /* FPA */; \ - inc %x6 /* IEU1 */; \ - fpadd32 %f10, %f8, %S2 /* FPA Group */; \ - add %sum, %x5, %sum /* IEU0 */; \ - fcmpgt32 %f0, %S0, %x1 /* FPM */; \ - fpadd32 %f14, %f12, %S3 /* FPA Group */; \ - srl %x6, 1, %x6 /* IEU0 */; \ - fcmpgt32 %f4, %S1, %x2 /* FPM */; \ - add %sum, %x6, %sum /* IEU0 Group */; \ - fzero %fz /* FPA */; \ - fcmpgt32 %f8, %S2, %x3 /* FPM */; \ - inc %x7 /* IEU0 Group */; \ - inc %x8 /* IEU1 */; \ - srl %x7, 1, %x7 /* IEU0 Group */; \ - inc %x1 /* IEU1 */; \ - fpadd32 %S0, %S1, %T0 /* FPA */; \ - fpadd32 %S2, %S3, %T1 /* FPA Group */; \ - add %sum, %x7, %sum /* IEU0 */; \ - fcmpgt32 %f12, %S3, %x4 /* FPM */; \ - srl %x8, 1, %x8 /* IEU0 Group */; \ - inc %x2 /* IEU1 */; \ - srl %x1, 1, %x1 /* IEU0 Group */; \ - add %sum, %x8, %sum /* IEU1 */; \ - add %sum, %x1, %sum /* IEU0 Group */; \ - fcmpgt32 %S0, %T0, %x5 /* FPM */; \ - srl %x2, 1, %x2 /* IEU0 Group */; \ - fcmpgt32 %S2, %T1, %x6 /* FPM */; \ - inc %x3 /* IEU0 Group */; \ - add %sum, %x2, %sum /* IEU1 */; \ - srl %x3, 1, %x3 /* IEU0 Group */; \ - inc %x4 /* IEU1 */; \ - fpadd32 %T0, %T1, %U0 /* FPA Group */; \ - add %sum, %x3, %sum /* IEU0 */; \ - fcmpgt32 %fz, %f2, %x7 /* FPM */; \ - srl %x4, 1, %x4 /* IEU0 Group */; \ - fcmpgt32 %fz, %f6, %x8 /* FPM */; \ - inc %x5 /* IEU0 Group */; \ - add %sum, %x4, %sum /* IEU1 */; \ - srl %x5, 1, %x5 /* IEU0 Group */; \ - fcmpgt32 %fz, %f10, %x1 /* FPM */; \ - inc %x6 /* IEU0 Group */; \ - add %sum, %x5, %sum /* IEU1 */; \ - fmovd %FA, %FB /* FPA Group */; \ - fcmpgt32 %fz, %f14, %x2 /* FPM */; \ - srl %x6, 1, %x6 /* IEU0 Group */; \ - ba,pt %xcc, ett /* CTI */; \ - inc %x7 /* IEU1 */; - -#define END_THE_TRICK1(f0,f2,f4,f6,f8,f10,f12,f14,FA,FB) \ - END_THE_TRICK(f0,f2,f4,f6,f8,f10,f12,f14,FA,FB,f48,f50,f52,f54,f56,f58,f60,f62) - -#define END_THE_TRICK2(S0,S1,S2,S3,T0,T1,U0,U1,V0,fz) \ - fpadd32 %U0, %U1, %V0 /* FPA Group */; \ - srl %x7, 1, %x7 /* IEU0 */; \ - add %sum, %x6, %sum /* IEU1 */; \ - std %V0, [%sp + STACKOFF] /* Store Group */; \ - inc %x8 /* IEU0 */; \ - sub %sum, %x7, %sum /* IEU1 */; \ - srl %x8, 1, %x8 /* IEU0 Group */; \ - fcmpgt32 %fz, %S1, %x3 /* FPM */; \ - inc %x1 /* IEU0 Group */; \ - fcmpgt32 %fz, %S3, %x4 /* FPM */; \ - srl %x1, 1, %x1 /* IEU0 Group */; \ - sub %sum, %x8, %sum /* IEU1 */; \ - ldx [%sp + STACKOFF], %x8 /* Load Group */; \ - inc %x2 /* IEU0 */; \ - sub %sum, %x1, %sum /* IEU1 */; \ - srl %x2, 1, %x2 /* IEU0 Group */; \ - fcmpgt32 %fz, %T1, %x5 /* FPM */; \ - inc %x3 /* IEU0 Group */; \ - fcmpgt32 %T0, %U0, %x6 /* FPM */; \ - srl %x3, 1, %x3 /* IEU0 Group */; \ - sub %sum, %x2, %sum /* IEU1 */; \ - inc %x4 /* IEU0 Group */; \ - sub %sum, %x3, %sum /* IEU1 */; \ - srl %x4, 1, %x4 /* IEU0 Group */; \ - fcmpgt32 %fz, %U1, %x7 /* FPM */; \ - inc %x5 /* IEU0 Group */; \ - fcmpgt32 %U0, %V0, %x1 /* FPM */; \ - srl %x5, 1, %x5 /* IEU0 Group */; \ - sub %sum, %x4, %sum /* IEU1 */; \ - sub %sum, %x5, %sum /* IEU0 Group */; \ - fcmpgt32 %fz, %V0, %x2 /* FPM */; \ - inc %x6 /* IEU0 Group */; \ - inc %x7 /* IEU1 */; \ - srl %x6, 1, %x6 /* IEU0 Group */; \ - inc %x1 /* IEU1 */; \ - srl %x7, 1, %x7 /* IEU0 Group */; \ - add %sum, %x6, %sum /* IEU1 */; \ - srl %x1, 1, %x1 /* IEU0 Group */; \ - sub %sum, %x7, %sum /* IEU1 */; \ - inc %x2 /* IEU0 Group */; \ - add %sum, %x1, %sum /* IEU1 */; \ - srl %x2, 1, %x2 /* IEU0 Group */; \ - sub %sum, %x2, %sum /* IEU0 Group */; \ - addcc %sum, %x8, %sum /* IEU1 Group */; \ - bcs,a,pn %xcc, 33f /* CTI */; \ - add %sum, 1, %sum /* IEU0 (Group) */; \ -33: /* That's it */; - - .text - .globl csum_partial_copy_user_vis - .align 32 -/* %asi should be either ASI_P or ASI_AIUS for csum_partial_copy resp. - * csum_partial_copy_from_user - * This assumes that !((%src^%dst)&3) && !((%src|%dst)&1) && %len >= 256 - */ -csum_partial_copy_user_vis: - andcc %dst, 7, %g0 /* IEU1 Group */ - be,pt %icc, 4f /* CTI */ - and %dst, 0x38, %o4 /* IEU0 */ - mov 1, %g5 /* IEU0 Group */ - andcc %dst, 2, %g0 /* IEU1 */ - be,pt %icc, 1f /* CTI */ - and %dst, 4, %g7 /* IEU0 Group */ - lduh [%src], %g2 /* Load */ - sub %len, 2, %len /* IEU0 Group */ - add %dst, 2, %dst /* IEU1 */ - andcc %dst, 4, %g7 /* IEU1 Group */ - sll %g5, 16, %g5 /* IEU0 */ - stha %g2, [%dst - 2] %asi /* Store Group */ - sll %g2, 16, %g2 /* IEU0 */ - add %src, 2, %src /* IEU1 */ - addcc %g2, %sum, %sum /* IEU1 Group */ - bcs,a,pn %icc, 1f /* CTI */ - add %sum, %g5, %sum /* IEU0 */ -1: lduw [%src], %g2 /* Load */ - brz,a,pn %g7, 4f /* CTI+IEU1 Group */ - and %dst, 0x38, %o4 /* IEU0 */ - add %dst, 4, %dst /* IEU0 Group */ - sub %len, 4, %len /* IEU1 */ - addcc %g2, %sum, %sum /* IEU1 Group */ - bcs,a,pn %icc, 1f /* CTI */ - add %sum, 1, %sum /* IEU0 */ -1: and %dst, 0x38, %o4 /* IEU0 Group */ - stwa %g2, [%dst - 4] %asi /* Store */ - add %src, 4, %src /* IEU1 */ -4: -#ifdef __KERNEL__ - VISEntry -#endif - mov %src, %g7 /* IEU1 Group */ - fzero %f48 /* FPA */ - alignaddr %src, %g0, %src /* Single Group */ - subcc %g7, %src, %g7 /* IEU1 Group */ - be,pt %xcc, 1f /* CTI */ - mov 0x40, %g1 /* IEU0 */ - lduw [%src], %g2 /* Load Group */ - subcc %sum, %g2, %sum /* IEU1 Group+load stall*/ - bcs,a,pn %icc, 1f /* CTI */ - sub %sum, 1, %sum /* IEU0 */ -1: srl %sum, 0, %sum /* IEU0 Group */ - clr %g5 /* IEU1 */ - brz,pn %o4, 3f /* CTI+IEU1 Group */ - sub %g1, %o4, %g1 /* IEU0 */ - ldd [%src], %f0 /* Load */ - clr %o4 /* IEU0 Group */ - andcc %dst, 8, %g0 /* IEU1 */ - be,pn %icc, 1f /* CTI */ - ldd [%src + 8], %f2 /* Load Group */ - add %src, 8, %src /* IEU0 */ - sub %len, 8, %len /* IEU1 */ - fpadd32 %f0, %f48, %f50 /* FPA */ - addcc %dst, 8, %dst /* IEU1 Group */ - faligndata %f0, %f2, %f16 /* FPA */ - fcmpgt32 %f48, %f50, %o4 /* FPM Group */ - fmovd %f2, %f0 /* FPA Group */ - ldd [%src + 8], %f2 /* Load */ - stda %f16, [%dst - 8] %asi /* Store */ - fmovd %f50, %f48 /* FPA */ -1: andcc %g1, 0x10, %g0 /* IEU1 Group */ - be,pn %icc, 1f /* CTI */ - and %g1, 0x20, %g1 /* IEU0 */ - fpadd32 %f0, %f48, %f50 /* FPA */ - ldd [%src + 16], %f4 /* Load Group */ - add %src, 16, %src /* IEU0 */ - add %dst, 16, %dst /* IEU1 */ - faligndata %f0, %f2, %f16 /* FPA */ - fcmpgt32 %f48, %f50, %g5 /* FPM Group */ - sub %len, 16, %len /* IEU0 */ - inc %o4 /* IEU1 */ - stda %f16, [%dst - 16] %asi /* Store Group */ - fpadd32 %f2, %f50, %f48 /* FPA */ - srl %o4, 1, %o5 /* IEU0 */ - faligndata %f2, %f4, %f18 /* FPA Group */ - stda %f18, [%dst - 8] %asi /* Store */ - fcmpgt32 %f50, %f48, %o4 /* FPM Group */ - add %o5, %sum, %sum /* IEU0 */ - ldd [%src + 8], %f2 /* Load */ - fmovd %f4, %f0 /* FPA */ -1: brz,a,pn %g1, 4f /* CTI+IEU1 Group */ - rd %asi, %g2 /* LSU Group + 4 bubbles*/ - inc %g5 /* IEU0 */ - fpadd32 %f0, %f48, %f50 /* FPA */ - ldd [%src + 16], %f4 /* Load Group */ - srl %g5, 1, %g5 /* IEU0 */ - add %dst, 32, %dst /* IEU1 */ - faligndata %f0, %f2, %f16 /* FPA */ - fcmpgt32 %f48, %f50, %o5 /* FPM Group */ - inc %o4 /* IEU0 */ - ldd [%src + 24], %f6 /* Load */ - srl %o4, 1, %o4 /* IEU0 Group */ - add %g5, %sum, %sum /* IEU1 */ - ldd [%src + 32], %f8 /* Load */ - fpadd32 %f2, %f50, %f48 /* FPA */ - faligndata %f2, %f4, %f18 /* FPA Group */ - sub %len, 32, %len /* IEU0 */ - stda %f16, [%dst - 32] %asi /* Store */ - fcmpgt32 %f50, %f48, %g3 /* FPM Group */ - inc %o5 /* IEU0 */ - add %o4, %sum, %sum /* IEU1 */ - fpadd32 %f4, %f48, %f50 /* FPA */ - faligndata %f4, %f6, %f20 /* FPA Group */ - srl %o5, 1, %o5 /* IEU0 */ - fcmpgt32 %f48, %f50, %g5 /* FPM Group */ - add %o5, %sum, %sum /* IEU0 */ - stda %f18, [%dst - 24] %asi /* Store */ - fpadd32 %f6, %f50, %f48 /* FPA */ - inc %g3 /* IEU0 Group */ - stda %f20, [%dst - 16] %asi /* Store */ - add %src, 32, %src /* IEU1 */ - faligndata %f6, %f8, %f22 /* FPA */ - fcmpgt32 %f50, %f48, %o4 /* FPM Group */ - srl %g3, 1, %g3 /* IEU0 */ - stda %f22, [%dst - 8] %asi /* Store */ - add %g3, %sum, %sum /* IEU0 Group */ -3: rd %asi, %g2 /* LSU Group + 4 bubbles*/ -#ifdef __KERNEL__ -4: sethi %hi(vis0s), %g7 /* IEU0 Group */ - or %g2, ASI_BLK_OR, %g2 /* IEU1 */ -#else -4: rd %pc, %g7 /* LSU Group + 4 bubbles*/ -#endif - inc %g5 /* IEU0 Group */ - and %src, 0x38, %g3 /* IEU1 */ - membar #StoreLoad /* LSU Group */ - srl %g5, 1, %g5 /* IEU0 */ - inc %o4 /* IEU1 */ - sll %g3, 8, %g3 /* IEU0 Group */ - sub %len, 0xc0, %len /* IEU1 */ - addcc %g5, %sum, %sum /* IEU1 Group */ - srl %o4, 1, %o4 /* IEU0 */ - add %g7, %g3, %g7 /* IEU0 Group */ - add %o4, %sum, %sum /* IEU1 */ -#ifdef __KERNEL__ - jmpl %g7 + %lo(vis0s), %g0 /* CTI+IEU1 Group */ -#else - jmpl %g7 + (vis0s - 4b), %g0 /* CTI+IEU1 Group */ -#endif - fzero %f32 /* FPA */ - - .align 2048 -vis0s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - ldda [%src] ASI_BLK_P, %f0 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f16 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - fmovd %f48, %f62 /* FPA Group f0 available*/ - faligndata %f0, %f2, %f48 /* FPA Group f2 available*/ - fcmpgt32 %f32, %f2, %x1 /* FPM Group f4 available*/ - fpadd32 %f0, %f62, %f0 /* FPA */ - fcmpgt32 %f32, %f4, %x2 /* FPM Group f6 available*/ - faligndata %f2, %f4, %f50 /* FPA */ - fcmpgt32 %f62, %f0, %x3 /* FPM Group f8 available*/ - faligndata %f4, %f6, %f52 /* FPA */ - fcmpgt32 %f32, %f6, %x4 /* FPM Group f10 available*/ - inc %x1 /* IEU0 */ - faligndata %f6, %f8, %f54 /* FPA */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group f12 available*/ - srl %x1, 1, %x1 /* IEU0 */ - inc %x2 /* IEU1 */ - faligndata %f8, %f10, %f56 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group f14 available*/ - srl %x2, 1, %x2 /* IEU0 */ - add %sum, %x1, %sum /* IEU1 */ - faligndata %f10, %f12, %f58 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - inc %x3 /* IEU0 */ - add %sum, %x2, %sum /* IEU1 */ - faligndata %f12, %f14, %f60 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - srl %x3, 1, %x3 /* IEU0 */ - inc %x4 /* IEU1 */ - fmovd %f14, %f62 /* FPA */ - srl %x4, 1, %x4 /* IEU0 Group */ - add %sum, %x3, %sum /* IEU1 */ -vis0: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f48,f50,f52,f54,f56,f58,f60,f62,f62, - ,LDBLK(f32), STBLK,,,,,,,, - ,bcs,pn %icc, vis0e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f48,f50,f52,f54,f56,f58,f60,f62,f62, - ,LDBLK(f0), STBLK,,,,,,,, - ,bcs,pn %icc, vis0e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f48,f50,f52,f54,f56,f58,f60,f62,f62, - ,LDBLK(f16), STBLK,,,,,,,, - ,bcc,pt %icc, vis0) -vis0e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f48,f50,f52,f54,f56,f58,f60,f62,f32, - ,SYNC, STBLK_XORASI(x1,x2),ST(f48,64),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40),ST(f60,48), - ,add %dst, 56, %dst; add %len, 192 - 8*8, %len; ba,pt %icc, e2) -vis0e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f48,f50,f52,f54,f56,f58,f60,f62,f0, - ,SYNC, STBLK_XORASI(x1,x2),ST(f48,64),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40),ST(f60,48), - ,add %dst, 56, %dst; add %len, 192 - 8*8, %len; ba,pt %icc, e3) -vis0e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f48,f50,f52,f54,f56,f58,f60,f62,f16, - ,SYNC, STBLK_XORASI(x1,x2),ST(f48,64),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40),ST(f60,48), - ,add %dst, 56, %dst; add %len, 192 - 8*8, %len; ba,pt %icc, e1) - .align 2048 -vis1s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - sub %src, 8, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f0 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f16 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - fmovd %f0, %f58 /* FPA Group */ - fmovd %f48, %f0 /* FPA Group */ - fcmpgt32 %f32, %f2, %x2 /* FPM Group */ - faligndata %f2, %f4, %f48 /* FPA */ - fcmpgt32 %f32, %f4, %x3 /* FPM Group */ - faligndata %f4, %f6, %f50 /* FPA */ - fcmpgt32 %f32, %f6, %x4 /* FPM Group */ - faligndata %f6, %f8, %f52 /* FPA */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group */ - inc %x2 /* IEU1 */ - faligndata %f8, %f10, %f54 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - srl %x2, 1, %x2 /* IEU0 */ - faligndata %f10, %f12, %f56 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - inc %x3 /* IEU0 */ - add %sum, %x2, %sum /* IEU1 */ - faligndata %f12, %f14, %f58 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - srl %x3, 1, %x3 /* IEU0 */ - inc %x4 /* IEU1 */ - fmovd %f14, %f60 /* FPA */ - srl %x4, 1, %x4 /* IEU0 Group */ - add %sum, %x3, %sum /* IEU1 */ -vis1: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f62,f48,f50,f52,f54,f56,f58,f60,f60, - ,LDBLK(f32), ,STBLK,,,,,,, - ,bcs,pn %icc, vis1e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f62,f48,f50,f52,f54,f56,f58,f60,f60, - ,LDBLK(f0), ,STBLK,,,,,,, - ,bcs,pn %icc, vis1e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f62,f48,f50,f52,f54,f56,f58,f60,f60, - ,LDBLK(f16), ,STBLK,,,,,,, - ,bcc,pt %icc, vis1) -vis1e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f62,f48,f50,f52,f54,f56,f58,f60,f32, - ,SYNC, ,STBLK_XORASI(x1,x2),ST(f48,0),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40), - ,add %dst, 48, %dst; add %len, 192 - 7*8, %len; ba,pt %icc, e2) -vis1e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f62,f48,f50,f52,f54,f56,f58,f60,f0, - ,SYNC, ,STBLK_XORASI(x1,x2),ST(f48,0),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40), - ,add %dst, 48, %dst; add %len, 192 - 7*8, %len; ba,pt %icc, e3) -vis1e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f62,f48,f50,f52,f54,f56,f58,f60,f16, - ,SYNC, ,STBLK_XORASI(x1,x2),ST(f48,0),ST(f50,8),ST(f52,16),ST(f54,24),ST(f56,32),ST(f58,40), - ,add %dst, 48, %dst; add %len, 192 - 7*8, %len; ba,pt %icc, e1) - .align 2048 -vis2s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - sub %src, 16, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f0 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f16 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - fmovd %f0, %f56 /* FPA Group */ - fmovd %f48, %f0 /* FPA Group */ - sub %dst, 64, %dst /* IEU0 */ - fpsub32 %f2, %f2, %f2 /* FPA Group */ - fcmpgt32 %f32, %f4, %x3 /* FPM Group */ - faligndata %f4, %f6, %f48 /* FPA */ - fcmpgt32 %f32, %f6, %x4 /* FPM Group */ - faligndata %f6, %f8, %f50 /* FPA */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group */ - faligndata %f8, %f10, %f52 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - faligndata %f10, %f12, %f54 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - inc %x3 /* IEU0 */ - faligndata %f12, %f14, %f56 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - srl %x3, 1, %x3 /* IEU0 */ - inc %x4 /* IEU1 */ - fmovd %f14, %f58 /* FPA */ - srl %x4, 1, %x4 /* IEU0 Group */ - add %sum, %x3, %sum /* IEU1 */ -vis2: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f60,f62,f48,f50,f52,f54,f56,f58,f58, - ,LDBLK(f32), ,,STBLK,,,,,, - ,bcs,pn %icc, vis2e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f60,f62,f48,f50,f52,f54,f56,f58,f58, - ,LDBLK(f0), ,,STBLK,,,,,, - ,bcs,pn %icc, vis2e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f60,f62,f48,f50,f52,f54,f56,f58,f58, - ,LDBLK(f16), ,,STBLK,,,,,, - ,bcc,pt %icc, vis2) -vis2e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f60,f62,f48,f50,f52,f54,f56,f58,f32, - ,SYNC, ,,STBLK_XORASI(x2,x3),ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88),ST(f56,96), - ,add %dst, 104, %dst; add %len, 192 - 6*8, %len; ba,pt %icc, e2) -vis2e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f60,f62,f48,f50,f52,f54,f56,f58,f0, - ,SYNC, ,,STBLK_XORASI(x2,x3),ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88),ST(f56,96), - ,add %dst, 104, %dst; add %len, 192 - 6*8, %len; ba,pt %icc, e3) -vis2e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f60,f62,f48,f50,f52,f54,f56,f58,f16, - ,SYNC, ,,STBLK_XORASI(x2,x3),ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88),ST(f56,96), - ,add %dst, 104, %dst; add %len, 192 - 6*8, %len; ba,pt %icc, e1) - .align 2048 -vis3s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - sub %src, 24, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f0 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f16 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - fmovd %f0, %f54 /* FPA Group */ - fmovd %f48, %f0 /* FPA Group */ - sub %dst, 64, %dst /* IEU0 */ - fpsub32 %f2, %f2, %f2 /* FPA Group */ - fpsub32 %f4, %f4, %f4 /* FPA Group */ - fcmpgt32 %f32, %f6, %x4 /* FPM Group */ - faligndata %f6, %f8, %f48 /* FPA */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group */ - faligndata %f8, %f10, %f50 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - faligndata %f10, %f12, %f52 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - faligndata %f12, %f14, %f54 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - fmovd %f14, %f56 /* FPA */ - inc %x4 /* IEU0 */ - srl %x4, 1, %x4 /* IEU0 Group */ -vis3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f58,f60,f62,f48,f50,f52,f54,f56,f56, - ,LDBLK(f32), ,,,STBLK,,,,, - ,bcs,pn %icc, vis3e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f58,f60,f62,f48,f50,f52,f54,f56,f56, - ,LDBLK(f0), ,,,STBLK,,,,, - ,bcs,pn %icc, vis3e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f58,f60,f62,f48,f50,f52,f54,f56,f56, - ,LDBLK(f16), ,,,STBLK,,,,, - ,bcc,pt %icc, vis3) -vis3e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f58,f60,f62,f48,f50,f52,f54,f56,f32, - ,SYNC, ,,,STBLK_XORASI(x3,x4),ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88), - ,add %dst, 96, %dst; add %len, 192 - 5*8, %len; ba,pt %icc, e2) -vis3e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f58,f60,f62,f48,f50,f52,f54,f56,f0, - ,SYNC, ,,,STBLK_XORASI(x3,x4),ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88), - ,add %dst, 96, %dst; add %len, 192 - 5*8, %len; ba,pt %icc, e3) -vis3e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f58,f60,f62,f48,f50,f52,f54,f56,f16, - ,SYNC, ,,,STBLK_XORASI(x3,x4),ST(f48,64),ST(f50,72),ST(f52,80),ST(f54,88), - ,add %dst, 96, %dst; add %len, 192 - 5*8, %len; ba,pt %icc, e1) - .align 2048 -vis4s: wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - sub %src, 32, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f0 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - ldda [%src] ASI_BLK_P, %f16 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - fmovd %f0, %f52 /* FPA Group */ - fmovd %f48, %f0 /* FPA Group */ - sub %dst, 64, %dst /* IEU0 */ - fpsub32 %f2, %f2, %f2 /* FPA Group */ - fpsub32 %f4, %f4, %f4 /* FPA Group */ - fpsub32 %f6, %f6, %f6 /* FPA Group */ - clr %x4 /* IEU0 */ - fcmpgt32 %f32, %f8, %x5 /* FPM Group */ - faligndata %f8, %f10, %f48 /* FPA */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - faligndata %f10, %f12, %f50 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - faligndata %f12, %f14, %f52 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - fmovd %f14, %f54 /* FPA */ -vis4: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f56,f58,f60,f62,f48,f50,f52,f54,f54, - ,LDBLK(f32), ,,,,STBLK,,,, - ,bcs,pn %icc, vis4e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f56,f58,f60,f62,f48,f50,f52,f54,f54, - ,LDBLK(f0), ,,,,STBLK,,,, - ,bcs,pn %icc, vis4e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f56,f58,f60,f62,f48,f50,f52,f54,f54, - ,LDBLK(f16), ,,,,STBLK,,,, - ,bcc,pt %icc, vis4) -vis4e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f56,f58,f60,f62,f48,f50,f52,f54,f32, - ,SYNC, ,,,,STBLK_XORASI(x4,x5),ST(f48,64),ST(f50,72),ST(f52,80), - ,add %dst, 88, %dst; add %len, 192 - 4*8, %len; ba,pt %icc, e2) -vis4e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f56,f58,f60,f62,f48,f50,f52,f54,f0, - ,SYNC, ,,,,STBLK_XORASI(x4,x5),ST(f48,64),ST(f50,72),ST(f52,80), - ,add %dst, 88, %dst; add %len, 192 - 4*8, %len; ba,pt %icc, e3) -vis4e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f56,f58,f60,f62,f48,f50,f52,f54,f16, - ,SYNC, ,,,,STBLK_XORASI(x4,x5),ST(f48,64),ST(f50,72),ST(f52,80), - ,add %dst, 88, %dst; add %len, 192 - 4*8, %len; ba,pt %icc, e1) - .align 2048 -vis5s: ldd [%src+0], %f10 /* Load Group */ - ldd [%src+8], %f12 /* Load Group */ - ldd [%src+16], %f14 /* Load Group */ - add %src, 24, %src /* IEU0 Group */ - wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - ldda [%src] ASI_BLK_P, %f16 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - fmovd %f48, %f0 /* FPA Group */ - fmuld %f32, %f32, %f2 /* FPM */ - clr %x4 /* IEU0 */ - faddd %f32, %f32, %f4 /* FPA Group */ - fmuld %f32, %f32, %f6 /* FPM */ - clr %x5 /* IEU0 */ - faddd %f32, %f32, %f8 /* FPA Group */ - fcmpgt32 %f32, %f10, %x6 /* FPM Group */ - sub %dst, 64, %dst /* IEU0 */ - faligndata %f10, %f12, %f48 /* FPA */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - faligndata %f12, %f14, %f50 /* FPA */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - fmovd %f14, %f52 /* FPA */ -vis5: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f54,f56,f58,f60,f62,f48,f50,f52,f52, - ,LDBLK(f32), ,,,,,STBLK,,, - ,bcs,pn %icc, vis5e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f54,f56,f58,f60,f62,f48,f50,f52,f52, - ,LDBLK(f0), ,,,,,STBLK,,, - ,bcs,pn %icc, vis5e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f54,f56,f58,f60,f62,f48,f50,f52,f52, - ,LDBLK(f16), ,,,,,STBLK,,, - ,bcc,pt %icc, vis5) -vis5e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f54,f56,f58,f60,f62,f48,f50,f52,f32, - ,SYNC, ,,,,,STBLK_XORASI(x5,x6),ST(f48,64),ST(f50,72), - ,add %dst, 80, %dst; add %len, 192 - 3*8, %len; ba,pt %icc, e2) -vis5e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f54,f56,f58,f60,f62,f48,f50,f52,f0, - ,SYNC, ,,,,,STBLK_XORASI(x5,x6),ST(f48,64),ST(f50,72), - ,add %dst, 80, %dst; add %len, 192 - 3*8, %len; ba,pt %icc, e3) -vis5e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f54,f56,f58,f60,f62,f48,f50,f52,f16, - ,SYNC, ,,,,,STBLK_XORASI(x5,x6),ST(f48,64),ST(f50,72), - ,add %dst, 80, %dst; add %len, 192 - 3*8, %len; ba,pt %icc, e1) - .align 2048 -vis6s: ldd [%src+0], %f12 /* Load Group */ - ldd [%src+8], %f14 /* Load Group */ - add %src, 16, %src /* IEU0 Group */ - wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - ldda [%src] ASI_BLK_P, %f16 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - fmovd %f48, %f0 /* FPA Group */ - fmuld %f32, %f32, %f2 /* FPM */ - clr %x4 /* IEU0 */ - faddd %f32, %f32, %f4 /* FPA Group */ - fmuld %f32, %f32, %f6 /* FPM */ - clr %x5 /* IEU0 */ - faddd %f32, %f32, %f8 /* FPA Group */ - fmuld %f32, %f32, %f10 /* FPM */ - clr %x6 /* IEU0 */ - fcmpgt32 %f32, %f12, %x7 /* FPM Group */ - sub %dst, 64, %dst /* IEU0 */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - faligndata %f12, %f14, %f48 /* FPA */ - fmovd %f14, %f50 /* FPA Group */ -vis6: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f52,f54,f56,f58,f60,f62,f48,f50,f50, - ,LDBLK(f32), ,,,,,,STBLK,, - ,bcs,pn %icc, vis6e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f52,f54,f56,f58,f60,f62,f48,f50,f50, - ,LDBLK(f0), ,,,,,,STBLK,, - ,bcs,pn %icc, vis6e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f52,f54,f56,f58,f60,f62,f48,f50,f50, - ,LDBLK(f16), ,,,,,,STBLK,, - ,bcc,pt %icc, vis6) -vis6e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f52,f54,f56,f58,f60,f62,f48,f50,f32, - ,SYNC, ,,,,,,STBLK_XORASI(x6,x7),ST(f48,64), - ,add %dst, 72, %dst; add %len, 192 - 2*8, %len; ba,pt %icc, e2) -vis6e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f52,f54,f56,f58,f60,f62,f48,f50,f0, - ,SYNC, ,,,,,,STBLK_XORASI(x6,x7),ST(f48,64), - ,add %dst, 72, %dst; add %len, 192 - 2*8, %len; ba,pt %icc, e3) -vis6e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f52,f54,f56,f58,f60,f62,f48,f50,f16, - ,SYNC, ,,,,,,STBLK_XORASI(x6,x7),ST(f48,64), - ,add %dst, 72, %dst; add %len, 192 - 2*8, %len; ba,pt %icc, e1) - .align 2048 -vis7s: ldd [%src+0], %f14 /* Load Group */ - add %src, 8, %src /* IEU0 Group */ - wr %g2, ASI_BLK_XOR, %asi /* LSU Group */ - ldda [%src] ASI_BLK_P, %f16 /* Load Group */ - add %src, 64, %src /* IEU0 Group */ - fmovd %f48, %f0 /* FPA Group */ - fmuld %f32, %f32, %f2 /* FPM */ - clr %x4 /* IEU0 */ - faddd %f32, %f32, %f4 /* FPA Group */ - fmuld %f32, %f32, %f6 /* FPM */ - clr %x5 /* IEU0 */ - faddd %f32, %f32, %f8 /* FPA Group */ - fmuld %f32, %f32, %f10 /* FPM */ - clr %x6 /* IEU0 */ - faddd %f32, %f32, %f12 /* FPA Group */ - clr %x7 /* IEU0 */ - fcmpgt32 %f32, %f14, %x8 /* FPM Group */ - sub %dst, 64, %dst /* IEU0 */ - fmovd %f14, %f48 /* FPA */ -vis7: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f50,f52,f54,f56,f58,f60,f62,f48,f48, - ,LDBLK(f32), ,,,,,,,STBLK, - ,bcs,pn %icc, vis7e1) - DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f50,f52,f54,f56,f58,f60,f62,f48,f48, - ,LDBLK(f0), ,,,,,,,STBLK, - ,bcs,pn %icc, vis7e2) - DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f50,f52,f54,f56,f58,f60,f62,f48,f48, - ,LDBLK(f16), ,,,,,,,STBLK, - ,bcc,pt %icc, vis7) -vis7e3: DO_THE_TRICK( f0,f2,f4,f6,f8,f10,f12,f14,f16,f18,f20,f22,f24,f26,f28,f30, - ,f50,f52,f54,f56,f58,f60,f62,f48,f32, - ,SYNC, ,,,,,,,STBLK_XORASI(x7,x8), - ,add %dst, 64, %dst; add %len, 192 - 1*8, %len; ba,pt %icc, e2) -vis7e1: DO_THE_TRICK( f16,f18,f20,f22,f24,f26,f28,f30,f32,f34,f36,f38,f40,f42,f44,f46, - ,f50,f52,f54,f56,f58,f60,f62,f48,f0, - ,SYNC, ,,,,,,,STBLK_XORASI(x7,x8), - ,add %dst, 64, %dst; add %len, 192 - 1*8, %len; ba,pt %icc, e3) -vis7e2: DO_THE_TRICK( f32,f34,f36,f38,f40,f42,f44,f46,f0,f2,f4,f6,f8,f10,f12,f14, - ,f50,f52,f54,f56,f58,f60,f62,f48,f16, - ,SYNC, ,,,,,,,STBLK_XORASI(x7,x8), - ,add %dst, 64, %dst; add %len, 192 - 1*8, %len; ba,pt %icc, e1) -e1: END_THE_TRICK1( f0,f2,f4,f6,f8,f10,f12,f14,f16,f6) -e2: END_THE_TRICK1( f16,f18,f20,f22,f24,f26,f28,f30,f32,f6) -e3: END_THE_TRICK1( f32,f34,f36,f38,f40,f42,f44,f46,f0,f6) -ett: rd %gsr, %x3 /* LSU Group+4bubbles */ - andcc %x3, 7, %x3 /* IEU1 Group */ - add %dst, 8, %dst /* IEU0 */ - bne,pn %icc, 1f /* CTI */ - fzero %f10 /* FPA */ - brz,a,pn %len, 2f /* CTI+IEU1 Group */ - stda %f6, [%dst - 8] %asi /* Store */ -1: cmp %len, 8 /* IEU1 */ - blu,pn %icc, 3f /* CTI */ - sub %src, 64, %src /* IEU0 Group */ -1: ldd [%src], %f2 /* Load Group */ - fpadd32 %f10, %f2, %f12 /* FPA Group+load stall*/ - add %src, 8, %src /* IEU0 */ - add %dst, 8, %dst /* IEU1 */ - faligndata %f6, %f2, %f14 /* FPA Group */ - fcmpgt32 %f10, %f12, %x5 /* FPM Group */ - stda %f14, [%dst - 16] %asi /* Store */ - fmovd %f2, %f6 /* FPA */ - fmovd %f12, %f10 /* FPA Group */ - sub %len, 8, %len /* IEU1 */ - fzero %f16 /* FPA Group - FPU nop */ - fzero %f18 /* FPA Group - FPU nop */ - inc %x5 /* IEU0 */ - srl %x5, 1, %x5 /* IEU0 Group (regdep) */ - cmp %len, 8 /* IEU1 */ - bgeu,pt %icc, 1b /* CTI */ - add %x5, %sum, %sum /* IEU0 Group */ -3: brz,a,pt %x3, 2f /* CTI+IEU1 */ - stda %f6, [%dst - 8] %asi /* Store Group */ - sta %f7, [%dst - 8] %asi /* Store Group */ - sub %dst, 4, %dst /* IEU0 */ - add %len, 4, %len /* IEU1 */ -2: -#ifdef __KERNEL__ - sub %sp, 8, %sp /* IEU0 Group */ -#endif - END_THE_TRICK2( f48,f50,f52,f54,f56,f58,f60,f10,f12,f62) - membar #Sync /* LSU Group */ -#ifdef __KERNEL__ - VISExit - add %sp, 8, %sp /* IEU0 Group */ -#endif -23: brnz,pn %len, 26f /* CTI+IEU1 Group */ -24: sllx %sum, 32, %g1 /* IEU0 */ -25: addcc %sum, %g1, %src /* IEU1 Group */ - srlx %src, 32, %src /* IEU0 Group (regdep) */ - bcs,a,pn %xcc, 1f /* CTI */ - add %src, 1, %src /* IEU1 */ -#ifndef __KERNEL__ -1: retl /* CTI Group brk forced*/ - srl %src, 0, %src /* IEU0 */ -#else -1: retl /* CTI Group brk forced*/ - ldx [%g6 + TI_TASK], %g4 /* Load */ -#endif -26: andcc %len, 8, %g0 /* IEU1 Group */ - be,pn %icc, 1f /* CTI */ - lduw [%src], %o4 /* Load */ - lduw [%src+4], %g2 /* Load Group */ - add %src, 8, %src /* IEU0 */ - add %dst, 8, %dst /* IEU1 */ - sllx %o4, 32, %g5 /* IEU0 Group */ - stwa %o4, [%dst - 8] %asi /* Store */ - or %g5, %g2, %g5 /* IEU0 Group */ - stwa %g2, [%dst - 4] %asi /* Store */ - addcc %g5, %sum, %sum /* IEU1 Group */ - bcs,a,pn %xcc, 1f /* CTI */ - add %sum, 1, %sum /* IEU0 */ -1: andcc %len, 4, %g0 /* IEU1 Group */ - be,a,pn %icc, 1f /* CTI */ - clr %g2 /* IEU0 */ - lduw [%src], %g7 /* Load */ - add %src, 4, %src /* IEU0 Group */ - add %dst, 4, %dst /* IEU1 */ - sllx %g7, 32, %g2 /* IEU0 Group */ - stwa %g7, [%dst - 4] %asi /* Store */ -1: andcc %len, 2, %g0 /* IEU1 */ - be,a,pn %icc, 1f /* CTI */ - clr %g3 /* IEU0 Group */ - lduh [%src], %g7 /* Load */ - add %src, 2, %src /* IEU1 */ - add %dst, 2, %dst /* IEU0 Group */ - sll %g7, 16, %g3 /* IEU0 Group */ - stha %g7, [%dst - 2] %asi /* Store */ -1: andcc %len, 1, %g0 /* IEU1 */ - be,a,pn %icc, 1f /* CTI */ - clr %o5 /* IEU0 Group */ - ldub [%src], %g7 /* Load */ - sll %g7, 8, %o5 /* IEU0 Group */ - stba %g7, [%dst] %asi /* Store */ -1: or %g2, %g3, %g3 /* IEU1 */ - or %o5, %g3, %g3 /* IEU0 Group (regdep) */ - addcc %g3, %sum, %sum /* IEU1 Group (regdep) */ - bcs,a,pn %xcc, 1f /* CTI */ - add %sum, 1, %sum /* IEU0 */ -1: ba,pt %xcc, 25b /* CTI Group */ - sllx %sum, 32, %g1 /* IEU0 */ - -#ifdef __KERNEL__ -end: - - .section __ex_table - .align 4 - .word csum_partial_copy_user_vis, 0, end, cpc_handler -#endif diff --git a/arch/sparc64/lib/VISmemset.S b/arch/sparc64/lib/VISmemset.S deleted file mode 100644 index 152723a490141..0000000000000 --- a/arch/sparc64/lib/VISmemset.S +++ /dev/null @@ -1,240 +0,0 @@ -/* $Id: VISmemset.S,v 1.10 1999/12/23 17:02:16 jj Exp $ - * VISmemset.S: High speed memset operations utilizing the UltraSparc - * Visual Instruction Set. - * - * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) - * Copyright (C) 1996, 1997, 1999 Jakub Jelinek (jakub@redhat.com) - */ - -#include "VIS.h" - -#ifdef REGS_64BIT -#define SET_BLOCKS(base, offset, source) \ - stx source, [base - offset - 0x18]; \ - stx source, [base - offset - 0x10]; \ - stx source, [base - offset - 0x08]; \ - stx source, [base - offset - 0x00]; -#else -#define SET_BLOCKS(base, offset, source) \ - stw source, [base - offset - 0x18]; \ - stw source, [base - offset - 0x14]; \ - stw source, [base - offset - 0x10]; \ - stw source, [base - offset - 0x0c]; \ - stw source, [base - offset - 0x08]; \ - stw source, [base - offset - 0x04]; \ - stw source, [base - offset - 0x00]; \ - stw source, [base - offset + 0x04]; -#endif - -#ifndef __KERNEL__ -/* So that the brz,a,pt in memset doesn't have to get through PLT, here we go... */ -#include "VISbzero.S" -#endif - -#ifdef __KERNEL__ -#include <asm/visasm.h> -#endif - - /* Well, memset is a lot easier to get right than bcopy... */ - .text - .align 32 -#ifdef __KERNEL__ - .globl __memset -__memset: -#endif - .globl memset -memset: -#ifndef __KERNEL__ - brz,a,pt %o1, bzero_private - mov %o2, %o1 -#ifndef REGS_64BIT - srl %o2, 0, %o2 -#endif -#endif - mov %o0, %o4 - cmp %o2, 7 - bleu,pn %xcc, 17f - andcc %o0, 3, %g5 - be,pt %xcc, 4f - and %o1, 0xff, %o1 - cmp %g5, 3 - be,pn %xcc, 2f - stb %o1, [%o0 + 0x00] - cmp %g5, 2 - be,pt %xcc, 2f - stb %o1, [%o0 + 0x01] - stb %o1, [%o0 + 0x02] -2: sub %g5, 4, %g5 - sub %o0, %g5, %o0 - add %o2, %g5, %o2 -4: sllx %o1, 8, %g1 - andcc %o0, 4, %g0 - or %o1, %g1, %o1 - sllx %o1, 16, %g1 - or %o1, %g1, %o1 - be,pt %xcc, 2f -#ifdef REGS_64BIT - sllx %o1, 32, %g1 -#else - cmp %o2, 128 -#endif - stw %o1, [%o0] - sub %o2, 4, %o2 - add %o0, 4, %o0 -2: -#ifdef REGS_64BIT - cmp %o2, 128 - or %o1, %g1, %o1 -#endif - blu,pn %xcc, 9f - andcc %o0, 0x38, %g5 - be,pn %icc, 6f - mov 64, %o5 - andcc %o0, 8, %g0 - be,pn %icc, 1f - sub %o5, %g5, %o5 -#ifdef REGS_64BIT - stx %o1, [%o0] -#else - stw %o1, [%o0] - stw %o1, [%o0 + 4] -#endif - add %o0, 8, %o0 -1: andcc %o5, 16, %g0 - be,pn %icc, 1f - sub %o2, %o5, %o2 -#ifdef REGS_64BIT - stx %o1, [%o0] - stx %o1, [%o0 + 8] -#else - stw %o1, [%o0] - stw %o1, [%o0 + 4] - stw %o1, [%o0 + 8] - stw %o1, [%o0 + 12] -#endif - add %o0, 16, %o0 -1: andcc %o5, 32, %g0 - be,pn %icc, 7f - andncc %o2, 0x3f, %o3 -#ifdef REGS_64BIT - stx %o1, [%o0] - stx %o1, [%o0 + 8] - stx %o1, [%o0 + 16] - stx %o1, [%o0 + 24] -#else - stw %o1, [%o0] - stw %o1, [%o0 + 4] - stw %o1, [%o0 + 8] - stw %o1, [%o0 + 12] - stw %o1, [%o0 + 16] - stw %o1, [%o0 + 20] - stw %o1, [%o0 + 24] - stw %o1, [%o0 + 28] -#endif - add %o0, 32, %o0 -7: be,pn %xcc, 9f - nop -#ifdef __KERNEL__ - VISEntryHalf -#endif - ldd [%o0 - 8], %f0 -18: rd %asi, %g2 - wr %g0, ASI_BLK_P, %asi - membar #StoreStore | #LoadStore - andcc %o3, 0xc0, %g5 - and %o2, 0x3f, %o2 - fmovd %f0, %f2 - fmovd %f0, %f4 - andn %o3, 0xff, %o3 - fmovd %f0, %f6 - cmp %g5, 64 - fmovd %f0, %f8 - fmovd %f0, %f10 - fmovd %f0, %f12 - brz,pn %g5, 10f - fmovd %f0, %f14 - be,pn %icc, 2f - stda %f0, [%o0 + 0x00] %asi - cmp %g5, 128 - be,pn %icc, 2f - stda %f0, [%o0 + 0x40] %asi - stda %f0, [%o0 + 0x80] %asi -2: brz,pn %o3, 12f - add %o0, %g5, %o0 -10: stda %f0, [%o0 + 0x00] %asi - stda %f0, [%o0 + 0x40] %asi - stda %f0, [%o0 + 0x80] %asi - stda %f0, [%o0 + 0xc0] %asi -11: subcc %o3, 256, %o3 - bne,pt %xcc, 10b - add %o0, 256, %o0 -12: -#ifdef __KERNEL__ - wr %g2, %g0, %asi - VISExitHalf -#else -#ifndef REGS_64BIT - wr %g0, FPRS_FEF, %fprs -#endif -#endif - membar #StoreLoad | #StoreStore -9: andcc %o2, 0x78, %g5 - be,pn %xcc, 13f - andcc %o2, 7, %o2 -#ifdef __KERNEL__ -14: srl %g5, 1, %o3 - sethi %hi(13f), %g3 - sub %g3, %o3, %g3 - jmpl %g3 + %lo(13f), %g0 - add %o0, %g5, %o0 -#else -14: rd %pc, %g3 -#ifdef REGS_64BIT - srl %g5, 1, %o3 - sub %g3, %o3, %g3 -#else - sub %g3, %g5, %g3 -#endif - jmpl %g3 + (13f - 14b), %g0 - add %o0, %g5, %o0 -#endif -12: SET_BLOCKS(%o0, 0x68, %o1) - SET_BLOCKS(%o0, 0x48, %o1) - SET_BLOCKS(%o0, 0x28, %o1) - SET_BLOCKS(%o0, 0x08, %o1) -13: be,pn %xcc, 8f - andcc %o2, 4, %g0 - be,pn %xcc, 1f - andcc %o2, 2, %g0 - stw %o1, [%o0] - add %o0, 4, %o0 -1: be,pn %xcc, 1f - andcc %o2, 1, %g0 - sth %o1, [%o0] - add %o0, 2, %o0 -1: bne,a,pn %xcc, 8f - stb %o1, [%o0] -8: retl - mov %o4, %o0 -17: brz,pn %o2, 0f -8: add %o0, 1, %o0 - subcc %o2, 1, %o2 - bne,pt %xcc, 8b - stb %o1, [%o0 - 1] -0: retl - mov %o4, %o0 -6: -#ifdef REGS_64BIT - stx %o1, [%o0] -#else - stw %o1, [%o0] - stw %o1, [%o0 + 4] -#endif - andncc %o2, 0x3f, %o3 - be,pn %xcc, 9b - nop -#ifdef __KERNEL__ - VISEntryHalf -#endif - ba,pt %xcc, 18b - ldd [%o0], %f0 diff --git a/arch/sparc64/lib/atomic.S b/arch/sparc64/lib/atomic.S index 41be4131f8008..e528b8d1a3e69 100644 --- a/arch/sparc64/lib/atomic.S +++ b/arch/sparc64/lib/atomic.S @@ -29,10 +29,10 @@ .globl atomic_add .type atomic_add,#function atomic_add: /* %o0 = increment, %o1 = atomic_ptr */ -1: lduw [%o1], %g5 - add %g5, %o0, %g7 - cas [%o1], %g5, %g7 - cmp %g5, %g7 +1: lduw [%o1], %g1 + add %g1, %o0, %g7 + cas [%o1], %g1, %g7 + cmp %g1, %g7 bne,pn %icc, 1b nop retl @@ -42,10 +42,10 @@ atomic_add: /* %o0 = increment, %o1 = atomic_ptr */ .globl atomic_sub .type atomic_sub,#function atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */ -1: lduw [%o1], %g5 - sub %g5, %o0, %g7 - cas [%o1], %g5, %g7 - cmp %g5, %g7 +1: lduw [%o1], %g1 + sub %g1, %o0, %g7 + cas [%o1], %g1, %g7 + cmp %g1, %g7 bne,pn %icc, 1b nop retl @@ -56,10 +56,10 @@ atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */ .type atomic_add_ret,#function atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ ATOMIC_PRE_BARRIER -1: lduw [%o1], %g5 - add %g5, %o0, %g7 - cas [%o1], %g5, %g7 - cmp %g5, %g7 +1: lduw [%o1], %g1 + add %g1, %o0, %g7 + cas [%o1], %g1, %g7 + cmp %g1, %g7 bne,pn %icc, 1b add %g7, %o0, %g7 ATOMIC_POST_BARRIER @@ -71,10 +71,10 @@ atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ .type atomic_sub_ret,#function atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ ATOMIC_PRE_BARRIER -1: lduw [%o1], %g5 - sub %g5, %o0, %g7 - cas [%o1], %g5, %g7 - cmp %g5, %g7 +1: lduw [%o1], %g1 + sub %g1, %o0, %g7 + cas [%o1], %g1, %g7 + cmp %g1, %g7 bne,pn %icc, 1b sub %g7, %o0, %g7 ATOMIC_POST_BARRIER @@ -85,10 +85,10 @@ atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ .globl atomic64_add .type atomic64_add,#function atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */ -1: ldx [%o1], %g5 - add %g5, %o0, %g7 - casx [%o1], %g5, %g7 - cmp %g5, %g7 +1: ldx [%o1], %g1 + add %g1, %o0, %g7 + casx [%o1], %g1, %g7 + cmp %g1, %g7 bne,pn %xcc, 1b nop retl @@ -98,10 +98,10 @@ atomic64_add: /* %o0 = increment, %o1 = atomic_ptr */ .globl atomic64_sub .type atomic64_sub,#function atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */ -1: ldx [%o1], %g5 - sub %g5, %o0, %g7 - casx [%o1], %g5, %g7 - cmp %g5, %g7 +1: ldx [%o1], %g1 + sub %g1, %o0, %g7 + casx [%o1], %g1, %g7 + cmp %g1, %g7 bne,pn %xcc, 1b nop retl @@ -112,10 +112,10 @@ atomic64_sub: /* %o0 = decrement, %o1 = atomic_ptr */ .type atomic64_add_ret,#function atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ ATOMIC_PRE_BARRIER -1: ldx [%o1], %g5 - add %g5, %o0, %g7 - casx [%o1], %g5, %g7 - cmp %g5, %g7 +1: ldx [%o1], %g1 + add %g1, %o0, %g7 + casx [%o1], %g1, %g7 + cmp %g1, %g7 bne,pn %xcc, 1b add %g7, %o0, %g7 ATOMIC_POST_BARRIER @@ -127,10 +127,10 @@ atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */ .type atomic64_sub_ret,#function atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */ ATOMIC_PRE_BARRIER -1: ldx [%o1], %g5 - sub %g5, %o0, %g7 - casx [%o1], %g5, %g7 - cmp %g5, %g7 +1: ldx [%o1], %g1 + sub %g1, %o0, %g7 + casx [%o1], %g1, %g7 + cmp %g1, %g7 bne,pn %xcc, 1b sub %g7, %o0, %g7 ATOMIC_POST_BARRIER diff --git a/arch/sparc64/lib/bitops.S b/arch/sparc64/lib/bitops.S index fd20171ecfd10..886dcd2b376a0 100644 --- a/arch/sparc64/lib/bitops.S +++ b/arch/sparc64/lib/bitops.S @@ -26,17 +26,17 @@ test_and_set_bit: /* %o0=nr, %o1=addr */ BITOP_PRE_BARRIER srlx %o0, 6, %g1 - mov 1, %g5 + mov 1, %o2 sllx %g1, 3, %g3 and %o0, 63, %g2 - sllx %g5, %g2, %g5 + sllx %o2, %g2, %o2 add %o1, %g3, %o1 1: ldx [%o1], %g7 - or %g7, %g5, %g1 + or %g7, %o2, %g1 casx [%o1], %g7, %g1 cmp %g7, %g1 bne,pn %xcc, 1b - and %g7, %g5, %g2 + and %g7, %o2, %g2 BITOP_POST_BARRIER clr %o0 retl @@ -48,17 +48,17 @@ test_and_set_bit: /* %o0=nr, %o1=addr */ test_and_clear_bit: /* %o0=nr, %o1=addr */ BITOP_PRE_BARRIER srlx %o0, 6, %g1 - mov 1, %g5 + mov 1, %o2 sllx %g1, 3, %g3 and %o0, 63, %g2 - sllx %g5, %g2, %g5 + sllx %o2, %g2, %o2 add %o1, %g3, %o1 1: ldx [%o1], %g7 - andn %g7, %g5, %g1 + andn %g7, %o2, %g1 casx [%o1], %g7, %g1 cmp %g7, %g1 bne,pn %xcc, 1b - and %g7, %g5, %g2 + and %g7, %o2, %g2 BITOP_POST_BARRIER clr %o0 retl @@ -70,17 +70,17 @@ test_and_clear_bit: /* %o0=nr, %o1=addr */ test_and_change_bit: /* %o0=nr, %o1=addr */ BITOP_PRE_BARRIER srlx %o0, 6, %g1 - mov 1, %g5 + mov 1, %o2 sllx %g1, 3, %g3 and %o0, 63, %g2 - sllx %g5, %g2, %g5 + sllx %o2, %g2, %o2 add %o1, %g3, %o1 1: ldx [%o1], %g7 - xor %g7, %g5, %g1 + xor %g7, %o2, %g1 casx [%o1], %g7, %g1 cmp %g7, %g1 bne,pn %xcc, 1b - and %g7, %g5, %g2 + and %g7, %o2, %g2 BITOP_POST_BARRIER clr %o0 retl @@ -91,13 +91,13 @@ test_and_change_bit: /* %o0=nr, %o1=addr */ .type set_bit,#function set_bit: /* %o0=nr, %o1=addr */ srlx %o0, 6, %g1 - mov 1, %g5 + mov 1, %o2 sllx %g1, 3, %g3 and %o0, 63, %g2 - sllx %g5, %g2, %g5 + sllx %o2, %g2, %o2 add %o1, %g3, %o1 1: ldx [%o1], %g7 - or %g7, %g5, %g1 + or %g7, %o2, %g1 casx [%o1], %g7, %g1 cmp %g7, %g1 bne,pn %xcc, 1b @@ -110,13 +110,13 @@ set_bit: /* %o0=nr, %o1=addr */ .type clear_bit,#function clear_bit: /* %o0=nr, %o1=addr */ srlx %o0, 6, %g1 - mov 1, %g5 + mov 1, %o2 sllx %g1, 3, %g3 and %o0, 63, %g2 - sllx %g5, %g2, %g5 + sllx %o2, %g2, %o2 add %o1, %g3, %o1 1: ldx [%o1], %g7 - andn %g7, %g5, %g1 + andn %g7, %o2, %g1 casx [%o1], %g7, %g1 cmp %g7, %g1 bne,pn %xcc, 1b @@ -129,13 +129,13 @@ clear_bit: /* %o0=nr, %o1=addr */ .type change_bit,#function change_bit: /* %o0=nr, %o1=addr */ srlx %o0, 6, %g1 - mov 1, %g5 + mov 1, %o2 sllx %g1, 3, %g3 and %o0, 63, %g2 - sllx %g5, %g2, %g5 + sllx %o2, %g2, %o2 add %o1, %g3, %o1 1: ldx [%o1], %g7 - xor %g7, %g5, %g1 + xor %g7, %o2, %g1 casx [%o1], %g7, %g1 cmp %g7, %g1 bne,pn %xcc, 1b diff --git a/arch/sparc64/lib/bzero.S b/arch/sparc64/lib/bzero.S new file mode 100644 index 0000000000000..21a933ffb7c29 --- /dev/null +++ b/arch/sparc64/lib/bzero.S @@ -0,0 +1,158 @@ +/* bzero.S: Simple prefetching memset, bzero, and clear_user + * implementations. + * + * Copyright (C) 2005 David S. Miller <davem@davemloft.net> + */ + + .text + + .globl __memset + .type __memset, #function +__memset: /* %o0=buf, %o1=pat, %o2=len */ + + .globl memset + .type memset, #function +memset: /* %o0=buf, %o1=pat, %o2=len */ + and %o1, 0xff, %o3 + mov %o2, %o1 + sllx %o3, 8, %g1 + or %g1, %o3, %o2 + sllx %o2, 16, %g1 + or %g1, %o2, %o2 + sllx %o2, 32, %g1 + ba,pt %xcc, 1f + or %g1, %o2, %o2 + + .globl __bzero + .type __bzero, #function +__bzero: /* %o0=buf, %o1=len */ + clr %o2 +1: mov %o0, %o3 + brz,pn %o1, __bzero_done + cmp %o1, 16 + bl,pn %icc, __bzero_tiny + prefetch [%o0 + 0x000], #n_writes + andcc %o0, 0x3, %g0 + be,pt %icc, 2f +1: stb %o2, [%o0 + 0x00] + add %o0, 1, %o0 + andcc %o0, 0x3, %g0 + bne,pn %icc, 1b + sub %o1, 1, %o1 +2: andcc %o0, 0x7, %g0 + be,pt %icc, 3f + stw %o2, [%o0 + 0x00] + sub %o1, 4, %o1 + add %o0, 4, %o0 +3: and %o1, 0x38, %g1 + cmp %o1, 0x40 + andn %o1, 0x3f, %o4 + bl,pn %icc, 5f + and %o1, 0x7, %o1 + prefetch [%o0 + 0x040], #n_writes + prefetch [%o0 + 0x080], #n_writes + prefetch [%o0 + 0x0c0], #n_writes + prefetch [%o0 + 0x100], #n_writes + prefetch [%o0 + 0x140], #n_writes +4: prefetch [%o0 + 0x180], #n_writes + stx %o2, [%o0 + 0x00] + stx %o2, [%o0 + 0x08] + stx %o2, [%o0 + 0x10] + stx %o2, [%o0 + 0x18] + stx %o2, [%o0 + 0x20] + stx %o2, [%o0 + 0x28] + stx %o2, [%o0 + 0x30] + stx %o2, [%o0 + 0x38] + subcc %o4, 0x40, %o4 + bne,pt %icc, 4b + add %o0, 0x40, %o0 + brz,pn %g1, 6f + nop +5: stx %o2, [%o0 + 0x00] + subcc %g1, 8, %g1 + bne,pt %icc, 5b + add %o0, 0x8, %o0 +6: brz,pt %o1, __bzero_done + nop +__bzero_tiny: +1: stb %o2, [%o0 + 0x00] + subcc %o1, 1, %o1 + bne,pt %icc, 1b + add %o0, 1, %o0 +__bzero_done: + retl + mov %o3, %o0 + .size __bzero, .-__bzero + .size __memset, .-__memset + .size memset, .-memset + +#define EX_ST(x,y) \ +98: x,y; \ + .section .fixup; \ + .align 4; \ +99: retl; \ + mov %o1, %o0; \ + .section __ex_table; \ + .align 4; \ + .word 98b, 99b; \ + .text; \ + .align 4; + + .globl __bzero_noasi + .type __bzero_noasi, #function +__bzero_noasi: /* %o0=buf, %o1=len */ + brz,pn %o1, __bzero_noasi_done + cmp %o1, 16 + bl,pn %icc, __bzero_noasi_tiny + EX_ST(prefetcha [%o0 + 0x00] %asi, #n_writes) + andcc %o0, 0x3, %g0 + be,pt %icc, 2f +1: EX_ST(stba %g0, [%o0 + 0x00] %asi) + add %o0, 1, %o0 + andcc %o0, 0x3, %g0 + bne,pn %icc, 1b + sub %o1, 1, %o1 +2: andcc %o0, 0x7, %g0 + be,pt %icc, 3f + EX_ST(stwa %g0, [%o0 + 0x00] %asi) + sub %o1, 4, %o1 + add %o0, 4, %o0 +3: and %o1, 0x38, %g1 + cmp %o1, 0x40 + andn %o1, 0x3f, %o4 + bl,pn %icc, 5f + and %o1, 0x7, %o1 + EX_ST(prefetcha [%o0 + 0x040] %asi, #n_writes) + EX_ST(prefetcha [%o0 + 0x080] %asi, #n_writes) + EX_ST(prefetcha [%o0 + 0x0c0] %asi, #n_writes) + EX_ST(prefetcha [%o0 + 0x100] %asi, #n_writes) + EX_ST(prefetcha [%o0 + 0x140] %asi, #n_writes) +4: EX_ST(prefetcha [%o0 + 0x180] %asi, #n_writes) + EX_ST(stxa %g0, [%o0 + 0x00] %asi) + EX_ST(stxa %g0, [%o0 + 0x08] %asi) + EX_ST(stxa %g0, [%o0 + 0x10] %asi) + EX_ST(stxa %g0, [%o0 + 0x18] %asi) + EX_ST(stxa %g0, [%o0 + 0x20] %asi) + EX_ST(stxa %g0, [%o0 + 0x28] %asi) + EX_ST(stxa %g0, [%o0 + 0x30] %asi) + EX_ST(stxa %g0, [%o0 + 0x38] %asi) + subcc %o4, 0x40, %o4 + bne,pt %icc, 4b + add %o0, 0x40, %o0 + brz,pn %g1, 6f + nop +5: EX_ST(stxa %g0, [%o0 + 0x00] %asi) + subcc %g1, 8, %g1 + bne,pt %icc, 5b + add %o0, 0x8, %o0 +6: brz,pt %o1, __bzero_noasi_done + nop +__bzero_noasi_tiny: +1: EX_ST(stba %g0, [%o0 + 0x00] %asi) + subcc %o1, 1, %o1 + bne,pt %icc, 1b + add %o0, 1, %o0 +__bzero_noasi_done: + retl + clr %o0 + .size __bzero_noasi, .-__bzero_noasi diff --git a/arch/sparc64/lib/checksum.S b/arch/sparc64/lib/checksum.S index dc7c887ca17a2..ba9cd3ccc2b26 100644 --- a/arch/sparc64/lib/checksum.S +++ b/arch/sparc64/lib/checksum.S @@ -13,500 +13,160 @@ * BSD4.4 portable checksum routine */ -#include <asm/errno.h> -#include <asm/head.h> -#include <asm/ptrace.h> -#include <asm/asi.h> -#include <asm/page.h> -#include <asm/thread_info.h> - - /* The problem with the "add with carry" instructions on Ultra - * are two fold. Firstly, they cannot pair with jack shit, - * and also they only add in the 32-bit carry condition bit - * into the accumulated sum. The following is much better. - * For larger chunks we use VIS code, which is faster ;) - */ - -#define src o0 -#define dst o1 -#define len o2 -#define sum o3 - .text - /* I think I have an erection... Once _AGAIN_ the SunSoft - * engineers are caught asleep at the keyboard, tsk tsk... - */ - -#define CSUMCOPY_LASTCHUNK(off, t0, t1) \ - ldxa [%src - off - 0x08] %asi, t0; \ - ldxa [%src - off - 0x00] %asi, t1; \ - nop; nop; \ - addcc t0, %sum, %sum; \ - stw t0, [%dst - off - 0x04]; \ - srlx t0, 32, t0; \ - bcc,pt %xcc, 51f; \ - stw t0, [%dst - off - 0x08]; \ - add %sum, 1, %sum; \ -51: addcc t1, %sum, %sum; \ - stw t1, [%dst - off + 0x04]; \ - srlx t1, 32, t1; \ - bcc,pt %xcc, 52f; \ - stw t1, [%dst - off - 0x00]; \ - add %sum, 1, %sum; \ -52: - -cpc_start: -cc_end_cruft: - andcc %g7, 8, %g0 ! IEU1 Group - be,pn %icc, 1f ! CTI - and %g7, 4, %g5 ! IEU0 - ldxa [%src + 0x00] %asi, %g2 ! Load Group - add %dst, 8, %dst ! IEU0 - add %src, 8, %src ! IEU1 - addcc %g2, %sum, %sum ! IEU1 Group + 2 bubbles - stw %g2, [%dst - 0x04] ! Store - srlx %g2, 32, %g2 ! IEU0 - bcc,pt %xcc, 1f ! CTI Group - stw %g2, [%dst - 0x08] ! Store - add %sum, 1, %sum ! IEU0 -1: brz,pt %g5, 1f ! CTI Group - clr %g2 ! IEU0 - lduwa [%src + 0x00] %asi, %g2 ! Load - add %dst, 4, %dst ! IEU0 Group - add %src, 4, %src ! IEU1 - stw %g2, [%dst - 0x04] ! Store Group + 2 bubbles - sllx %g2, 32, %g2 ! IEU0 -1: andcc %g7, 2, %g0 ! IEU1 - be,pn %icc, 1f ! CTI Group - clr %o4 ! IEU1 - lduha [%src + 0x00] %asi, %o4 ! Load - add %src, 2, %src ! IEU0 Group - add %dst, 2, %dst ! IEU1 - sth %o4, [%dst - 0x2] ! Store Group + 2 bubbles - sll %o4, 16, %o4 ! IEU0 -1: andcc %g7, 1, %g0 ! IEU1 - be,pn %icc, 1f ! CTI Group - clr %o5 ! IEU0 - lduba [%src + 0x00] %asi, %o5 ! Load - stb %o5, [%dst + 0x00] ! Store Group + 2 bubbles - sll %o5, 8, %o5 ! IEU0 -1: or %g2, %o4, %o4 ! IEU1 - or %o5, %o4, %o4 ! IEU0 Group - addcc %o4, %sum, %sum ! IEU1 - bcc,pt %xcc, ccfold ! CTI - nop ! IEU0 Group - b,pt %xcc, ccfold ! CTI - add %sum, 1, %sum ! IEU1 - -cc_fixit: - cmp %len, 6 ! IEU1 Group - bl,a,pn %icc, ccte ! CTI - andcc %len, 0xf, %g7 ! IEU1 Group - andcc %src, 2, %g0 ! IEU1 Group - be,pn %icc, 1f ! CTI - andcc %src, 0x4, %g0 ! IEU1 Group - lduha [%src + 0x00] %asi, %g4 ! Load - sub %len, 2, %len ! IEU0 - add %src, 2, %src ! IEU0 Group - add %dst, 2, %dst ! IEU1 - sll %g4, 16, %g3 ! IEU0 Group + 1 bubble - addcc %g3, %sum, %sum ! IEU1 - bcc,pt %xcc, 0f ! CTI - srl %sum, 16, %g3 ! IEU0 Group - add %g3, 1, %g3 ! IEU0 4 clocks (mispredict) -0: andcc %src, 0x4, %g0 ! IEU1 Group - sth %g4, [%dst - 0x2] ! Store - sll %sum, 16, %sum ! IEU0 - sll %g3, 16, %g3 ! IEU0 Group - srl %sum, 16, %sum ! IEU0 Group - or %g3, %sum, %sum ! IEU0 Group (regdep) -1: be,pt %icc, ccmerge ! CTI - andcc %len, 0xf0, %g1 ! IEU1 - lduwa [%src + 0x00] %asi, %g4 ! Load Group - sub %len, 4, %len ! IEU0 - add %src, 4, %src ! IEU1 - add %dst, 4, %dst ! IEU0 Group - addcc %g4, %sum, %sum ! IEU1 Group + 1 bubble - stw %g4, [%dst - 0x4] ! Store - bcc,pt %xcc, ccmerge ! CTI - andcc %len, 0xf0, %g1 ! IEU1 Group - b,pt %xcc, ccmerge ! CTI 4 clocks (mispredict) - add %sum, 1, %sum ! IEU0 - - .align 32 - .globl csum_partial_copy_sparc64 -csum_partial_copy_sparc64: /* %o0=src, %o1=dest, %o2=len, %o3=sum */ - xorcc %src, %dst, %o4 ! IEU1 Group - srl %sum, 0, %sum ! IEU0 - andcc %o4, 3, %g0 ! IEU1 Group - srl %len, 0, %len ! IEU0 - bne,pn %icc, ccslow ! CTI - andcc %src, 1, %g0 ! IEU1 Group - bne,pn %icc, ccslow ! CTI - cmp %len, 256 ! IEU1 Group - bgeu,pt %icc, csum_partial_copy_vis ! CTI - andcc %src, 7, %g0 ! IEU1 Group - bne,pn %icc, cc_fixit ! CTI - andcc %len, 0xf0, %g1 ! IEU1 Group -ccmerge:be,pn %icc, ccte ! CTI - andcc %len, 0xf, %g7 ! IEU1 Group - sll %g1, 2, %o4 ! IEU0 -13: sethi %hi(12f), %o5 ! IEU0 Group - add %src, %g1, %src ! IEU1 - sub %o5, %o4, %o5 ! IEU0 Group - jmpl %o5 + %lo(12f), %g0 ! CTI Group brk forced - add %dst, %g1, %dst ! IEU0 Group -cctbl: CSUMCOPY_LASTCHUNK(0xe8,%g2,%g3) - CSUMCOPY_LASTCHUNK(0xd8,%g2,%g3) - CSUMCOPY_LASTCHUNK(0xc8,%g2,%g3) - CSUMCOPY_LASTCHUNK(0xb8,%g2,%g3) - CSUMCOPY_LASTCHUNK(0xa8,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x98,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x88,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x78,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x68,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x58,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x48,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x38,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x28,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x18,%g2,%g3) - CSUMCOPY_LASTCHUNK(0x08,%g2,%g3) -12: - andcc %len, 0xf, %g7 ! IEU1 Group -ccte: bne,pn %icc, cc_end_cruft ! CTI - nop ! IEU0 -ccfold: sllx %sum, 32, %o0 ! IEU0 Group - addcc %sum, %o0, %o0 ! IEU1 Group (regdep) - srlx %o0, 32, %o0 ! IEU0 Group (regdep) - bcs,a,pn %xcc, 1f ! CTI - add %o0, 1, %o0 ! IEU1 4 clocks (mispredict) -1: retl ! CTI Group brk forced - ldx [%g6 + TI_TASK], %g4 ! Load - -ccslow: mov 0, %g5 - brlez,pn %len, 4f - andcc %src, 1, %o5 - be,a,pt %icc, 1f - srl %len, 1, %g7 - sub %len, 1, %len - lduba [%src] %asi, %g5 - add %src, 1, %src - stb %g5, [%dst] - srl %len, 1, %g7 - add %dst, 1, %dst -1: brz,a,pn %g7, 3f - andcc %len, 1, %g0 - andcc %src, 2, %g0 - be,a,pt %icc, 1f - srl %g7, 1, %g7 - lduha [%src] %asi, %o4 - sub %len, 2, %len - srl %o4, 8, %g2 - sub %g7, 1, %g7 - stb %g2, [%dst] - add %o4, %g5, %g5 - stb %o4, [%dst + 1] - add %src, 2, %src - srl %g7, 1, %g7 - add %dst, 2, %dst -1: brz,a,pn %g7, 2f - andcc %len, 2, %g0 - lduwa [%src] %asi, %o4 -5: srl %o4, 24, %g2 - srl %o4, 16, %g3 - stb %g2, [%dst] - srl %o4, 8, %g2 - stb %g3, [%dst + 1] - add %src, 4, %src - stb %g2, [%dst + 2] - addcc %o4, %g5, %g5 - stb %o4, [%dst + 3] - addc %g5, %g0, %g5 - add %dst, 4, %dst - subcc %g7, 1, %g7 - bne,a,pt %icc, 5b - lduwa [%src] %asi, %o4 - sll %g5, 16, %g2 - srl %g5, 16, %g5 - srl %g2, 16, %g2 - andcc %len, 2, %g0 - add %g2, %g5, %g5 -2: be,a,pt %icc, 3f - andcc %len, 1, %g0 - lduha [%src] %asi, %o4 - andcc %len, 1, %g0 - srl %o4, 8, %g2 - add %src, 2, %src - stb %g2, [%dst] - add %g5, %o4, %g5 - stb %o4, [%dst + 1] - add %dst, 2, %dst -3: be,a,pt %icc, 1f - sll %g5, 16, %o4 - lduba [%src] %asi, %g2 - sll %g2, 8, %o4 - stb %g2, [%dst] - add %g5, %o4, %g5 - sll %g5, 16, %o4 -1: addcc %o4, %g5, %g5 - srl %g5, 16, %o4 - addc %g0, %o4, %g5 - brz,pt %o5, 4f - srl %g5, 8, %o4 - and %g5, 0xff, %g2 - and %o4, 0xff, %o4 - sll %g2, 8, %g2 - or %g2, %o4, %g5 -4: addcc %sum, %g5, %sum - addc %g0, %sum, %o0 - retl - srl %o0, 0, %o0 -cpc_end: - - /* Now the version with userspace as the destination */ -#define CSUMCOPY_LASTCHUNK_USER(off, t0, t1) \ - ldx [%src - off - 0x08], t0; \ - ldx [%src - off - 0x00], t1; \ - nop; nop; \ - addcc t0, %sum, %sum; \ - stwa t0, [%dst - off - 0x04] %asi; \ - srlx t0, 32, t0; \ - bcc,pt %xcc, 51f; \ - stwa t0, [%dst - off - 0x08] %asi; \ - add %sum, 1, %sum; \ -51: addcc t1, %sum, %sum; \ - stwa t1, [%dst - off + 0x04] %asi; \ - srlx t1, 32, t1; \ - bcc,pt %xcc, 52f; \ - stwa t1, [%dst - off - 0x00] %asi; \ - add %sum, 1, %sum; \ -52: -cpc_user_start: -cc_user_end_cruft: - andcc %g7, 8, %g0 ! IEU1 Group - be,pn %icc, 1f ! CTI - and %g7, 4, %g5 ! IEU0 - ldx [%src + 0x00], %g2 ! Load Group - add %dst, 8, %dst ! IEU0 - add %src, 8, %src ! IEU1 - addcc %g2, %sum, %sum ! IEU1 Group + 2 bubbles - stwa %g2, [%dst - 0x04] %asi ! Store - srlx %g2, 32, %g2 ! IEU0 - bcc,pt %xcc, 1f ! CTI Group - stwa %g2, [%dst - 0x08] %asi ! Store - add %sum, 1, %sum ! IEU0 -1: brz,pt %g5, 1f ! CTI Group - clr %g2 ! IEU0 - lduw [%src + 0x00], %g2 ! Load - add %dst, 4, %dst ! IEU0 Group - add %src, 4, %src ! IEU1 - stwa %g2, [%dst - 0x04] %asi ! Store Group + 2 bubbles - sllx %g2, 32, %g2 ! IEU0 -1: andcc %g7, 2, %g0 ! IEU1 - be,pn %icc, 1f ! CTI Group - clr %o4 ! IEU1 - lduh [%src + 0x00], %o4 ! Load - add %src, 2, %src ! IEU0 Group - add %dst, 2, %dst ! IEU1 - stha %o4, [%dst - 0x2] %asi ! Store Group + 2 bubbles - sll %o4, 16, %o4 ! IEU0 -1: andcc %g7, 1, %g0 ! IEU1 - be,pn %icc, 1f ! CTI Group - clr %o5 ! IEU0 - ldub [%src + 0x00], %o5 ! Load - stba %o5, [%dst + 0x00] %asi ! Store Group + 2 bubbles - sll %o5, 8, %o5 ! IEU0 -1: or %g2, %o4, %o4 ! IEU1 - or %o5, %o4, %o4 ! IEU0 Group - addcc %o4, %sum, %sum ! IEU1 - bcc,pt %xcc, ccuserfold ! CTI - nop ! IEU0 Group - b,pt %xcc, ccuserfold ! CTI - add %sum, 1, %sum ! IEU1 - -cc_user_fixit: - cmp %len, 6 ! IEU1 Group - bl,a,pn %icc, ccuserte ! CTI - andcc %len, 0xf, %g7 ! IEU1 Group - andcc %src, 2, %g0 ! IEU1 Group - be,pn %icc, 1f ! CTI - andcc %src, 0x4, %g0 ! IEU1 Group - lduh [%src + 0x00], %g4 ! Load - sub %len, 2, %len ! IEU0 - add %src, 2, %src ! IEU0 Group - add %dst, 2, %dst ! IEU1 - sll %g4, 16, %g3 ! IEU0 Group + 1 bubble - addcc %g3, %sum, %sum ! IEU1 - bcc,pt %xcc, 0f ! CTI - srl %sum, 16, %g3 ! IEU0 Group - add %g3, 1, %g3 ! IEU0 4 clocks (mispredict) -0: andcc %src, 0x4, %g0 ! IEU1 Group - stha %g4, [%dst - 0x2] %asi ! Store - sll %sum, 16, %sum ! IEU0 - sll %g3, 16, %g3 ! IEU0 Group - srl %sum, 16, %sum ! IEU0 Group - or %g3, %sum, %sum ! IEU0 Group (regdep) -1: be,pt %icc, ccusermerge ! CTI - andcc %len, 0xf0, %g1 ! IEU1 - lduw [%src + 0x00], %g4 ! Load Group - sub %len, 4, %len ! IEU0 - add %src, 4, %src ! IEU1 - add %dst, 4, %dst ! IEU0 Group - addcc %g4, %sum, %sum ! IEU1 Group + 1 bubble - stwa %g4, [%dst - 0x4] %asi ! Store - bcc,pt %xcc, ccusermerge ! CTI - andcc %len, 0xf0, %g1 ! IEU1 Group - b,pt %xcc, ccusermerge ! CTI 4 clocks (mispredict) - add %sum, 1, %sum ! IEU0 +csum_partial_fix_alignment: + /* We checked for zero length already, so there must be + * at least one byte. + */ + be,pt %icc, 1f + nop + ldub [%o0 + 0x00], %o4 + add %o0, 1, %o0 + sub %o1, 1, %o1 +1: andcc %o0, 0x2, %g0 + be,pn %icc, csum_partial_post_align + cmp %o1, 2 + blu,pn %icc, csum_partial_end_cruft + nop + lduh [%o0 + 0x00], %o5 + add %o0, 2, %o0 + sub %o1, 2, %o1 + ba,pt %xcc, csum_partial_post_align + add %o5, %o4, %o4 .align 32 - .globl csum_partial_copy_user_sparc64 -csum_partial_copy_user_sparc64: /* %o0=src, %o1=dest, %o2=len, %o3=sum */ - xorcc %src, %dst, %o4 ! IEU1 Group - srl %sum, 0, %sum ! IEU0 - andcc %o4, 3, %g0 ! IEU1 Group - srl %len, 0, %len ! IEU0 - bne,pn %icc, ccuserslow ! CTI - andcc %src, 1, %g0 ! IEU1 Group - bne,pn %icc, ccuserslow ! CTI - cmp %len, 256 ! IEU1 Group - bgeu,pt %icc, csum_partial_copy_user_vis ! CTI - andcc %src, 7, %g0 ! IEU1 Group - bne,pn %icc, cc_user_fixit ! CTI - andcc %len, 0xf0, %g1 ! IEU1 Group -ccusermerge: - be,pn %icc, ccuserte ! CTI - andcc %len, 0xf, %g7 ! IEU1 Group - sll %g1, 2, %o4 ! IEU0 -13: sethi %hi(12f), %o5 ! IEU0 Group - add %src, %g1, %src ! IEU1 - sub %o5, %o4, %o5 ! IEU0 Group - jmpl %o5 + %lo(12f), %g0 ! CTI Group brk forced - add %dst, %g1, %dst ! IEU0 Group -ccusertbl: - CSUMCOPY_LASTCHUNK_USER(0xe8,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0xd8,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0xc8,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0xb8,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0xa8,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x98,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x88,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x78,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x68,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x58,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x48,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x38,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x28,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x18,%g2,%g3) - CSUMCOPY_LASTCHUNK_USER(0x08,%g2,%g3) -12: - andcc %len, 0xf, %g7 ! IEU1 Group -ccuserte: - bne,pn %icc, cc_user_end_cruft ! CTI - nop ! IEU0 -ccuserfold: - sllx %sum, 32, %o0 ! IEU0 Group - addcc %sum, %o0, %o0 ! IEU1 Group (regdep) - srlx %o0, 32, %o0 ! IEU0 Group (regdep) - bcs,a,pn %xcc, 1f ! CTI - add %o0, 1, %o0 ! IEU1 4 clocks (mispredict) -1: retl ! CTI Group brk forced - ldx [%g6 + TI_TASK], %g4 ! IEU0 Group - -ccuserslow: - mov 0, %g5 - brlez,pn %len, 4f - andcc %src, 1, %o5 - be,a,pt %icc, 1f - srl %len, 1, %g7 - sub %len, 1, %len - ldub [%src], %g5 - add %src, 1, %src - stba %g5, [%dst] %asi - srl %len, 1, %g7 - add %dst, 1, %dst -1: brz,a,pn %g7, 3f - andcc %len, 1, %g0 - andcc %src, 2, %g0 - be,a,pt %icc, 1f - srl %g7, 1, %g7 - lduh [%src], %o4 - sub %len, 2, %len - srl %o4, 8, %g2 - sub %g7, 1, %g7 - stba %g2, [%dst] %asi - add %o4, %g5, %g5 - stba %o4, [%dst + 1] %asi - add %src, 2, %src - srl %g7, 1, %g7 - add %dst, 2, %dst -1: brz,a,pn %g7, 2f - andcc %len, 2, %g0 - lduw [%src], %o4 -5: srl %o4, 24, %g2 - srl %o4, 16, %g3 - stba %g2, [%dst] %asi - srl %o4, 8, %g2 - stba %g3, [%dst + 1] %asi - add %src, 4, %src - stba %g2, [%dst + 2] %asi - addcc %o4, %g5, %g5 - stba %o4, [%dst + 3] %asi - addc %g5, %g0, %g5 - add %dst, 4, %dst - subcc %g7, 1, %g7 - bne,a,pt %icc, 5b - lduw [%src], %o4 - sll %g5, 16, %g2 - srl %g5, 16, %g5 - srl %g2, 16, %g2 - andcc %len, 2, %g0 - add %g2, %g5, %g5 -2: be,a,pt %icc, 3f - andcc %len, 1, %g0 - lduh [%src], %o4 - andcc %len, 1, %g0 - srl %o4, 8, %g2 - add %src, 2, %src - stba %g2, [%dst] %asi - add %g5, %o4, %g5 - stba %o4, [%dst + 1] %asi - add %dst, 2, %dst -3: be,a,pt %icc, 1f - sll %g5, 16, %o4 - ldub [%src], %g2 - sll %g2, 8, %o4 - stba %g2, [%dst] %asi - add %g5, %o4, %g5 - sll %g5, 16, %o4 -1: addcc %o4, %g5, %g5 - srl %g5, 16, %o4 - addc %g0, %o4, %g5 - brz,pt %o5, 4f - srl %g5, 8, %o4 - and %g5, 0xff, %g2 - and %o4, 0xff, %o4 - sll %g2, 8, %g2 - or %g2, %o4, %g5 -4: addcc %sum, %g5, %sum - addc %g0, %sum, %o0 - retl - srl %o0, 0, %o0 -cpc_user_end: - - .globl cpc_handler -cpc_handler: - ldx [%sp + 0x7ff + 128], %g1 - ldub [%g6 + TI_CURRENT_DS], %g3 - sub %g0, EFAULT, %g2 - brnz,a,pt %g1, 1f - st %g2, [%g1] -1: wr %g3, %g0, %asi + .globl csum_partial +csum_partial: /* %o0=buff, %o1=len, %o2=sum */ + prefetch [%o0 + 0x000], #n_reads + clr %o4 + prefetch [%o0 + 0x040], #n_reads + brz,pn %o1, csum_partial_finish + andcc %o0, 0x3, %g0 + + /* We "remember" whether the lowest bit in the address + * was set in %g7. Because if it is, we have to swap + * upper and lower 8 bit fields of the sum we calculate. + */ + bne,pn %icc, csum_partial_fix_alignment + andcc %o0, 0x1, %g7 + +csum_partial_post_align: + prefetch [%o0 + 0x080], #n_reads + andncc %o1, 0x3f, %o3 + + prefetch [%o0 + 0x0c0], #n_reads + sub %o1, %o3, %o1 + brz,pn %o3, 2f + prefetch [%o0 + 0x100], #n_reads + + /* So that we don't need to use the non-pairing + * add-with-carry instructions we accumulate 32-bit + * values into a 64-bit register. At the end of the + * loop we fold it down to 32-bits and so on. + */ + prefetch [%o0 + 0x140], #n_reads +1: lduw [%o0 + 0x00], %o5 + lduw [%o0 + 0x04], %g1 + lduw [%o0 + 0x08], %g2 + add %o4, %o5, %o4 + lduw [%o0 + 0x0c], %g3 + add %o4, %g1, %o4 + lduw [%o0 + 0x10], %o5 + add %o4, %g2, %o4 + lduw [%o0 + 0x14], %g1 + add %o4, %g3, %o4 + lduw [%o0 + 0x18], %g2 + add %o4, %o5, %o4 + lduw [%o0 + 0x1c], %g3 + add %o4, %g1, %o4 + lduw [%o0 + 0x20], %o5 + add %o4, %g2, %o4 + lduw [%o0 + 0x24], %g1 + add %o4, %g3, %o4 + lduw [%o0 + 0x28], %g2 + add %o4, %o5, %o4 + lduw [%o0 + 0x2c], %g3 + add %o4, %g1, %o4 + lduw [%o0 + 0x30], %o5 + add %o4, %g2, %o4 + lduw [%o0 + 0x34], %g1 + add %o4, %g3, %o4 + lduw [%o0 + 0x38], %g2 + add %o4, %o5, %o4 + lduw [%o0 + 0x3c], %g3 + add %o4, %g1, %o4 + prefetch [%o0 + 0x180], #n_reads + add %o4, %g2, %o4 + subcc %o3, 0x40, %o3 + add %o0, 0x40, %o0 + bne,pt %icc, 1b + add %o4, %g3, %o4 + +2: and %o1, 0x3c, %o3 + brz,pn %o3, 2f + sub %o1, %o3, %o1 +1: lduw [%o0 + 0x00], %o5 + subcc %o3, 0x4, %o3 + add %o0, 0x4, %o0 + bne,pt %icc, 1b + add %o4, %o5, %o4 + +2: + /* fold 64-->32 */ + srlx %o4, 32, %o5 + srl %o4, 0, %o4 + add %o4, %o5, %o4 + srlx %o4, 32, %o5 + srl %o4, 0, %o4 + add %o4, %o5, %o4 + + /* fold 32-->16 */ + sethi %hi(0xffff0000), %g1 + srl %o4, 16, %o5 + andn %o4, %g1, %g2 + add %o5, %g2, %o4 + srl %o4, 16, %o5 + andn %o4, %g1, %g2 + add %o5, %g2, %o4 + +csum_partial_end_cruft: + /* %o4 has the 16-bit sum we have calculated so-far. */ + cmp %o1, 2 + blu,pt %icc, 1f + nop + lduh [%o0 + 0x00], %o5 + sub %o1, 2, %o1 + add %o0, 2, %o0 + add %o4, %o5, %o4 +1: brz,pt %o1, 1f + nop + ldub [%o0 + 0x00], %o5 + sub %o1, 1, %o1 + add %o0, 1, %o0 + sllx %o5, 8, %o5 + add %o4, %o5, %o4 +1: + /* fold 32-->16 */ + sethi %hi(0xffff0000), %g1 + srl %o4, 16, %o5 + andn %o4, %g1, %g2 + add %o5, %g2, %o4 + srl %o4, 16, %o5 + andn %o4, %g1, %g2 + add %o5, %g2, %o4 + +1: brz,pt %g7, 1f + nop + + /* We started with an odd byte, byte-swap the result. */ + srl %o4, 8, %o5 + and %o4, 0xff, %g1 + sll %g1, 8, %g1 + or %o5, %g1, %o4 + +1: add %o2, %o4, %o2 + +csum_partial_finish: retl - ldx [%g6 + TI_TASK], %g4 - - .section __ex_table - .align 4 - .word cpc_start, 0, cpc_end, cpc_handler - .word cpc_user_start, 0, cpc_user_end, cpc_handler + mov %o2, %o0 diff --git a/arch/sparc64/lib/csum_copy.S b/arch/sparc64/lib/csum_copy.S new file mode 100644 index 0000000000000..71af488390646 --- /dev/null +++ b/arch/sparc64/lib/csum_copy.S @@ -0,0 +1,308 @@ +/* csum_copy.S: Checksum+copy code for sparc64 + * + * Copyright (C) 2005 David S. Miller <davem@davemloft.net> + */ + +#ifdef __KERNEL__ +#define GLOBAL_SPARE %g7 +#else +#define GLOBAL_SPARE %g5 +#endif + +#ifndef EX_LD +#define EX_LD(x) x +#endif + +#ifndef EX_ST +#define EX_ST(x) x +#endif + +#ifndef EX_RETVAL +#define EX_RETVAL(x) x +#endif + +#ifndef LOAD +#define LOAD(type,addr,dest) type [addr], dest +#endif + +#ifndef STORE +#define STORE(type,src,addr) type src, [addr] +#endif + +#ifndef FUNC_NAME +#define FUNC_NAME csum_partial_copy_nocheck +#endif + + .register %g2, #scratch + .register %g3, #scratch + + .text + +90: + /* We checked for zero length already, so there must be + * at least one byte. + */ + be,pt %icc, 1f + nop + EX_LD(LOAD(ldub, %o0 + 0x00, %o4)) + add %o0, 1, %o0 + sub %o2, 1, %o2 + EX_ST(STORE(stb, %o4, %o1 + 0x00)) + add %o1, 1, %o1 +1: andcc %o0, 0x2, %g0 + be,pn %icc, 80f + cmp %o2, 2 + blu,pn %icc, 60f + nop + EX_LD(LOAD(lduh, %o0 + 0x00, %o5)) + add %o0, 2, %o0 + sub %o2, 2, %o2 + EX_ST(STORE(sth, %o5, %o1 + 0x00)) + add %o1, 2, %o1 + ba,pt %xcc, 80f + add %o5, %o4, %o4 + + .globl FUNC_NAME +FUNC_NAME: /* %o0=src, %o1=dst, %o2=len, %o3=sum */ + LOAD(prefetch, %o0 + 0x000, #n_reads) + xor %o0, %o1, %g1 + clr %o4 + andcc %g1, 0x3, %g0 + bne,pn %icc, 95f + LOAD(prefetch, %o0 + 0x040, #n_reads) + + brz,pn %o2, 70f + andcc %o0, 0x3, %g0 + + /* We "remember" whether the lowest bit in the address + * was set in GLOBAL_SPARE. Because if it is, we have to swap + * upper and lower 8 bit fields of the sum we calculate. + */ + bne,pn %icc, 90b + andcc %o0, 0x1, GLOBAL_SPARE + +80: + LOAD(prefetch, %o0 + 0x080, #n_reads) + andncc %o2, 0x3f, %g3 + + LOAD(prefetch, %o0 + 0x0c0, #n_reads) + sub %o2, %g3, %o2 + brz,pn %g3, 2f + LOAD(prefetch, %o0 + 0x100, #n_reads) + + /* So that we don't need to use the non-pairing + * add-with-carry instructions we accumulate 32-bit + * values into a 64-bit register. At the end of the + * loop we fold it down to 32-bits and so on. + */ + ba,pt %xcc, 1f + LOAD(prefetch, %o0 + 0x140, #n_reads) + + .align 32 +1: EX_LD(LOAD(lduw, %o0 + 0x00, %o5)) + EX_LD(LOAD(lduw, %o0 + 0x04, %g1)) + EX_LD(LOAD(lduw, %o0 + 0x08, %g2)) + add %o4, %o5, %o4 + EX_ST(STORE(stw, %o5, %o1 + 0x00)) + EX_LD(LOAD(lduw, %o0 + 0x0c, %o5)) + add %o4, %g1, %o4 + EX_ST(STORE(stw, %g1, %o1 + 0x04)) + EX_LD(LOAD(lduw, %o0 + 0x10, %g1)) + add %o4, %g2, %o4 + EX_ST(STORE(stw, %g2, %o1 + 0x08)) + EX_LD(LOAD(lduw, %o0 + 0x14, %g2)) + add %o4, %o5, %o4 + EX_ST(STORE(stw, %o5, %o1 + 0x0c)) + EX_LD(LOAD(lduw, %o0 + 0x18, %o5)) + add %o4, %g1, %o4 + EX_ST(STORE(stw, %g1, %o1 + 0x10)) + EX_LD(LOAD(lduw, %o0 + 0x1c, %g1)) + add %o4, %g2, %o4 + EX_ST(STORE(stw, %g2, %o1 + 0x14)) + EX_LD(LOAD(lduw, %o0 + 0x20, %g2)) + add %o4, %o5, %o4 + EX_ST(STORE(stw, %o5, %o1 + 0x18)) + EX_LD(LOAD(lduw, %o0 + 0x24, %o5)) + add %o4, %g1, %o4 + EX_ST(STORE(stw, %g1, %o1 + 0x1c)) + EX_LD(LOAD(lduw, %o0 + 0x28, %g1)) + add %o4, %g2, %o4 + EX_ST(STORE(stw, %g2, %o1 + 0x20)) + EX_LD(LOAD(lduw, %o0 + 0x2c, %g2)) + add %o4, %o5, %o4 + EX_ST(STORE(stw, %o5, %o1 + 0x24)) + EX_LD(LOAD(lduw, %o0 + 0x30, %o5)) + add %o4, %g1, %o4 + EX_ST(STORE(stw, %g1, %o1 + 0x28)) + EX_LD(LOAD(lduw, %o0 + 0x34, %g1)) + add %o4, %g2, %o4 + EX_ST(STORE(stw, %g2, %o1 + 0x2c)) + EX_LD(LOAD(lduw, %o0 + 0x38, %g2)) + add %o4, %o5, %o4 + EX_ST(STORE(stw, %o5, %o1 + 0x30)) + EX_LD(LOAD(lduw, %o0 + 0x3c, %o5)) + add %o4, %g1, %o4 + EX_ST(STORE(stw, %g1, %o1 + 0x34)) + LOAD(prefetch, %o0 + 0x180, #n_reads) + add %o4, %g2, %o4 + EX_ST(STORE(stw, %g2, %o1 + 0x38)) + subcc %g3, 0x40, %g3 + add %o0, 0x40, %o0 + add %o4, %o5, %o4 + EX_ST(STORE(stw, %o5, %o1 + 0x3c)) + bne,pt %icc, 1b + add %o1, 0x40, %o1 + +2: and %o2, 0x3c, %g3 + brz,pn %g3, 2f + sub %o2, %g3, %o2 +1: EX_LD(LOAD(lduw, %o0 + 0x00, %o5)) + subcc %g3, 0x4, %g3 + add %o0, 0x4, %o0 + add %o4, %o5, %o4 + EX_ST(STORE(stw, %o5, %o1 + 0x00)) + bne,pt %icc, 1b + add %o1, 0x4, %o1 + +2: + /* fold 64-->32 */ + srlx %o4, 32, %o5 + srl %o4, 0, %o4 + add %o4, %o5, %o4 + srlx %o4, 32, %o5 + srl %o4, 0, %o4 + add %o4, %o5, %o4 + + /* fold 32-->16 */ + sethi %hi(0xffff0000), %g1 + srl %o4, 16, %o5 + andn %o4, %g1, %g2 + add %o5, %g2, %o4 + srl %o4, 16, %o5 + andn %o4, %g1, %g2 + add %o5, %g2, %o4 + +60: + /* %o4 has the 16-bit sum we have calculated so-far. */ + cmp %o2, 2 + blu,pt %icc, 1f + nop + EX_LD(LOAD(lduh, %o0 + 0x00, %o5)) + sub %o2, 2, %o2 + add %o0, 2, %o0 + add %o4, %o5, %o4 + EX_ST(STORE(sth, %o5, %o1 + 0x00)) + add %o1, 0x2, %o1 +1: brz,pt %o2, 1f + nop + EX_LD(LOAD(ldub, %o0 + 0x00, %o5)) + sub %o2, 1, %o2 + add %o0, 1, %o0 + EX_ST(STORE(stb, %o5, %o1 + 0x00)) + sllx %o5, 8, %o5 + add %o1, 1, %o1 + add %o4, %o5, %o4 +1: + /* fold 32-->16 */ + sethi %hi(0xffff0000), %g1 + srl %o4, 16, %o5 + andn %o4, %g1, %g2 + add %o5, %g2, %o4 + srl %o4, 16, %o5 + andn %o4, %g1, %g2 + add %o5, %g2, %o4 + +1: brz,pt GLOBAL_SPARE, 1f + nop + + /* We started with an odd byte, byte-swap the result. */ + srl %o4, 8, %o5 + and %o4, 0xff, %g1 + sll %g1, 8, %g1 + or %o5, %g1, %o4 + +1: add %o3, %o4, %o3 + +70: + retl + mov %o3, %o0 + +95: mov 0, GLOBAL_SPARE + brlez,pn %o2, 4f + andcc %o0, 1, %o5 + be,a,pt %icc, 1f + srl %o2, 1, %g1 + sub %o2, 1, %o2 + EX_LD(LOAD(ldub, %o0, GLOBAL_SPARE)) + add %o0, 1, %o0 + EX_ST(STORE(stb, GLOBAL_SPARE, %o1)) + srl %o2, 1, %g1 + add %o1, 1, %o1 +1: brz,a,pn %g1, 3f + andcc %o2, 1, %g0 + andcc %o0, 2, %g0 + be,a,pt %icc, 1f + srl %g1, 1, %g1 + EX_LD(LOAD(lduh, %o0, %o4)) + sub %o2, 2, %o2 + srl %o4, 8, %g2 + sub %g1, 1, %g1 + EX_ST(STORE(stb, %g2, %o1)) + add %o4, GLOBAL_SPARE, GLOBAL_SPARE + EX_ST(STORE(stb, %o4, %o1 + 1)) + add %o0, 2, %o0 + srl %g1, 1, %g1 + add %o1, 2, %o1 +1: brz,a,pn %g1, 2f + andcc %o2, 2, %g0 + EX_LD(LOAD(lduw, %o0, %o4)) +5: srl %o4, 24, %g2 + srl %o4, 16, %g3 + EX_ST(STORE(stb, %g2, %o1)) + srl %o4, 8, %g2 + EX_ST(STORE(stb, %g3, %o1 + 1)) + add %o0, 4, %o0 + EX_ST(STORE(stb, %g2, %o1 + 2)) + addcc %o4, GLOBAL_SPARE, GLOBAL_SPARE + EX_ST(STORE(stb, %o4, %o1 + 3)) + addc GLOBAL_SPARE, %g0, GLOBAL_SPARE + add %o1, 4, %o1 + subcc %g1, 1, %g1 + bne,a,pt %icc, 5b + EX_LD(LOAD(lduw, %o0, %o4)) + sll GLOBAL_SPARE, 16, %g2 + srl GLOBAL_SPARE, 16, GLOBAL_SPARE + srl %g2, 16, %g2 + andcc %o2, 2, %g0 + add %g2, GLOBAL_SPARE, GLOBAL_SPARE +2: be,a,pt %icc, 3f + andcc %o2, 1, %g0 + EX_LD(LOAD(lduh, %o0, %o4)) + andcc %o2, 1, %g0 + srl %o4, 8, %g2 + add %o0, 2, %o0 + EX_ST(STORE(stb, %g2, %o1)) + add GLOBAL_SPARE, %o4, GLOBAL_SPARE + EX_ST(STORE(stb, %o4, %o1 + 1)) + add %o1, 2, %o1 +3: be,a,pt %icc, 1f + sll GLOBAL_SPARE, 16, %o4 + EX_LD(LOAD(ldub, %o0, %g2)) + sll %g2, 8, %o4 + EX_ST(STORE(stb, %g2, %o1)) + add GLOBAL_SPARE, %o4, GLOBAL_SPARE + sll GLOBAL_SPARE, 16, %o4 +1: addcc %o4, GLOBAL_SPARE, GLOBAL_SPARE + srl GLOBAL_SPARE, 16, %o4 + addc %g0, %o4, GLOBAL_SPARE + brz,pt %o5, 4f + srl GLOBAL_SPARE, 8, %o4 + and GLOBAL_SPARE, 0xff, %g2 + and %o4, 0xff, %o4 + sll %g2, 8, %g2 + or %g2, %o4, GLOBAL_SPARE +4: addcc %o3, GLOBAL_SPARE, %o3 + addc %g0, %o3, %o0 + retl + srl %o0, 0, %o0 + .size FUNC_NAME, .-FUNC_NAME diff --git a/arch/sparc64/lib/csum_copy_from_user.S b/arch/sparc64/lib/csum_copy_from_user.S new file mode 100644 index 0000000000000..817ebdae39f8e --- /dev/null +++ b/arch/sparc64/lib/csum_copy_from_user.S @@ -0,0 +1,21 @@ +/* csum_copy_from_user.S: Checksum+copy from userspace. + * + * Copyright (C) 2005 David S. Miller (davem@davemloft.net) + */ + +#define EX_LD(x) \ +98: x; \ + .section .fixup; \ + .align 4; \ +99: retl; \ + mov -1, %o0; \ + .section __ex_table; \ + .align 4; \ + .word 98b, 99b; \ + .text; \ + .align 4; + +#define FUNC_NAME __csum_partial_copy_from_user +#define LOAD(type,addr,dest) type##a [addr] %asi, dest + +#include "csum_copy.S" diff --git a/arch/sparc64/lib/csum_copy_to_user.S b/arch/sparc64/lib/csum_copy_to_user.S new file mode 100644 index 0000000000000..c2f9463ea1e26 --- /dev/null +++ b/arch/sparc64/lib/csum_copy_to_user.S @@ -0,0 +1,21 @@ +/* csum_copy_to_user.S: Checksum+copy to userspace. + * + * Copyright (C) 2005 David S. Miller (davem@davemloft.net) + */ + +#define EX_ST(x) \ +98: x; \ + .section .fixup; \ + .align 4; \ +99: retl; \ + mov -1, %o0; \ + .section __ex_table; \ + .align 4; \ + .word 98b, 99b; \ + .text; \ + .align 4; + +#define FUNC_NAME __csum_partial_copy_to_user +#define STORE(type,src,addr) type##a src, [addr] %asi + +#include "csum_copy.S" diff --git a/arch/sparc64/lib/debuglocks.c b/arch/sparc64/lib/debuglocks.c index 46e5ebfb4b7ce..c421e0c653253 100644 --- a/arch/sparc64/lib/debuglocks.c +++ b/arch/sparc64/lib/debuglocks.c @@ -138,15 +138,15 @@ wlock_again: } /* Try once to increment the counter. */ __asm__ __volatile__( -" ldx [%0], %%g5\n" -" brlz,a,pn %%g5, 2f\n" +" ldx [%0], %%g1\n" +" brlz,a,pn %%g1, 2f\n" " mov 1, %0\n" -" add %%g5, 1, %%g7\n" -" casx [%0], %%g5, %%g7\n" -" sub %%g5, %%g7, %0\n" +" add %%g1, 1, %%g7\n" +" casx [%0], %%g1, %%g7\n" +" sub %%g1, %%g7, %0\n" "2:" : "=r" (val) : "0" (&(rw->lock)) - : "g5", "g7", "memory"); + : "g1", "g7", "memory"); membar("#StoreLoad | #StoreStore"); if (val) goto wlock_again; @@ -173,14 +173,14 @@ runlock_again: /* Spin trying to decrement the counter using casx. */ __asm__ __volatile__( " membar #StoreLoad | #LoadLoad\n" -" ldx [%0], %%g5\n" -" sub %%g5, 1, %%g7\n" -" casx [%0], %%g5, %%g7\n" +" ldx [%0], %%g1\n" +" sub %%g1, 1, %%g7\n" +" casx [%0], %%g1, %%g7\n" " membar #StoreLoad | #StoreStore\n" -" sub %%g5, %%g7, %0\n" +" sub %%g1, %%g7, %0\n" : "=r" (val) : "0" (&(rw->lock)) - : "g5", "g7", "memory"); + : "g1", "g7", "memory"); if (val) { if (!--stuck) { if (shown++ <= 2) @@ -216,17 +216,17 @@ wlock_again: __asm__ __volatile__( " mov 1, %%g3\n" " sllx %%g3, 63, %%g3\n" -" ldx [%0], %%g5\n" -" brlz,pn %%g5, 1f\n" -" or %%g5, %%g3, %%g7\n" -" casx [%0], %%g5, %%g7\n" +" ldx [%0], %%g1\n" +" brlz,pn %%g1, 1f\n" +" or %%g1, %%g3, %%g7\n" +" casx [%0], %%g1, %%g7\n" " membar #StoreLoad | #StoreStore\n" " ba,pt %%xcc, 2f\n" -" sub %%g5, %%g7, %0\n" +" sub %%g1, %%g7, %0\n" "1: mov 1, %0\n" "2:" : "=r" (val) : "0" (&(rw->lock)) - : "g3", "g5", "g7", "memory"); + : "g3", "g1", "g7", "memory"); if (val) { /* We couldn't get the write bit. */ if (!--stuck) { @@ -248,15 +248,15 @@ wlock_again: __asm__ __volatile__( " mov 1, %%g3\n" " sllx %%g3, 63, %%g3\n" -"1: ldx [%0], %%g5\n" -" andn %%g5, %%g3, %%g7\n" -" casx [%0], %%g5, %%g7\n" -" cmp %%g5, %%g7\n" +"1: ldx [%0], %%g1\n" +" andn %%g1, %%g3, %%g7\n" +" casx [%0], %%g1, %%g7\n" +" cmp %%g1, %%g7\n" " bne,pn %%xcc, 1b\n" " membar #StoreLoad | #StoreStore" : /* no outputs */ : "r" (&(rw->lock)) - : "g3", "g5", "g7", "cc", "memory"); + : "g3", "g1", "g7", "cc", "memory"); while(rw->lock != 0) { if (!--stuck) { if (shown++ <= 2) @@ -294,14 +294,14 @@ wlock_again: " membar #StoreLoad | #LoadLoad\n" " mov 1, %%g3\n" " sllx %%g3, 63, %%g3\n" -" ldx [%0], %%g5\n" -" andn %%g5, %%g3, %%g7\n" -" casx [%0], %%g5, %%g7\n" +" ldx [%0], %%g1\n" +" andn %%g1, %%g3, %%g7\n" +" casx [%0], %%g1, %%g7\n" " membar #StoreLoad | #StoreStore\n" -" sub %%g5, %%g7, %0\n" +" sub %%g1, %%g7, %0\n" : "=r" (val) : "0" (&(rw->lock)) - : "g3", "g5", "g7", "memory"); + : "g3", "g1", "g7", "memory"); if (val) { if (!--stuck) { if (shown++ <= 2) @@ -323,17 +323,17 @@ int _do_write_trylock (rwlock_t *rw, char *str) __asm__ __volatile__( " mov 1, %%g3\n" " sllx %%g3, 63, %%g3\n" -" ldx [%0], %%g5\n" -" brlz,pn %%g5, 1f\n" -" or %%g5, %%g3, %%g7\n" -" casx [%0], %%g5, %%g7\n" +" ldx [%0], %%g1\n" +" brlz,pn %%g1, 1f\n" +" or %%g1, %%g3, %%g7\n" +" casx [%0], %%g1, %%g7\n" " membar #StoreLoad | #StoreStore\n" " ba,pt %%xcc, 2f\n" -" sub %%g5, %%g7, %0\n" +" sub %%g1, %%g7, %0\n" "1: mov 1, %0\n" "2:" : "=r" (val) : "0" (&(rw->lock)) - : "g3", "g5", "g7", "memory"); + : "g3", "g1", "g7", "memory"); if (val) { put_cpu(); @@ -347,15 +347,15 @@ int _do_write_trylock (rwlock_t *rw, char *str) __asm__ __volatile__( " mov 1, %%g3\n" " sllx %%g3, 63, %%g3\n" -"1: ldx [%0], %%g5\n" -" andn %%g5, %%g3, %%g7\n" -" casx [%0], %%g5, %%g7\n" -" cmp %%g5, %%g7\n" +"1: ldx [%0], %%g1\n" +" andn %%g1, %%g3, %%g7\n" +" casx [%0], %%g1, %%g7\n" +" cmp %%g1, %%g7\n" " bne,pn %%xcc, 1b\n" " membar #StoreLoad | #StoreStore" : /* no outputs */ : "r" (&(rw->lock)) - : "g3", "g5", "g7", "cc", "memory"); + : "g3", "g1", "g7", "cc", "memory"); put_cpu(); diff --git a/arch/sparc64/lib/dec_and_lock.S b/arch/sparc64/lib/dec_and_lock.S index e86906744cf6f..7e6fdaebedbab 100644 --- a/arch/sparc64/lib/dec_and_lock.S +++ b/arch/sparc64/lib/dec_and_lock.S @@ -27,12 +27,12 @@ .globl _atomic_dec_and_lock _atomic_dec_and_lock: /* %o0 = counter, %o1 = lock */ -loop1: lduw [%o0], %g5 - subcc %g5, 1, %g7 +loop1: lduw [%o0], %g2 + subcc %g2, 1, %g7 be,pn %icc, start_to_zero nop -nzero: cas [%o0], %g5, %g7 - cmp %g5, %g7 +nzero: cas [%o0], %g2, %g7 + cmp %g2, %g7 bne,pn %icc, loop1 mov 0, %g1 @@ -50,13 +50,13 @@ to_zero: ldstub [%o1], %g3 brnz,pn %g3, spin_on_lock membar #StoreLoad | #StoreStore -loop2: cas [%o0], %g5, %g7 /* ASSERT(g7 == 0) */ - cmp %g5, %g7 +loop2: cas [%o0], %g2, %g7 /* ASSERT(g7 == 0) */ + cmp %g2, %g7 be,pt %icc, out mov 1, %g1 - lduw [%o0], %g5 - subcc %g5, 1, %g7 + lduw [%o0], %g2 + subcc %g2, 1, %g7 be,pn %icc, loop2 nop membar #StoreStore | #LoadStore diff --git a/arch/sparc64/lib/mcount.S b/arch/sparc64/lib/mcount.S index 4e8c7928c49f1..2ef2e268bdcfd 100644 --- a/arch/sparc64/lib/mcount.S +++ b/arch/sparc64/lib/mcount.S @@ -38,22 +38,22 @@ _mcount: * Check whether %sp is dangerously low. */ ldub [%g6 + TI_FPDEPTH], %g1 - srl %g1, 1, %g5 - add %g5, 1, %g5 - sllx %g5, 8, %g5 ! each fpregs frame is 256b - add %g5, 192, %g5 - add %g6, %g5, %g5 ! where does task_struct+frame end? - sub %g5, STACK_BIAS, %g5 - cmp %sp, %g5 + srl %g1, 1, %g3 + add %g3, 1, %g3 + sllx %g3, 8, %g3 ! each fpregs frame is 256b + add %g3, 192, %g3 + add %g6, %g3, %g3 ! where does task_struct+frame end? + sub %g3, STACK_BIAS, %g3 + cmp %sp, %g3 bg,pt %xcc, 1f - sethi %hi(panicstring), %g5 + sethi %hi(panicstring), %g3 sethi %hi(ovstack), %g7 ! cant move to panic stack fast enough or %g7, %lo(ovstack), %g7 add %g7, OVSTACKSIZE, %g7 sub %g7, STACK_BIAS, %g7 mov %g7, %sp call prom_printf - or %g5, %lo(panicstring), %o0 + or %g3, %lo(panicstring), %o0 call prom_halt nop #endif diff --git a/arch/sparc64/lib/memcmp.S b/arch/sparc64/lib/memcmp.S index d34dc3d874dae..c90ad96c51b9c 100644 --- a/arch/sparc64/lib/memcmp.S +++ b/arch/sparc64/lib/memcmp.S @@ -13,12 +13,12 @@ memcmp: cmp %o2, 0 ! IEU1 Group loop: be,pn %icc, ret_0 ! CTI nop ! IEU0 - ldub [%o0], %g5 ! LSU Group + ldub [%o0], %g7 ! LSU Group ldub [%o1], %g3 ! LSU Group sub %o2, 1, %o2 ! IEU0 add %o0, 1, %o0 ! IEU1 add %o1, 1, %o1 ! IEU0 Group - subcc %g5, %g3, %g3 ! IEU1 Group + subcc %g7, %g3, %g3 ! IEU1 Group be,pt %icc, loop ! CTI cmp %o2, 0 ! IEU1 Group diff --git a/arch/sparc64/lib/memmove.S b/arch/sparc64/lib/memmove.S index 1c1ebbbdf830e..97395802c23c4 100644 --- a/arch/sparc64/lib/memmove.S +++ b/arch/sparc64/lib/memmove.S @@ -12,17 +12,17 @@ memmove: /* o0=dst o1=src o2=len */ mov %o0, %g1 cmp %o0, %o1 bleu,pt %xcc, memcpy - add %o1, %o2, %g5 - cmp %g5, %o0 + add %o1, %o2, %g7 + cmp %g7, %o0 bleu,pt %xcc, memcpy add %o0, %o2, %o5 - sub %g5, 1, %o1 + sub %g7, 1, %o1 sub %o5, 1, %o0 -1: ldub [%o1], %g5 +1: ldub [%o1], %g7 subcc %o2, 1, %o2 sub %o1, 1, %o1 - stb %g5, [%o0] + stb %g7, [%o0] bne,pt %icc, 1b sub %o0, 1, %o0 diff --git a/arch/sparc64/lib/memscan.S b/arch/sparc64/lib/memscan.S index a34c6b9d21e85..5e72d49114179 100644 --- a/arch/sparc64/lib/memscan.S +++ b/arch/sparc64/lib/memscan.S @@ -52,43 +52,43 @@ check_bytes: andcc %o5, 0xff, %g0 add %o0, -5, %g2 ba,pt %xcc, 3f - srlx %o5, 32, %g5 + srlx %o5, 32, %g7 -2: srlx %o5, 8, %g5 +2: srlx %o5, 8, %g7 be,pn %icc, 1f add %o0, -8, %g2 - andcc %g5, 0xff, %g0 - srlx %g5, 8, %g5 + andcc %g7, 0xff, %g0 + srlx %g7, 8, %g7 be,pn %icc, 1f inc %g2 - andcc %g5, 0xff, %g0 + andcc %g7, 0xff, %g0 - srlx %g5, 8, %g5 + srlx %g7, 8, %g7 be,pn %icc, 1f inc %g2 - andcc %g5, 0xff, %g0 - srlx %g5, 8, %g5 + andcc %g7, 0xff, %g0 + srlx %g7, 8, %g7 be,pn %icc, 1f inc %g2 andcc %g3, %o3, %g0 be,a,pn %icc, 2f mov %o0, %g2 -3: andcc %g5, 0xff, %g0 - srlx %g5, 8, %g5 +3: andcc %g7, 0xff, %g0 + srlx %g7, 8, %g7 be,pn %icc, 1f inc %g2 - andcc %g5, 0xff, %g0 - srlx %g5, 8, %g5 + andcc %g7, 0xff, %g0 + srlx %g7, 8, %g7 be,pn %icc, 1f inc %g2 - andcc %g5, 0xff, %g0 - srlx %g5, 8, %g5 + andcc %g7, 0xff, %g0 + srlx %g7, 8, %g7 be,pn %icc, 1f inc %g2 - andcc %g5, 0xff, %g0 - srlx %g5, 8, %g5 + andcc %g7, 0xff, %g0 + srlx %g7, 8, %g7 be,pn %icc, 1f inc %g2 diff --git a/arch/sparc64/lib/rwsem.S b/arch/sparc64/lib/rwsem.S new file mode 100644 index 0000000000000..174ff7b9164c5 --- /dev/null +++ b/arch/sparc64/lib/rwsem.S @@ -0,0 +1,165 @@ +/* rwsem.S: RW semaphore assembler. + * + * Written by David S. Miller (davem@redhat.com), 2001. + * Derived from asm-i386/rwsem.h + */ + +#include <asm/rwsem-const.h> + + .section .sched.text + + .globl __down_read +__down_read: +1: lduw [%o0], %g1 + add %g1, 1, %g7 + cas [%o0], %g1, %g7 + cmp %g1, %g7 + bne,pn %icc, 1b + add %g7, 1, %g7 + cmp %g7, 0 + bl,pn %icc, 3f + membar #StoreLoad | #StoreStore +2: + retl + nop +3: + save %sp, -192, %sp + call rwsem_down_read_failed + mov %i0, %o0 + ret + restore + .size __down_read, .-__down_read + + .globl __down_read_trylock +__down_read_trylock: +1: lduw [%o0], %g1 + add %g1, 1, %g7 + cmp %g7, 0 + bl,pn %icc, 2f + mov 0, %o1 + cas [%o0], %g1, %g7 + cmp %g1, %g7 + bne,pn %icc, 1b + mov 1, %o1 + membar #StoreLoad | #StoreStore +2: retl + mov %o1, %o0 + .size __down_read_trylock, .-__down_read_trylock + + .globl __down_write +__down_write: + sethi %hi(RWSEM_ACTIVE_WRITE_BIAS), %g1 + or %g1, %lo(RWSEM_ACTIVE_WRITE_BIAS), %g1 +1: + lduw [%o0], %g3 + add %g3, %g1, %g7 + cas [%o0], %g3, %g7 + cmp %g3, %g7 + bne,pn %icc, 1b + cmp %g7, 0 + bne,pn %icc, 3f + membar #StoreLoad | #StoreStore +2: retl + nop +3: + save %sp, -192, %sp + call rwsem_down_write_failed + mov %i0, %o0 + ret + restore + .size __down_write, .-__down_write + + .globl __down_write_trylock +__down_write_trylock: + sethi %hi(RWSEM_ACTIVE_WRITE_BIAS), %g1 + or %g1, %lo(RWSEM_ACTIVE_WRITE_BIAS), %g1 +1: + lduw [%o0], %g3 + cmp %g3, 0 + bne,pn %icc, 2f + mov 0, %o1 + add %g3, %g1, %g7 + cas [%o0], %g3, %g7 + cmp %g3, %g7 + bne,pn %icc, 1b + mov 1, %o1 + membar #StoreLoad | #StoreStore +2: retl + mov %o1, %o0 + .size __down_write_trylock, .-__down_write_trylock + + .globl __up_read +__up_read: +1: + lduw [%o0], %g1 + sub %g1, 1, %g7 + cas [%o0], %g1, %g7 + cmp %g1, %g7 + bne,pn %icc, 1b + cmp %g7, 0 + bl,pn %icc, 3f + membar #StoreLoad | #StoreStore +2: retl + nop +3: sethi %hi(RWSEM_ACTIVE_MASK), %g1 + sub %g7, 1, %g7 + or %g1, %lo(RWSEM_ACTIVE_MASK), %g1 + andcc %g7, %g1, %g0 + bne,pn %icc, 2b + nop + save %sp, -192, %sp + call rwsem_wake + mov %i0, %o0 + ret + restore + .size __up_read, .-__up_read + + .globl __up_write +__up_write: + sethi %hi(RWSEM_ACTIVE_WRITE_BIAS), %g1 + or %g1, %lo(RWSEM_ACTIVE_WRITE_BIAS), %g1 +1: + lduw [%o0], %g3 + sub %g3, %g1, %g7 + cas [%o0], %g3, %g7 + cmp %g3, %g7 + bne,pn %icc, 1b + sub %g7, %g1, %g7 + cmp %g7, 0 + bl,pn %icc, 3f + membar #StoreLoad | #StoreStore +2: + retl + nop +3: + save %sp, -192, %sp + call rwsem_wake + mov %i0, %o0 + ret + restore + .size __up_write, .-__up_write + + .globl __downgrade_write +__downgrade_write: + sethi %hi(RWSEM_WAITING_BIAS), %g1 + or %g1, %lo(RWSEM_WAITING_BIAS), %g1 +1: + lduw [%o0], %g3 + sub %g3, %g1, %g7 + cas [%o0], %g3, %g7 + cmp %g3, %g7 + bne,pn %icc, 1b + sub %g7, %g1, %g7 + cmp %g7, 0 + bl,pn %icc, 3f + membar #StoreLoad | #StoreStore +2: + retl + nop +3: + save %sp, -192, %sp + call rwsem_downgrade_wake + mov %i0, %o0 + ret + restore + .size __downgrade_write, .-__downgrade_write diff --git a/arch/sparc64/lib/rwsem.c b/arch/sparc64/lib/rwsem.c deleted file mode 100644 index e19968dbc2d15..0000000000000 --- a/arch/sparc64/lib/rwsem.c +++ /dev/null @@ -1,239 +0,0 @@ -/* rwsem.c: Don't inline expand these suckers all over the place. - * - * Written by David S. Miller (davem@redhat.com), 2001. - * Derived from asm-i386/rwsem.h - */ - -#include <linux/kernel.h> -#include <linux/rwsem.h> -#include <linux/init.h> -#include <linux/module.h> - -extern struct rw_semaphore *FASTCALL(rwsem_down_read_failed(struct rw_semaphore *sem)); -extern struct rw_semaphore *FASTCALL(rwsem_down_write_failed(struct rw_semaphore *sem)); -extern struct rw_semaphore *FASTCALL(rwsem_wake(struct rw_semaphore *)); -extern struct rw_semaphore *FASTCALL(rwsem_downgrade_wake(struct rw_semaphore *)); - -void __sched __down_read(struct rw_semaphore *sem) -{ - __asm__ __volatile__( - "! beginning __down_read\n" - "1:\tlduw [%0], %%g5\n\t" - "add %%g5, 1, %%g7\n\t" - "cas [%0], %%g5, %%g7\n\t" - "cmp %%g5, %%g7\n\t" - "bne,pn %%icc, 1b\n\t" - " add %%g7, 1, %%g7\n\t" - "cmp %%g7, 0\n\t" - "bl,pn %%icc, 3f\n\t" - " membar #StoreLoad | #StoreStore\n" - "2:\n\t" - ".subsection 2\n" - "3:\tmov %0, %%g5\n\t" - "save %%sp, -160, %%sp\n\t" - "mov %%g1, %%l1\n\t" - "mov %%g2, %%l2\n\t" - "mov %%g3, %%l3\n\t" - "call %1\n\t" - " mov %%g5, %%o0\n\t" - "mov %%l1, %%g1\n\t" - "mov %%l2, %%g2\n\t" - "ba,pt %%xcc, 2b\n\t" - " restore %%l3, %%g0, %%g3\n\t" - ".previous\n\t" - "! ending __down_read" - : : "r" (sem), "i" (rwsem_down_read_failed) - : "g5", "g7", "memory", "cc"); -} -EXPORT_SYMBOL(__down_read); - -int __down_read_trylock(struct rw_semaphore *sem) -{ - int result; - - __asm__ __volatile__( - "! beginning __down_read_trylock\n" - "1:\tlduw [%1], %%g5\n\t" - "add %%g5, 1, %%g7\n\t" - "cmp %%g7, 0\n\t" - "bl,pn %%icc, 2f\n\t" - " mov 0, %0\n\t" - "cas [%1], %%g5, %%g7\n\t" - "cmp %%g5, %%g7\n\t" - "bne,pn %%icc, 1b\n\t" - " mov 1, %0\n\t" - "membar #StoreLoad | #StoreStore\n" - "2:\n\t" - "! ending __down_read_trylock" - : "=&r" (result) - : "r" (sem) - : "g5", "g7", "memory", "cc"); - - return result; -} -EXPORT_SYMBOL(__down_read_trylock); - -void __sched __down_write(struct rw_semaphore *sem) -{ - __asm__ __volatile__( - "! beginning __down_write\n\t" - "sethi %%hi(%2), %%g1\n\t" - "or %%g1, %%lo(%2), %%g1\n" - "1:\tlduw [%0], %%g5\n\t" - "add %%g5, %%g1, %%g7\n\t" - "cas [%0], %%g5, %%g7\n\t" - "cmp %%g5, %%g7\n\t" - "bne,pn %%icc, 1b\n\t" - " cmp %%g7, 0\n\t" - "bne,pn %%icc, 3f\n\t" - " membar #StoreLoad | #StoreStore\n" - "2:\n\t" - ".subsection 2\n" - "3:\tmov %0, %%g5\n\t" - "save %%sp, -160, %%sp\n\t" - "mov %%g2, %%l2\n\t" - "mov %%g3, %%l3\n\t" - "call %1\n\t" - " mov %%g5, %%o0\n\t" - "mov %%l2, %%g2\n\t" - "ba,pt %%xcc, 2b\n\t" - " restore %%l3, %%g0, %%g3\n\t" - ".previous\n\t" - "! ending __down_write" - : : "r" (sem), "i" (rwsem_down_write_failed), - "i" (RWSEM_ACTIVE_WRITE_BIAS) - : "g1", "g5", "g7", "memory", "cc"); -} -EXPORT_SYMBOL(__down_write); - -int __down_write_trylock(struct rw_semaphore *sem) -{ - int result; - - __asm__ __volatile__( - "! beginning __down_write_trylock\n\t" - "sethi %%hi(%2), %%g1\n\t" - "or %%g1, %%lo(%2), %%g1\n" - "1:\tlduw [%1], %%g5\n\t" - "cmp %%g5, 0\n\t" - "bne,pn %%icc, 2f\n\t" - " mov 0, %0\n\t" - "add %%g5, %%g1, %%g7\n\t" - "cas [%1], %%g5, %%g7\n\t" - "cmp %%g5, %%g7\n\t" - "bne,pn %%icc, 1b\n\t" - " mov 1, %0\n\t" - "membar #StoreLoad | #StoreStore\n" - "2:\n\t" - "! ending __down_write_trylock" - : "=&r" (result) - : "r" (sem), "i" (RWSEM_ACTIVE_WRITE_BIAS) - : "g1", "g5", "g7", "memory", "cc"); - - return result; -} -EXPORT_SYMBOL(__down_write_trylock); - -void __up_read(struct rw_semaphore *sem) -{ - __asm__ __volatile__( - "! beginning __up_read\n\t" - "1:\tlduw [%0], %%g5\n\t" - "sub %%g5, 1, %%g7\n\t" - "cas [%0], %%g5, %%g7\n\t" - "cmp %%g5, %%g7\n\t" - "bne,pn %%icc, 1b\n\t" - " cmp %%g7, 0\n\t" - "bl,pn %%icc, 3f\n\t" - " membar #StoreLoad | #StoreStore\n" - "2:\n\t" - ".subsection 2\n" - "3:\tsethi %%hi(%2), %%g1\n\t" - "sub %%g7, 1, %%g7\n\t" - "or %%g1, %%lo(%2), %%g1\n\t" - "andcc %%g7, %%g1, %%g0\n\t" - "bne,pn %%icc, 2b\n\t" - " mov %0, %%g5\n\t" - "save %%sp, -160, %%sp\n\t" - "mov %%g2, %%l2\n\t" - "mov %%g3, %%l3\n\t" - "call %1\n\t" - " mov %%g5, %%o0\n\t" - "mov %%l2, %%g2\n\t" - "ba,pt %%xcc, 2b\n\t" - " restore %%l3, %%g0, %%g3\n\t" - ".previous\n\t" - "! ending __up_read" - : : "r" (sem), "i" (rwsem_wake), - "i" (RWSEM_ACTIVE_MASK) - : "g1", "g5", "g7", "memory", "cc"); -} -EXPORT_SYMBOL(__up_read); - -void __up_write(struct rw_semaphore *sem) -{ - __asm__ __volatile__( - "! beginning __up_write\n\t" - "sethi %%hi(%2), %%g1\n\t" - "or %%g1, %%lo(%2), %%g1\n" - "1:\tlduw [%0], %%g5\n\t" - "sub %%g5, %%g1, %%g7\n\t" - "cas [%0], %%g5, %%g7\n\t" - "cmp %%g5, %%g7\n\t" - "bne,pn %%icc, 1b\n\t" - " sub %%g7, %%g1, %%g7\n\t" - "cmp %%g7, 0\n\t" - "bl,pn %%icc, 3f\n\t" - " membar #StoreLoad | #StoreStore\n" - "2:\n\t" - ".subsection 2\n" - "3:\tmov %0, %%g5\n\t" - "save %%sp, -160, %%sp\n\t" - "mov %%g2, %%l2\n\t" - "mov %%g3, %%l3\n\t" - "call %1\n\t" - " mov %%g5, %%o0\n\t" - "mov %%l2, %%g2\n\t" - "ba,pt %%xcc, 2b\n\t" - " restore %%l3, %%g0, %%g3\n\t" - ".previous\n\t" - "! ending __up_write" - : : "r" (sem), "i" (rwsem_wake), - "i" (RWSEM_ACTIVE_WRITE_BIAS) - : "g1", "g5", "g7", "memory", "cc"); -} -EXPORT_SYMBOL(__up_write); - -void __downgrade_write(struct rw_semaphore *sem) -{ - __asm__ __volatile__( - "! beginning __downgrade_write\n\t" - "sethi %%hi(%2), %%g1\n\t" - "or %%g1, %%lo(%2), %%g1\n" - "1:\tlduw [%0], %%g5\n\t" - "sub %%g5, %%g1, %%g7\n\t" - "cas [%0], %%g5, %%g7\n\t" - "cmp %%g5, %%g7\n\t" - "bne,pn %%icc, 1b\n\t" - " sub %%g7, %%g1, %%g7\n\t" - "cmp %%g7, 0\n\t" - "bl,pn %%icc, 3f\n\t" - " membar #StoreLoad | #StoreStore\n" - "2:\n\t" - ".subsection 2\n" - "3:\tmov %0, %%g5\n\t" - "save %%sp, -160, %%sp\n\t" - "mov %%g2, %%l2\n\t" - "mov %%g3, %%l3\n\t" - "call %1\n\t" - " mov %%g5, %%o0\n\t" - "mov %%l2, %%g2\n\t" - "ba,pt %%xcc, 2b\n\t" - " restore %%l3, %%g0, %%g3\n\t" - ".previous\n\t" - "! ending __up_write" - : : "r" (sem), "i" (rwsem_downgrade_wake), - "i" (RWSEM_WAITING_BIAS) - : "g1", "g5", "g7", "memory", "cc"); -} -EXPORT_SYMBOL(__downgrade_write); diff --git a/arch/sparc64/lib/strlen.S b/arch/sparc64/lib/strlen.S index 066ec1ed7d0dd..e9ba1920d818e 100644 --- a/arch/sparc64/lib/strlen.S +++ b/arch/sparc64/lib/strlen.S @@ -48,16 +48,16 @@ strlen: add %o0, 4, %o0 /* Check every byte. */ - srl %o5, 24, %g5 - andcc %g5, 0xff, %g0 + srl %o5, 24, %g7 + andcc %g7, 0xff, %g0 be,pn %icc, 1f add %o0, -4, %o4 - srl %o5, 16, %g5 - andcc %g5, 0xff, %g0 + srl %o5, 16, %g7 + andcc %g7, 0xff, %g0 be,pn %icc, 1f add %o4, 1, %o4 - srl %o5, 8, %g5 - andcc %g5, 0xff, %g0 + srl %o5, 8, %g7 + andcc %g7, 0xff, %g0 be,pn %icc, 1f add %o4, 1, %o4 andcc %o5, 0xff, %g0 diff --git a/arch/sparc64/lib/strlen_user.S b/arch/sparc64/lib/strlen_user.S index 4af69a0adfbcc..9ed54ba14fc63 100644 --- a/arch/sparc64/lib/strlen_user.S +++ b/arch/sparc64/lib/strlen_user.S @@ -54,16 +54,16 @@ __strnlen_user: ba,a,pt %xcc, 1f /* Check every byte. */ -82: srl %o5, 24, %g5 - andcc %g5, 0xff, %g0 +82: srl %o5, 24, %g7 + andcc %g7, 0xff, %g0 be,pn %icc, 1f add %o0, -3, %o4 - srl %o5, 16, %g5 - andcc %g5, 0xff, %g0 + srl %o5, 16, %g7 + andcc %g7, 0xff, %g0 be,pn %icc, 1f add %o4, 1, %o4 - srl %o5, 8, %g5 - andcc %g5, 0xff, %g0 + srl %o5, 8, %g7 + andcc %g7, 0xff, %g0 be,pn %icc, 1f add %o4, 1, %o4 andcc %o5, 0xff, %g0 diff --git a/arch/sparc64/lib/strncpy_from_user.S b/arch/sparc64/lib/strncpy_from_user.S index 93d600a319763..09cbbaa0ebf43 100644 --- a/arch/sparc64/lib/strncpy_from_user.S +++ b/arch/sparc64/lib/strncpy_from_user.S @@ -34,15 +34,15 @@ .type __strncpy_from_user,#function __strncpy_from_user: /* %o0=dest, %o1=src, %o2=count */ - sethi %hi(0b), %o5 ! IEU0 Group - andcc %o1, 7, %g0 ! IEU1 + andcc %o1, 7, %g0 ! IEU1 Group bne,pn %icc, 30f ! CTI - ldx [%o5 + %lo(0b)], %o4 ! Load Group - add %o0, %o2, %g3 ! IEU0 + add %o0, %o2, %g3 ! IEU0 60: ldxa [%o1] %asi, %g1 ! Load Group brlez,pn %o2, 10f ! CTI - sllx %o4, 7, %o5 ! IEU0 Group - mov %o0, %o3 ! IEU1 + mov %o0, %o3 ! IEU0 +50: sethi %hi(0b), %o4 ! IEU0 Group + ldx [%o4 + %lo(0b)], %o4 ! Load + sllx %o4, 7, %o5 ! IEU1 Group 1: sub %g1, %o4, %g2 ! IEU0 Group stx %g1, [%o0] ! Store add %o0, 8, %o0 ! IEU1 @@ -55,34 +55,34 @@ __strncpy_from_user: 10: retl ! CTI Group mov %o2, %o0 ! IEU0 5: srlx %g2, 32, %g7 ! IEU0 Group - sethi %hi(0xff00), %g5 ! IEU1 + sethi %hi(0xff00), %o4 ! IEU1 andcc %g7, %o5, %g0 ! IEU1 Group be,pn %icc, 2f ! CTI - or %g5, %lo(0xff00), %g5 ! IEU0 + or %o4, %lo(0xff00), %o4 ! IEU0 srlx %g1, 48, %g7 ! IEU0 Group - andcc %g7, %g5, %g0 ! IEU1 Group + andcc %g7, %o4, %g0 ! IEU1 Group be,pn %icc, 50f ! CTI andcc %g7, 0xff, %g0 ! IEU1 Group be,pn %icc, 51f ! CTI srlx %g1, 32, %g7 ! IEU0 - andcc %g7, %g5, %g0 ! IEU1 Group + andcc %g7, %o4, %g0 ! IEU1 Group be,pn %icc, 52f ! CTI andcc %g7, 0xff, %g0 ! IEU1 Group be,pn %icc, 53f ! CTI 2: andcc %g2, %o5, %g0 ! IEU1 Group be,pn %icc, 2f ! CTI srl %g1, 16, %g7 ! IEU0 - andcc %g7, %g5, %g0 ! IEU1 Group + andcc %g7, %o4, %g0 ! IEU1 Group be,pn %icc, 54f ! CTI andcc %g7, 0xff, %g0 ! IEU1 Group be,pn %icc, 55f ! CTI - andcc %g1, %g5, %g0 ! IEU1 Group + andcc %g1, %o4, %g0 ! IEU1 Group be,pn %icc, 56f ! CTI andcc %g1, 0xff, %g0 ! IEU1 Group be,a,pn %icc, 57f ! CTI sub %o0, %o3, %o0 ! IEU0 2: cmp %o0, %g3 ! IEU1 Group - bl,a,pt %xcc, 1b ! CTI + bl,a,pt %xcc, 50b ! CTI 62: ldxa [%o1] %asi, %g1 ! Load retl ! CTI Group mov %o2, %o0 ! IEU0 diff --git a/arch/sparc64/lib/xor.S b/arch/sparc64/lib/xor.S index f748fd6bbc389..4cd5d2be1ae1f 100644 --- a/arch/sparc64/lib/xor.S +++ b/arch/sparc64/lib/xor.S @@ -248,7 +248,7 @@ xor_vis_4: .globl xor_vis_5 .type xor_vis_5,#function xor_vis_5: - mov %o5, %g5 + save %sp, -192, %sp rd %fprs, %o5 andcc %o5, FPRS_FEF|FPRS_DU, %g0 be,pt %icc, 0f @@ -256,61 +256,60 @@ xor_vis_5: jmpl %g1 + %lo(VISenter), %g7 add %g7, 8, %g7 0: wr %g0, FPRS_FEF, %fprs - mov %g5, %o5 rd %asi, %g1 wr %g0, ASI_BLK_P, %asi membar #LoadStore|#StoreLoad|#StoreStore - sub %o0, 64, %o0 - ldda [%o1] %asi, %f0 - ldda [%o2] %asi, %f16 + sub %i0, 64, %i0 + ldda [%i1] %asi, %f0 + ldda [%i2] %asi, %f16 -5: ldda [%o3] %asi, %f32 +5: ldda [%i3] %asi, %f32 fxor %f0, %f16, %f48 fxor %f2, %f18, %f50 - add %o1, 64, %o1 + add %i1, 64, %i1 fxor %f4, %f20, %f52 fxor %f6, %f22, %f54 - add %o2, 64, %o2 + add %i2, 64, %i2 fxor %f8, %f24, %f56 fxor %f10, %f26, %f58 fxor %f12, %f28, %f60 fxor %f14, %f30, %f62 - ldda [%o4] %asi, %f16 + ldda [%i4] %asi, %f16 fxor %f48, %f32, %f48 fxor %f50, %f34, %f50 fxor %f52, %f36, %f52 fxor %f54, %f38, %f54 - add %o3, 64, %o3 + add %i3, 64, %i3 fxor %f56, %f40, %f56 fxor %f58, %f42, %f58 fxor %f60, %f44, %f60 fxor %f62, %f46, %f62 - ldda [%o5] %asi, %f32 + ldda [%i5] %asi, %f32 fxor %f48, %f16, %f48 fxor %f50, %f18, %f50 - add %o4, 64, %o4 + add %i4, 64, %i4 fxor %f52, %f20, %f52 fxor %f54, %f22, %f54 - add %o5, 64, %o5 + add %i5, 64, %i5 fxor %f56, %f24, %f56 fxor %f58, %f26, %f58 fxor %f60, %f28, %f60 fxor %f62, %f30, %f62 - ldda [%o1] %asi, %f0 + ldda [%i1] %asi, %f0 fxor %f48, %f32, %f48 fxor %f50, %f34, %f50 fxor %f52, %f36, %f52 fxor %f54, %f38, %f54 fxor %f56, %f40, %f56 fxor %f58, %f42, %f58 - subcc %o0, 64, %o0 + subcc %i0, 64, %i0 fxor %f60, %f44, %f60 fxor %f62, %f46, %f62 - stda %f48, [%o1 - 64] %asi + stda %f48, [%i1 - 64] %asi bne,pt %xcc, 5b - ldda [%o2] %asi, %f16 + ldda [%i2] %asi, %f16 - ldda [%o3] %asi, %f32 + ldda [%i3] %asi, %f32 fxor %f0, %f16, %f48 fxor %f2, %f18, %f50 fxor %f4, %f20, %f52 @@ -319,7 +318,7 @@ xor_vis_5: fxor %f10, %f26, %f58 fxor %f12, %f28, %f60 fxor %f14, %f30, %f62 - ldda [%o4] %asi, %f16 + ldda [%i4] %asi, %f16 fxor %f48, %f32, %f48 fxor %f50, %f34, %f50 fxor %f52, %f36, %f52 @@ -328,7 +327,7 @@ xor_vis_5: fxor %f58, %f42, %f58 fxor %f60, %f44, %f60 fxor %f62, %f46, %f62 - ldda [%o5] %asi, %f32 + ldda [%i5] %asi, %f32 fxor %f48, %f16, %f48 fxor %f50, %f18, %f50 fxor %f52, %f20, %f52 @@ -346,9 +345,10 @@ xor_vis_5: fxor %f58, %f42, %f58 fxor %f60, %f44, %f60 fxor %f62, %f46, %f62 - stda %f48, [%o1] %asi + stda %f48, [%i1] %asi membar #Sync|#StoreStore|#StoreLoad wr %g1, %g0, %asi - retl - wr %g0, 0, %fprs + wr %g0, 0, %fprs + ret + restore .size xor_vis_5, .-xor_vis_5 diff --git a/arch/sparc64/mm/fault.c b/arch/sparc64/mm/fault.c index 45edb9459bcdf..3ffee7b51aed5 100644 --- a/arch/sparc64/mm/fault.c +++ b/arch/sparc64/mm/fault.c @@ -144,7 +144,9 @@ static void unhandled_fault(unsigned long address, struct task_struct *tsk, "at virtual address %016lx\n", (unsigned long)address); } printk(KERN_ALERT "tsk->{mm,active_mm}->context = %016lx\n", - (tsk->mm ? tsk->mm->context : tsk->active_mm->context)); + (tsk->mm ? + CTX_HWBITS(tsk->mm->context) : + CTX_HWBITS(tsk->active_mm->context))); printk(KERN_ALERT "tsk->{mm,active_mm}->pgd = %016lx\n", (tsk->mm ? (unsigned long) tsk->mm->pgd : (unsigned long) tsk->active_mm->pgd)); diff --git a/arch/sparc64/mm/hugetlbpage.c b/arch/sparc64/mm/hugetlbpage.c index ffa207795f1df..5a1f831b2de1b 100644 --- a/arch/sparc64/mm/hugetlbpage.c +++ b/arch/sparc64/mm/hugetlbpage.c @@ -20,6 +20,7 @@ #include <asm/tlb.h> #include <asm/tlbflush.h> #include <asm/cacheflush.h> +#include <asm/mmu_context.h> static pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr) { @@ -217,12 +218,50 @@ void unmap_hugepage_range(struct vm_area_struct *vma, flush_tlb_range(vma, start, end); } +static void context_reload(void *__data) +{ + struct mm_struct *mm = __data; + + if (mm == current->mm) + load_secondary_context(mm); +} + int hugetlb_prefault(struct address_space *mapping, struct vm_area_struct *vma) { struct mm_struct *mm = current->mm; unsigned long addr; int ret = 0; + /* On UltraSPARC-III+ and later, configure the second half of + * the Data-TLB for huge pages. + */ + if (tlb_type == cheetah_plus) { + unsigned long ctx; + + spin_lock(&ctx_alloc_lock); + ctx = mm->context.sparc64_ctx_val; + ctx &= ~CTX_PGSZ_MASK; + ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; + ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; + + if (ctx != mm->context.sparc64_ctx_val) { + /* When changing the page size fields, we + * must perform a context flush so that no + * stale entries match. This flush must + * occur with the original context register + * settings. + */ + do_flush_tlb_mm(mm); + + /* Reload the context register of all processors + * also executing in this address space. + */ + mm->context.sparc64_ctx_val = ctx; + on_each_cpu(context_reload, mm, 0, 0); + } + spin_unlock(&ctx_alloc_lock); + } + BUG_ON(vma->vm_start & ~HPAGE_MASK); BUG_ON(vma->vm_end & ~HPAGE_MASK); diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c index 0e62b62c7dd44..89022ccaa75bb 100644 --- a/arch/sparc64/mm/init.c +++ b/arch/sparc64/mm/init.c @@ -61,7 +61,7 @@ static unsigned long bootmap_base; /* get_new_mmu_context() uses "cache + 1". */ DEFINE_SPINLOCK(ctx_alloc_lock); unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; -#define CTX_BMAP_SLOTS (1UL << (CTX_VERSION_SHIFT - 6)) +#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6)) unsigned long mmu_context_bmap[CTX_BMAP_SLOTS]; /* References to special section boundaries */ @@ -85,40 +85,14 @@ void check_pgt_cache(void) preempt_disable(); if (pgtable_cache_size > PGT_CACHE_HIGH) { do { -#ifdef CONFIG_SMP if (pgd_quicklist) free_pgd_slow(get_pgd_fast()); -#endif if (pte_quicklist[0]) free_pte_slow(pte_alloc_one_fast(NULL, 0)); if (pte_quicklist[1]) free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10))); } while (pgtable_cache_size > PGT_CACHE_LOW); } -#ifndef CONFIG_SMP - if (pgd_cache_size > PGT_CACHE_HIGH / 4) { - struct page *page, *page2; - for (page2 = NULL, page = (struct page *)pgd_quicklist; page;) { - if ((unsigned long)page->lru.prev == 3) { - if (page2) - page2->lru.next = page->lru.next; - else - pgd_quicklist = (void *) page->lru.next; - pgd_cache_size -= 2; - __free_page(page); - if (page2) - page = (struct page *)page2->lru.next; - else - page = (struct page *)pgd_quicklist; - if (pgd_cache_size <= PGT_CACHE_LOW / 4) - break; - continue; - } - page2 = page; - page = (struct page *)page->lru.next; - } - } -#endif preempt_enable(); } @@ -135,7 +109,7 @@ __inline__ void flush_dcache_page_impl(struct page *page) atomic_inc(&dcpage_flushes); #endif -#if (L1DCACHE_SIZE > PAGE_SIZE) +#ifdef DCACHE_ALIASING_POSSIBLE __flush_dcache_page(page_address(page), ((tlb_type == spitfire) && page_mapping(page) != NULL)); @@ -158,15 +132,15 @@ static __inline__ void set_dcache_dirty(struct page *page, int this_cpu) mask = (mask << 24) | (1UL << PG_dcache_dirty); __asm__ __volatile__("1:\n\t" "ldx [%2], %%g7\n\t" - "and %%g7, %1, %%g5\n\t" - "or %%g5, %0, %%g5\n\t" - "casx [%2], %%g7, %%g5\n\t" - "cmp %%g7, %%g5\n\t" + "and %%g7, %1, %%g1\n\t" + "or %%g1, %0, %%g1\n\t" + "casx [%2], %%g7, %%g1\n\t" + "cmp %%g7, %%g1\n\t" "bne,pn %%xcc, 1b\n\t" " membar #StoreLoad | #StoreStore" : /* no outputs */ : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) - : "g5", "g7"); + : "g1", "g7"); } static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) @@ -176,20 +150,20 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c __asm__ __volatile__("! test_and_clear_dcache_dirty\n" "1:\n\t" "ldx [%2], %%g7\n\t" - "srlx %%g7, 24, %%g5\n\t" - "and %%g5, %3, %%g5\n\t" - "cmp %%g5, %0\n\t" + "srlx %%g7, 24, %%g1\n\t" + "and %%g1, %3, %%g1\n\t" + "cmp %%g1, %0\n\t" "bne,pn %%icc, 2f\n\t" - " andn %%g7, %1, %%g5\n\t" - "casx [%2], %%g7, %%g5\n\t" - "cmp %%g7, %%g5\n\t" + " andn %%g7, %1, %%g1\n\t" + "casx [%2], %%g7, %%g1\n\t" + "cmp %%g7, %%g1\n\t" "bne,pn %%xcc, 1b\n\t" " membar #StoreLoad | #StoreStore\n" "2:" : /* no outputs */ : "r" (cpu), "r" (mask), "r" (&page->flags), "i" (NR_CPUS - 1UL) - : "g5", "g7"); + : "g1", "g7"); } extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code); @@ -219,8 +193,9 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t p put_cpu(); } + if (get_thread_fault_code()) - __update_mmu_cache(vma->vm_mm->context & TAG_CONTEXT_BITS, + __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context), address, pte, get_thread_fault_code()); } @@ -281,9 +256,6 @@ void show_mem(void) printk("%ld pages of RAM\n", num_physpages); printk("%d free pages\n", nr_free_pages()); printk("%d pages in page table cache\n",pgtable_cache_size); -#ifndef CONFIG_SMP - printk("%d entries in page dir cache\n",pgd_cache_size); -#endif } void mmu_info(struct seq_file *m) @@ -392,10 +364,10 @@ static void inherit_prom_mappings(void) n = n / sizeof(*trans); /* - * The obp translations are saved based on 8k pagesize, since obp can use - * a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000, ie obp - * range, are handled in entry.S and do not use the vpte scheme (see rant - * in inherit_locked_prom_mappings()). + * The obp translations are saved based on 8k pagesize, since obp can + * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000, + * ie obp range, are handled in entry.S and do not use the vpte scheme + * (see rant in inherit_locked_prom_mappings()). */ #define OBP_PMD_SIZE 2048 prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base); @@ -449,11 +421,15 @@ static void inherit_prom_mappings(void) prom_printf("Remapping the kernel... "); /* Spitfire Errata #32 workaround */ + /* NOTE: Using plain zero for the context value is + * correct here, we are not using the Linux trap + * tables yet so we should not use the special + * UltraSPARC-III+ page size encodings yet. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ - : "r" (0), - "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); + : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); switch (tlb_type) { default: @@ -513,6 +489,11 @@ static void inherit_prom_mappings(void) tte_vaddr = (unsigned long) KERNBASE; /* Spitfire Errata #32 workaround */ + /* NOTE: Using plain zero for the context value is + * correct here, we are not using the Linux trap + * tables yet so we should not use the special + * UltraSPARC-III+ page size encodings yet. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -531,6 +512,11 @@ static void inherit_prom_mappings(void) /* Spitfire Errata #32 workaround */ + /* NOTE: Using plain zero for the context value is + * correct here, we are not using the Linux trap + * tables yet so we should not use the special + * UltraSPARC-III+ page size encodings yet. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -617,6 +603,9 @@ static void __flush_nucleus_vptes(void) unsigned long tag; /* Spitfire Errata #32 workaround */ + /* NOTE: Always runs on spitfire, so no cheetah+ + * page size encodings. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -783,6 +772,9 @@ void inherit_locked_prom_mappings(int save_p) unsigned long data; /* Spitfire Errata #32 workaround */ + /* NOTE: Always runs on spitfire, so no cheetah+ + * page size encodings. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -794,6 +786,9 @@ void inherit_locked_prom_mappings(int save_p) unsigned long tag; /* Spitfire Errata #32 workaround */ + /* NOTE: Always runs on spitfire, so no + * cheetah+ page size encodings. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -821,6 +816,9 @@ void inherit_locked_prom_mappings(int save_p) unsigned long data; /* Spitfire Errata #32 workaround */ + /* NOTE: Always runs on spitfire, so no + * cheetah+ page size encodings. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -832,6 +830,9 @@ void inherit_locked_prom_mappings(int save_p) unsigned long tag; /* Spitfire Errata #32 workaround */ + /* NOTE: Always runs on spitfire, so no + * cheetah+ page size encodings. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -947,6 +948,7 @@ void prom_reload_locked(void) } } +#ifdef DCACHE_ALIASING_POSSIBLE void __flush_dcache_range(unsigned long start, unsigned long end) { unsigned long va; @@ -970,6 +972,7 @@ void __flush_dcache_range(unsigned long start, unsigned long end) "i" (ASI_DCACHE_INVALIDATE)); } } +#endif /* DCACHE_ALIASING_POSSIBLE */ /* If not locked, zap it. */ void __flush_tlb_all(void) @@ -985,6 +988,9 @@ void __flush_tlb_all(void) if (tlb_type == spitfire) { for (i = 0; i < 64; i++) { /* Spitfire Errata #32 workaround */ + /* NOTE: Always runs on spitfire, so no + * cheetah+ page size encodings. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -1000,6 +1006,9 @@ void __flush_tlb_all(void) } /* Spitfire Errata #32 workaround */ + /* NOTE: Always runs on spitfire, so no + * cheetah+ page size encodings. + */ __asm__ __volatile__("stxa %0, [%1] %2\n\t" "flush %%g6" : /* No outputs */ @@ -1033,11 +1042,14 @@ void __flush_tlb_all(void) void get_new_mmu_context(struct mm_struct *mm) { unsigned long ctx, new_ctx; + unsigned long orig_pgsz_bits; + spin_lock(&ctx_alloc_lock); - ctx = CTX_HWBITS(tlb_context_cache + 1); - new_ctx = find_next_zero_bit(mmu_context_bmap, 1UL << CTX_VERSION_SHIFT, ctx); - if (new_ctx >= (1UL << CTX_VERSION_SHIFT)) { + orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); + ctx = (tlb_context_cache + 1) & CTX_NR_MASK; + new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); + if (new_ctx >= (1 << CTX_NR_BITS)) { new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); if (new_ctx >= ctx) { int i; @@ -1066,9 +1078,8 @@ void get_new_mmu_context(struct mm_struct *mm) new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); out: tlb_context_cache = new_ctx; + mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; spin_unlock(&ctx_alloc_lock); - - mm->context = new_ctx; } #ifndef CONFIG_SMP @@ -1087,7 +1098,7 @@ struct pgtable_cache_struct pgt_quicklists; * using the later address range, accesses with the first address * range will see the newly initialized data rather than the garbage. */ -#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */ +#ifdef DCACHE_ALIASING_POSSIBLE #define DC_ALIAS_SHIFT 1 #else #define DC_ALIAS_SHIFT 0 @@ -1111,7 +1122,7 @@ pte_t *__pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) unsigned long paddr; pte_t *pte; -#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */ +#ifdef DCACHE_ALIASING_POSSIBLE set_page_count(page, 1); ClearPageCompound(page); @@ -1129,7 +1140,7 @@ pte_t *__pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) to_free = (unsigned long *) paddr; } -#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */ +#ifdef DCACHE_ALIASING_POSSIBLE /* Now free the other one up, adjust cache size. */ preempt_disable(); *to_free = (unsigned long) pte_quicklist[color ^ 0x1]; @@ -1702,22 +1713,6 @@ void __init mem_init(void) initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin)); initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT; -#ifndef CONFIG_SMP - { - /* Put empty_pg_dir on pgd_quicklist */ - extern pgd_t empty_pg_dir[1024]; - unsigned long addr = (unsigned long)empty_pg_dir; - unsigned long alias_base = kern_base + PAGE_OFFSET - - (long)(KERNBASE); - - memset(empty_pg_dir, 0, sizeof(empty_pg_dir)); - addr += alias_base; - free_pgd_fast((pgd_t *)addr); - num_physpages++; - totalram_pages++; - } -#endif - printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n", nr_free_pages() << (PAGE_SHIFT-10), codepages << (PAGE_SHIFT-10), diff --git a/arch/sparc64/mm/tlb.c b/arch/sparc64/mm/tlb.c index 6255d6ef48eb0..90ca99d0b89cd 100644 --- a/arch/sparc64/mm/tlb.c +++ b/arch/sparc64/mm/tlb.c @@ -26,15 +26,13 @@ void flush_tlb_pending(void) struct mmu_gather *mp = &__get_cpu_var(mmu_gathers); if (mp->tlb_nr) { - unsigned long context = mp->mm->context; - - if (CTX_VALID(context)) { + if (CTX_VALID(mp->mm->context)) { #ifdef CONFIG_SMP smp_flush_tlb_pending(mp->mm, mp->tlb_nr, &mp->vaddrs[0]); #else - __flush_tlb_pending(CTX_HWBITS(context), mp->tlb_nr, - &mp->vaddrs[0]); + __flush_tlb_pending(CTX_HWBITS(mp->mm->context), + mp->tlb_nr, &mp->vaddrs[0]); #endif } mp->tlb_nr = 0; @@ -73,6 +71,7 @@ void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t } no_cache_flush: + if (mp->tlb_frozen) return; @@ -101,11 +100,10 @@ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long if (mp->tlb_frozen) return; - /* Nobody should call us with start below VM hole and end above. - * See if it is really true. - */ - BUG_ON(s > e); + /* If start is greater than end, that is a real problem. */ + BUG_ON(start > end); + /* However, straddling the VA space hole is quite normal. */ s &= PMD_MASK; e = (e + PMD_SIZE - 1) & PMD_MASK; @@ -123,6 +121,22 @@ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long start = vpte_base + (s >> (PAGE_SHIFT - 3)); end = vpte_base + (e >> (PAGE_SHIFT - 3)); + + /* If the request straddles the VA space hole, we + * need to swap start and end. The reason this + * occurs is that "vpte_base" is the center of + * the linear page table mapping area. Thus, + * high addresses with the sign bit set map to + * addresses below vpte_base and non-sign bit + * addresses map to addresses above vpte_base. + */ + if (end < start) { + unsigned long tmp = start; + + start = end; + end = tmp; + } + while (start < end) { mp->vaddrs[nr] = start; mp->tlb_nr = ++nr; @@ -135,10 +149,3 @@ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start, unsigned long if (nr) flush_tlb_pending(); } - -unsigned long __ptrs_per_pmd(void) -{ - if (test_thread_flag(TIF_32BIT)) - return (1UL << (32 - (PAGE_SHIFT-3) - PAGE_SHIFT)); - return REAL_PTRS_PER_PMD; -} diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S index af8205edfbd0f..7a0934321010a 100644 --- a/arch/sparc64/mm/ultra.S +++ b/arch/sparc64/mm/ultra.S @@ -13,6 +13,7 @@ #include <asm/pil.h> #include <asm/head.h> #include <asm/thread_info.h> +#include <asm/cacheflush.h> /* Basically, most of the Spitfire vs. Cheetah madness * has to do with the fact that Cheetah does not support @@ -49,9 +50,9 @@ __flush_tlb_mm: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */ .globl __flush_tlb_pending __flush_tlb_pending: /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ - rdpr %pstate, %g5 + rdpr %pstate, %g7 sllx %o1, 3, %o1 - andn %g5, PSTATE_IE, %g2 + andn %g7, PSTATE_IE, %g2 wrpr %g2, %pstate mov SECONDARY_CONTEXT, %o4 ldxa [%o4] ASI_DMMU, %g2 @@ -70,7 +71,7 @@ __flush_tlb_pending: stxa %g2, [%o4] ASI_DMMU flush %g6 retl - wrpr %g5, 0x0, %pstate + wrpr %g7, 0x0, %pstate .align 32 .globl __flush_tlb_kernel_range @@ -114,64 +115,27 @@ __spitfire_flush_tlb_mm_slow: .align 32 .globl __flush_icache_page __flush_icache_page: /* %o0 = phys_page */ - sethi %hi(1 << 13), %o2 ! IC_set bit - mov 1, %g1 - srlx %o0, 5, %o0 - clr %o1 ! IC_addr - sllx %g1, 36, %g1 - ldda [%o1] ASI_IC_TAG, %o4 - sub %g1, 1, %g2 - or %o0, %g1, %o0 ! VALID+phys-addr comparitor - - sllx %g2, 1, %g2 - andn %g2, ITAG_MASK, %g2 ! IC_tag mask - nop - nop - nop - nop - nop - nop - -1: addx %g0, %g0, %g0 - ldda [%o1 + %o2] ASI_IC_TAG, %g4 - addx %g0, %g0, %g0 - and %o5, %g2, %g3 - cmp %g3, %o0 - add %o1, 0x20, %o1 - ldda [%o1] ASI_IC_TAG, %o4 - be,pn %xcc, iflush1 - -2: nop - and %g5, %g2, %g5 - cmp %g5, %o0 - be,pn %xcc, iflush2 -3: cmp %o1, %o2 - bne,pt %xcc, 1b - addx %g0, %g0, %g0 - nop - + membar #StoreStore + srlx %o0, PAGE_SHIFT, %o0 + sethi %uhi(PAGE_OFFSET), %g1 + sllx %o0, PAGE_SHIFT, %o0 + sethi %hi(PAGE_SIZE), %g2 + sllx %g1, 32, %g1 + add %o0, %g1, %o0 +1: subcc %g2, 32, %g2 + bne,pt %icc, 1b + flush %o0 + %g2 retl - ldx [%g6 + TI_TASK], %g4 + nop -iflush1:sub %o1, 0x20, %g3 - stxa %g0, [%g3] ASI_IC_TAG - flush %g6 - ba,a,pt %xcc, 2b -iflush2:sub %o1, 0x20, %g3 - stxa %g0, [%o1 + %o2] ASI_IC_TAG - flush %g6 - ba,a,pt %xcc, 3b +#ifdef DCACHE_ALIASING_POSSIBLE -#if (PAGE_SHIFT == 13) -#define DTAG_MASK 0x3 -#elif (PAGE_SHIFT == 16) -#define DTAG_MASK 0x1f -#elif (PAGE_SHIFT == 19) -#define DTAG_MASK 0xff -#elif (PAGE_SHIFT == 22) -#define DTAG_MASK 0x3ff +#if (PAGE_SHIFT != 13) +#error only page shift of 13 is supported by dcache flush #endif +#define DTAG_MASK 0x3 + .align 64 .globl __flush_dcache_page __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */ @@ -228,6 +192,7 @@ dflush4:stxa %g0, [%o4] ASI_DCACHE_TAG membar #Sync ba,pt %xcc, 2b nop +#endif /* DCACHE_ALIASING_POSSIBLE */ .align 32 __prefill_dtlb: @@ -258,10 +223,18 @@ __update_mmu_cache: /* %o0=hw_context, %o1=address, %o2=pte, %o3=fault_code */ or %o5, %o0, %o5 ba,a,pt %xcc, __prefill_itlb - /* Cheetah specific versions, patched at boot time. */ + /* Cheetah specific versions, patched at boot time. + * + * This writes of the PRIMARY_CONTEXT register in this file are + * safe even on Cheetah+ and later wrt. the page size fields. + * The nucleus page size fields do not matter because we make + * no data references, and these instructions execute out of a + * locked I-TLB entry sitting in the fully assosciative I-TLB. + * This sequence should also never trap. + */ __cheetah_flush_tlb_mm: /* 15 insns */ - rdpr %pstate, %g5 - andn %g5, PSTATE_IE, %g2 + rdpr %pstate, %g7 + andn %g7, PSTATE_IE, %g2 wrpr %g2, 0x0, %pstate wrpr %g0, 1, %tl mov PRIMARY_CONTEXT, %o2 @@ -274,13 +247,13 @@ __cheetah_flush_tlb_mm: /* 15 insns */ flush %g6 wrpr %g0, 0, %tl retl - wrpr %g5, 0x0, %pstate + wrpr %g7, 0x0, %pstate __cheetah_flush_tlb_pending: /* 22 insns */ /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */ - rdpr %pstate, %g5 + rdpr %pstate, %g7 sllx %o1, 3, %o1 - andn %g5, PSTATE_IE, %g2 + andn %g7, PSTATE_IE, %g2 wrpr %g2, 0x0, %pstate wrpr %g0, 1, %tl mov PRIMARY_CONTEXT, %o4 @@ -299,8 +272,9 @@ __cheetah_flush_tlb_pending: /* 22 insns */ flush %g6 wrpr %g0, 0, %tl retl - wrpr %g5, 0x0, %pstate + wrpr %g7, 0x0, %pstate +#ifdef DCACHE_ALIASING_POSSIBLE flush_dcpage_cheetah: /* 11 insns */ sethi %uhi(PAGE_OFFSET), %g1 sllx %g1, 32, %g1 @@ -313,6 +287,7 @@ flush_dcpage_cheetah: /* 11 insns */ nop retl /* I-cache flush never needed on Cheetah, see callers. */ nop +#endif /* DCACHE_ALIASING_POSSIBLE */ cheetah_patch_one: 1: lduw [%o1], %g1 @@ -343,12 +318,14 @@ cheetah_patch_cachetlbops: call cheetah_patch_one mov 22, %o2 +#ifdef DCACHE_ALIASING_POSSIBLE sethi %hi(__flush_dcache_page), %o0 or %o0, %lo(__flush_dcache_page), %o0 sethi %hi(flush_dcpage_cheetah), %o1 or %o1, %lo(flush_dcpage_cheetah), %o1 call cheetah_patch_one mov 11, %o2 +#endif /* DCACHE_ALIASING_POSSIBLE */ ret restore @@ -464,6 +441,7 @@ xcall_report_regs: b rtrap_xcall ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 +#ifdef DCACHE_ALIASING_POSSIBLE .align 32 .globl xcall_flush_dcache_page_cheetah xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */ @@ -475,12 +453,13 @@ xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */ nop retry nop +#endif /* DCACHE_ALIASING_POSSIBLE */ .globl xcall_flush_dcache_page_spitfire xcall_flush_dcache_page_spitfire: /* %g1 == physical page address %g7 == kernel page virtual address %g5 == (page->mapping != NULL) */ -#if (L1DCACHE_SIZE > PAGE_SIZE) +#ifdef DCACHE_ALIASING_POSSIBLE srlx %g1, (13 - 2), %g1 ! Form tag comparitor sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K sub %g3, (1 << 5), %g3 ! D$ linesize == 32 @@ -499,7 +478,7 @@ xcall_flush_dcache_page_spitfire: /* %g1 == physical page address sub %g3, (1 << 5), %g3 brz,pn %g5, 2f -#endif /* L1DCACHE_SIZE > PAGE_SIZE */ +#endif /* DCACHE_ALIASING_POSSIBLE */ sethi %hi(PAGE_SIZE), %g3 1: flush %g7 diff --git a/arch/sparc64/prom/map.S b/arch/sparc64/prom/map.S index 509f7b4abef1e..21b3f9c99ea77 100644 --- a/arch/sparc64/prom/map.S +++ b/arch/sparc64/prom/map.S @@ -32,6 +32,7 @@ prom_remap: /* %o0 = physpage, %o1 = virtpage, %o2 = mmu_ihandle */ ldx [%g2 + 0x08], %l0 ! prom_cif_handler mov %g6, %i3 mov %g4, %i4 + mov %g5, %i5 flushw sethi %hi(prom_remap - call_method), %g7 @@ -62,6 +63,7 @@ prom_remap: /* %o0 = physpage, %o1 = virtpage, %o2 = mmu_ihandle */ /* Restore hard-coded globals. */ mov %i3, %g6 mov %i4, %g4 + mov %i5, %g5 /* Wheee.... we are done. */ ret diff --git a/arch/sparc64/prom/p1275.c b/arch/sparc64/prom/p1275.c index 9eab4421e1e4c..59fe38bba39e8 100644 --- a/arch/sparc64/prom/p1275.c +++ b/arch/sparc64/prom/p1275.c @@ -30,6 +30,16 @@ extern void prom_world(int); extern void prom_cif_interface(void); extern void prom_cif_callback(void); +static inline unsigned long spitfire_get_primary_context(void) +{ + unsigned long ctx; + + __asm__ __volatile__("ldxa [%1] %2, %0" + : "=r" (ctx) + : "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); + return ctx; +} + /* * This provides SMP safety on the p1275buf. prom_callback() drops this lock * to allow recursuve acquisition. @@ -43,14 +53,9 @@ long p1275_cmd (char *service, long fmt, ...) int nargs, nrets, i; va_list list; long attrs, x; - long ctx = 0; p = p1275buf.prom_buffer; - ctx = spitfire_get_primary_context (); - if (ctx) { - flushw_user (); - spitfire_set_primary_context (0); - } + BUG_ON((spitfire_get_primary_context() & CTX_NR_MASK) != 0); spin_lock_irqsave(&prom_entry_lock, flags); @@ -146,9 +151,6 @@ long p1275_cmd (char *service, long fmt, ...) spin_unlock_irqrestore(&prom_entry_lock, flags); - if (ctx) - spitfire_set_primary_context (ctx); - return x; } diff --git a/arch/x86_64/kernel/pci-gart.c b/arch/x86_64/kernel/pci-gart.c index 49d5d5f137fa4..57f35c68aa34d 100644 --- a/arch/x86_64/kernel/pci-gart.c +++ b/arch/x86_64/kernel/pci-gart.c @@ -193,7 +193,7 @@ static void *dma_alloc_pages(struct device *dev, unsigned gfp, unsigned order) int node; if (dev->bus == &pci_bus_type) { cpumask_t mask; - mask = pcibus_to_cpumask(to_pci_dev(dev)->bus->number); + mask = pcibus_to_cpumask(to_pci_dev(dev)->bus); node = cpu_to_node(first_cpu(mask)); } else node = numa_node_id(); diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c index 440416026504e..82a1103b24130 100644 --- a/drivers/ide/pci/serverworks.c +++ b/drivers/ide/pci/serverworks.c @@ -341,7 +341,7 @@ static int svwks_ide_dma_end (ide_drive_t *drive) return __ide_dma_end(drive); } -static unsigned int __init init_chipset_svwks (struct pci_dev *dev, const char *name) +static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name) { unsigned int reg; u8 btr; @@ -508,7 +508,7 @@ static unsigned int __init ata66_svwks (ide_hwif_t *hwif) } #undef CAN_SW_DMA -static void __init init_hwif_svwks (ide_hwif_t *hwif) +static void __devinit init_hwif_svwks (ide_hwif_t *hwif) { u8 dma_stat = 0; @@ -556,7 +556,7 @@ static void __init init_hwif_svwks (ide_hwif_t *hwif) /* * We allow the BM-DMA driver to only work on enabled interfaces. */ -static void __init init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase) +static void __devinit init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase) { struct pci_dev *dev = hwif->pci_dev; @@ -568,7 +568,7 @@ static void __init init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase) ide_setup_dma(hwif, dmabase, 8); } -static int __init init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d) +static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d) { return ide_setup_pci_device(dev, d); } diff --git a/drivers/mtd/maps/pci.c b/drivers/mtd/maps/pci.c index 3dee11edede7b..08b60bdc53812 100644 --- a/drivers/mtd/maps/pci.c +++ b/drivers/mtd/maps/pci.c @@ -205,9 +205,9 @@ intel_dc21285_init(struct pci_dev *dev, struct map_pci_info *map) * or simply enabling it? */ if (!(pci_resource_flags(dev, PCI_ROM_RESOURCE) & - PCI_ROM_ADDRESS_ENABLE)) { + IORESOURCE_ROM_ENABLE)) { u32 val; - pci_resource_flags(dev, PCI_ROM_RESOURCE) |= PCI_ROM_ADDRESS_ENABLE; + pci_resource_flags(dev, PCI_ROM_RESOURCE) |= IORESOURCE_ROM_ENABLE; pci_read_config_dword(dev, PCI_ROM_ADDRESS, &val); val |= PCI_ROM_ADDRESS_ENABLE; pci_write_config_dword(dev, PCI_ROM_ADDRESS, val); @@ -241,7 +241,7 @@ intel_dc21285_exit(struct pci_dev *dev, struct map_pci_info *map) /* * We need to undo the PCI BAR2/PCI ROM BAR address alteration. */ - pci_resource_flags(dev, PCI_ROM_RESOURCE) &= ~PCI_ROM_ADDRESS_ENABLE; + pci_resource_flags(dev, PCI_ROM_RESOURCE) &= ~IORESOURCE_ROM_ENABLE; pci_read_config_dword(dev, PCI_ROM_ADDRESS, &val); val &= ~PCI_ROM_ADDRESS_ENABLE; pci_write_config_dword(dev, PCI_ROM_ADDRESS, val); diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 812c4274d7cdd..7f31991772ea4 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -47,3 +47,13 @@ config PCI_NAMES When in doubt, say Y. +config PCI_DEBUG + bool "PCI Debugging" + depends on PCI && DEBUG_KERNEL + help + Say Y here if you want the PCI core to produce a bunch of debug + messages to the system log. Select this if you are having a + problem with PCI support and want to see more of what is going on. + + When in doubt, say N. + diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 92b11de780e38..7dea494c0d7bb 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -41,6 +41,10 @@ ifndef CONFIG_X86 obj-y += syscall.o endif +ifeq ($(CONFIG_PCI_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif + hostprogs-y := gen-devlist # Dependencies on generated files need to be listed explicitly diff --git a/drivers/pci/gen-devlist.c b/drivers/pci/gen-devlist.c index 372e2102581d8..8abfc499fdefc 100644 --- a/drivers/pci/gen-devlist.c +++ b/drivers/pci/gen-devlist.c @@ -7,7 +7,7 @@ #include <stdio.h> #include <string.h> -#define MAX_NAME_SIZE 89 +#define MAX_NAME_SIZE 200 static void pq(FILE *f, const char *c, int len) diff --git a/drivers/pci/hotplug.c b/drivers/pci/hotplug.c index 42b23049a7fcd..d471b3ea5d12f 100644 --- a/drivers/pci/hotplug.c +++ b/drivers/pci/hotplug.c @@ -1,15 +1,8 @@ +#include <linux/kernel.h> #include <linux/pci.h> #include <linux/module.h> #include "pci.h" -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - int pci_hotplug (struct device *dev, char **envp, int num_envp, char *buffer, int buffer_size) { @@ -71,7 +64,8 @@ static int pci_visit_bus (struct pci_visit * fn, struct pci_bus_wrapped *wrapped struct pci_dev_wrapped wrapped_dev; int result = 0; - DBG("scanning bus %02x\n", wrapped_bus->bus->number); + pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(wrapped_bus->bus), + wrapped_bus->bus->number); if (fn->pre_visit_pci_bus) { result = fn->pre_visit_pci_bus(wrapped_bus, wrapped_parent); @@ -106,8 +100,7 @@ static int pci_visit_bridge (struct pci_visit * fn, struct pci_bus_wrapped wrapped_bus; int result = 0; - DBG("scanning bridge %02x, %02x\n", PCI_SLOT(wrapped_dev->dev->devfn), - PCI_FUNC(wrapped_dev->dev->devfn)); + pr_debug("PCI: Scanning bridge %s\n", pci_name(wrapped_dev->dev)); if (fn->visit_pci_dev) { result = fn->visit_pci_dev(wrapped_dev, wrapped_parent); @@ -153,8 +146,7 @@ int pci_visit_dev(struct pci_visit *fn, struct pci_dev_wrapped *wrapped_dev, return result; break; default: - DBG("scanning device %02x, %02x\n", - PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + pr_debug("PCI: Scanning device %s\n", pci_name(dev)); if (fn->visit_pci_dev) { result = fn->visit_pci_dev (wrapped_dev, wrapped_parent); @@ -169,4 +161,3 @@ int pci_visit_dev(struct pci_visit *fn, struct pci_dev_wrapped *wrapped_dev, return result; } EXPORT_SYMBOL(pci_visit_dev); - diff --git a/drivers/pci/hotplug/cpqphp_core.c b/drivers/pci/hotplug/cpqphp_core.c index 24e0699ab0aad..afbccfa5217d7 100644 --- a/drivers/pci/hotplug/cpqphp_core.c +++ b/drivers/pci/hotplug/cpqphp_core.c @@ -577,11 +577,11 @@ cpqhp_set_attention_status(struct controller *ctrl, struct pci_func *func, { u8 hp_slot; - hp_slot = func->device - ctrl->slot_device_offset; - if (func == NULL) return(1); + hp_slot = func->device - ctrl->slot_device_offset; + // Wait for exclusive access to hardware down(&ctrl->crit_sect); diff --git a/drivers/pci/hotplug/ibmphp_pci.c b/drivers/pci/hotplug/ibmphp_pci.c index 90ef5c086844f..2335fac65fb4e 100644 --- a/drivers/pci/hotplug/ibmphp_pci.c +++ b/drivers/pci/hotplug/ibmphp_pci.c @@ -1308,43 +1308,37 @@ static int unconfigure_boot_device (u8 busno, u8 device, u8 function) /* ????????? DO WE NEED TO WRITE ANYTHING INTO THE PCI CONFIG SPACE BACK ?????????? */ } else { /* This is Memory */ + start_address &= PCI_BASE_ADDRESS_MEM_MASK; if (start_address & PCI_BASE_ADDRESS_MEM_PREFETCH) { /* pfmem */ - start_address &= PCI_BASE_ADDRESS_MEM_MASK; debug ("start address of pfmem is %x\n", start_address); if (ibmphp_find_resource (bus, start_address, &pfmem, PFMEM) < 0) { err ("cannot find corresponding PFMEM resource to remove\n"); return -EIO; } - if (pfmem) + if (pfmem) { debug ("pfmem->start = %x\n", pfmem->start); - ibmphp_remove_resource (pfmem); - - if (tmp_address & PCI_BASE_ADDRESS_MEM_TYPE_64) { - /* takes up another dword */ - count += 1; + ibmphp_remove_resource(pfmem); } - } else { /* regular memory */ - start_address &= PCI_BASE_ADDRESS_MEM_MASK; debug ("start address of mem is %x\n", start_address); if (ibmphp_find_resource (bus, start_address, &mem, MEM) < 0) { err ("cannot find corresponding MEM resource to remove\n"); return -EIO; } - if (mem) + if (mem) { debug ("mem->start = %x\n", mem->start); - ibmphp_remove_resource (mem); - - if (tmp_address & PCI_BASE_ADDRESS_MEM_TYPE_64) { - /* takes up another dword */ - count += 1; + ibmphp_remove_resource(mem); } } + if (tmp_address & PCI_BASE_ADDRESS_MEM_TYPE_64) { + /* takes up another dword */ + count += 1; + } } /* end of mem */ } /* end of for */ @@ -1428,40 +1422,34 @@ static int unconfigure_boot_bridge (u8 busno, u8 device, u8 function) /* ????????? DO WE NEED TO WRITE ANYTHING INTO THE PCI CONFIG SPACE BACK ?????????? */ } else { /* This is Memory */ + start_address &= PCI_BASE_ADDRESS_MEM_MASK; if (start_address & PCI_BASE_ADDRESS_MEM_PREFETCH) { /* pfmem */ - start_address &= PCI_BASE_ADDRESS_MEM_MASK; if (ibmphp_find_resource (bus, start_address, &pfmem, PFMEM) < 0) { err ("cannot find corresponding PFMEM resource to remove\n"); return -EINVAL; } - if (pfmem) + if (pfmem) { debug ("pfmem->start = %x\n", pfmem->start); - ibmphp_remove_resource (pfmem); - - if (tmp_address & PCI_BASE_ADDRESS_MEM_TYPE_64) { - /* takes up another dword */ - count += 1; + ibmphp_remove_resource(pfmem); } - } else { /* regular memory */ - start_address &= PCI_BASE_ADDRESS_MEM_MASK; if (ibmphp_find_resource (bus, start_address, &mem, MEM) < 0) { err ("cannot find corresponding MEM resource to remove\n"); return -EINVAL; } - if (mem) + if (mem) { debug ("mem->start = %x\n", mem->start); - ibmphp_remove_resource (mem); - - if (tmp_address & PCI_BASE_ADDRESS_MEM_TYPE_64) { - /* takes up another dword */ - count += 1; + ibmphp_remove_resource(mem); } } + if (tmp_address & PCI_BASE_ADDRESS_MEM_TYPE_64) { + /* takes up another dword */ + count += 1; + } } /* end of mem */ } /* end of for */ debug ("%s - exiting, returning success\n", __FUNCTION__); diff --git a/drivers/pci/hotplug/pci_hotplug.h b/drivers/pci/hotplug/pci_hotplug.h index 2bae8aa587464..57ace325168df 100644 --- a/drivers/pci/hotplug/pci_hotplug.h +++ b/drivers/pci/hotplug/pci_hotplug.h @@ -152,6 +152,8 @@ struct hotplug_slot_info { * @ops: pointer to the &struct hotplug_slot_ops to be used for this slot * @info: pointer to the &struct hotplug_slot_info for the inital values for * this slot. + * @release: called during pci_hp_deregister to free memory allocated in a + * hotplug_slot structure. * @private: used by the hotplug pci controller driver to store whatever it * needs. */ diff --git a/drivers/pci/hotplug/pci_hotplug_core.c b/drivers/pci/hotplug/pci_hotplug_core.c index 906fd9b3fbd39..c802f6270b895 100644 --- a/drivers/pci/hotplug/pci_hotplug_core.c +++ b/drivers/pci/hotplug/pci_hotplug_core.c @@ -567,6 +567,11 @@ int pci_hp_register (struct hotplug_slot *slot) return -ENODEV; if ((slot->info == NULL) || (slot->ops == NULL)) return -EINVAL; + if (slot->release == NULL) { + dbg("Why are you trying to register a hotplug slot" + "without a proper release function?\n"); + return -EINVAL; + } kobject_set_name(&slot->kobj, "%s", slot->name); kobj_set_kset_s(slot, pci_hotplug_slots_subsys); diff --git a/drivers/pci/hotplug/rpaphp.h b/drivers/pci/hotplug/rpaphp.h index df9575ef5aa55..81746e6e0e0fe 100644 --- a/drivers/pci/hotplug/rpaphp.h +++ b/drivers/pci/hotplug/rpaphp.h @@ -94,7 +94,7 @@ struct slot { /* dn has phb info */ struct pci_dev *bridge; /* slot's pci_dev in pci_devices */ union { - struct list_head pci_funcs; /* pci_devs in PCI slot */ + struct list_head *pci_devs; /* pci_devs in PCI slot */ struct vio_dev *vio_dev; /* vio_dev in VIO slot */ } dev; struct hotplug_slot *hotplug_slot; diff --git a/drivers/pci/hotplug/rpaphp_pci.c b/drivers/pci/hotplug/rpaphp_pci.c index a96b4af16f245..d8305a935aab1 100644 --- a/drivers/pci/hotplug/rpaphp_pci.c +++ b/drivers/pci/hotplug/rpaphp_pci.c @@ -130,11 +130,11 @@ int rpaphp_get_pci_adapter_status(struct slot *slot, int is_init, u8 * value) *value = EMPTY; } else if (state == PRESENT) { - if (!is_init) + if (!is_init) { /* at run-time slot->state can be changed by */ /* config/unconfig adapter */ *value = slot->state; - else { + } else { child_dn = slot->dn->child; if (child_dn) child_dev = rpaphp_find_pci_dev(child_dn); @@ -263,56 +263,17 @@ static void enable_eeh(struct device_node *dn) } -#ifdef DEBUG static void print_slot_pci_funcs(struct slot *slot) { - struct list_head *l; + struct pci_dev *dev; if (slot->dev_type == PCI_DEV) { - printk("pci_funcs of slot[%s]\n", slot->name); - if (list_empty(&slot->dev.pci_funcs)) - printk(" pci_funcs is EMPTY\n"); - - list_for_each (l, &slot->dev.pci_funcs) { - struct rpaphp_pci_func *func = - list_entry(l, struct rpaphp_pci_func, sibling); - printk(" FOUND dev=%s\n", pci_name(func->pci_dev)); - } + dbg("%s: pci_devs of slot[%s]\n", __FUNCTION__, slot->name); + list_for_each_entry (dev, slot->dev.pci_devs, bus_list) + dbg("\t%s\n", pci_name(dev)); } return; } -#else -static void print_slot_pci_funcs(struct slot *slot) -{ - return; -} -#endif - -static int init_slot_pci_funcs(struct slot *slot) -{ - struct device_node *child; - - for (child = slot->dn->child; child != NULL; child = child->sibling) { - struct pci_dev *pdev = rpaphp_find_pci_dev(child); - - if (pdev) { - struct rpaphp_pci_func *func; - func = kmalloc(sizeof(struct rpaphp_pci_func), GFP_KERNEL); - if (!func) - return -ENOMEM; - memset(func, 0, sizeof(struct rpaphp_pci_func)); - INIT_LIST_HEAD(&func->sibling); - func->pci_dev = pdev; - list_add_tail(&func->sibling, &slot->dev.pci_funcs); - print_slot_pci_funcs(slot); - } else { - err("%s: dn=%s has no pci_dev\n", - __FUNCTION__, child->full_name); - return -EIO; - } - } - return 0; -} static int rpaphp_config_pci_adapter(struct slot *slot) { @@ -335,13 +296,8 @@ static int rpaphp_config_pci_adapter(struct slot *slot) err("%s: can't find any devices.\n", __FUNCTION__); goto exit; } - /* associate corresponding pci_dev */ - rc = init_slot_pci_funcs(slot); - if (rc) - goto exit; print_slot_pci_funcs(slot); - if (!list_empty(&slot->dev.pci_funcs)) - rc = 0; + rc = 0; } else { /* slot is not enabled */ err("slot doesn't have pci_dev structure\n"); @@ -371,34 +327,16 @@ static void rpaphp_eeh_remove_bus_device(struct pci_dev *dev) int rpaphp_unconfig_pci_adapter(struct slot *slot) { + struct pci_dev *dev; int retval = 0; - struct list_head *ln, *tmp; - dbg("Entry %s: slot[%s]\n", __FUNCTION__, slot->name); - if (list_empty(&slot->dev.pci_funcs)) { - err("%s: slot[%s] doesn't have any devices.\n", __FUNCTION__, - slot->name); + list_for_each_entry(dev, slot->dev.pci_devs, bus_list) + rpaphp_eeh_remove_bus_device(dev); - retval = -EINVAL; - goto exit; - } - /* remove the devices from the pci core */ - list_for_each_safe (ln, tmp, &slot->dev.pci_funcs) { - struct rpaphp_pci_func *func; - - func = list_entry(ln, struct rpaphp_pci_func, sibling); - if (func->pci_dev) { - pci_remove_bus_device(func->pci_dev); - rpaphp_eeh_remove_bus_device(func->pci_dev); - } - kfree(func); - } - INIT_LIST_HEAD(&slot->dev.pci_funcs); + pci_remove_behind_bridge(slot->bridge); slot->state = NOT_CONFIGURED; info("%s: devices in slot[%s] unconfigured.\n", __FUNCTION__, slot->name); -exit: - dbg("Exit %s, rc=0x%x\n", __FUNCTION__, retval); return retval; } @@ -444,6 +382,7 @@ static int set_phb_slot_name(struct slot *slot) static int setup_pci_slot(struct slot *slot) { + struct pci_bus *bus; int rc; if (slot->type == PHB) { @@ -460,6 +399,12 @@ static int setup_pci_slot(struct slot *slot) __FUNCTION__, slot->name); goto exit_rc; } + + bus = slot->bridge->subordinate; + if (!bus) + goto exit_rc; + slot->dev.pci_devs = &bus->devices; + dbg("%s set slot->name to %s\n", __FUNCTION__, pci_name(slot->bridge)); strcpy(slot->name, pci_name(slot->bridge)); @@ -484,22 +429,15 @@ static int setup_pci_slot(struct slot *slot) err("%s: CONFIG pci adapter failed\n", __FUNCTION__); goto exit_rc; } - } else if (slot->hotplug_slot->info->adapter_status == CONFIGURED) { - if (init_slot_pci_funcs(slot)) { - err("%s: init_slot_pci_funcs failed\n", __FUNCTION__); - goto exit_rc; - } - } else { + } else if (slot->hotplug_slot->info->adapter_status != CONFIGURED) { err("%s: slot[%s]'s adapter_status is NOT_VALID.\n", __FUNCTION__, slot->name); goto exit_rc; } - print_slot_pci_funcs(slot); - if (!list_empty(&slot->dev.pci_funcs)) { + if (!list_empty(slot->dev.pci_devs)) { slot->state = CONFIGURED; - } else { /* DLPAR add as opposed to * boot time */ @@ -521,7 +459,6 @@ int register_pci_slot(struct slot *slot) slot->removable = 0; else slot->removable = 1; - INIT_LIST_HEAD(&slot->dev.pci_funcs); if (setup_pci_hotplug_slot_info(slot)) goto exit_rc; if (setup_pci_slot(slot)) diff --git a/drivers/pci/hotplug/rpaphp_slot.c b/drivers/pci/hotplug/rpaphp_slot.c index 5c58fd099bcf0..ff2cbf0652d83 100644 --- a/drivers/pci/hotplug/rpaphp_slot.c +++ b/drivers/pci/hotplug/rpaphp_slot.c @@ -98,17 +98,6 @@ static void rpaphp_release_slot(struct hotplug_slot *hotplug_slot) void dealloc_slot_struct(struct slot *slot) { - struct list_head *ln, *n; - - if (slot->dev_type == PCI_DEV) { - list_for_each_safe (ln, n, &slot->dev.pci_funcs) { - struct rpaphp_pci_func *func; - - func = list_entry(ln, struct rpaphp_pci_func, sibling); - kfree(func); - } - } - kfree(slot->hotplug_slot->info); kfree(slot->hotplug_slot->name); kfree(slot->hotplug_slot); diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 5425e0f77d860..22ecd3b058be1 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -703,12 +703,14 @@ static int msix_capability_init(struct pci_dev *dev, **/ int pci_enable_msi(struct pci_dev* dev) { - int pos, temp = dev->irq, status = -EINVAL; + int pos, temp, status = -EINVAL; u16 control; if (!pci_msi_enable || !dev) return status; + temp = dev->irq; + if ((status = msi_init()) < 0) return status; diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index 76fe2db404dff..37b7961efc44a 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -49,13 +49,6 @@ pci_device_probe_dynamic(struct pci_driver *drv, struct pci_dev *pci_dev) return error; } -static inline void -dynid_init(struct dynid *dynid) -{ - memset(dynid, 0, sizeof(*dynid)); - INIT_LIST_HEAD(&dynid->node); -} - /** * store_new_id * @@ -82,8 +75,9 @@ store_new_id(struct device_driver *driver, const char *buf, size_t count) dynid = kmalloc(sizeof(*dynid), GFP_KERNEL); if (!dynid) return -ENOMEM; - dynid_init(dynid); + memset(dynid, 0, sizeof(*dynid)); + INIT_LIST_HEAD(&dynid->node); dynid->id.vendor = vendor; dynid->id.device = device; dynid->id.subvendor = subvendor; @@ -167,7 +161,6 @@ static inline int pci_device_probe_dynamic(struct pci_driver *drv, struct pci_de { return -ENODEV; } -static inline void dynid_init(struct dynid *dynid) {} static inline void pci_init_dynids(struct pci_dynids *dynids) {} static inline void pci_free_dynids(struct pci_driver *drv) {} static inline int pci_create_newid_file(struct pci_driver *drv) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index eb8cf2b12f3e6..d57ae71d32b1d 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -46,7 +46,7 @@ pci_config_attr(irq, "%u\n"); static ssize_t local_cpus_show(struct device *dev, char *buf) { - cpumask_t mask = pcibus_to_cpumask(to_pci_dev(dev)->bus->number); + cpumask_t mask = pcibus_to_cpumask(to_pci_dev(dev)->bus); int len = cpumask_scnprintf(buf, PAGE_SIZE-2, mask); strcat(buf,"\n"); return 1+len; @@ -481,7 +481,7 @@ static int __init pci_sysfs_init(void) struct pci_dev *pdev = NULL; sysfs_initialized = 1; - while ((pdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) + for_each_pci_dev(pdev) pci_create_sysfs_dev_files(pdev); return 0; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index fb2b64b1f827c..bfbff83352688 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -9,6 +9,7 @@ * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> */ +#include <linux/kernel.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/pci.h> @@ -16,13 +17,6 @@ #include <linux/spinlock.h> #include <asm/dma.h> /* isa_dma_bridge_buggy */ -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif /** * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children @@ -635,7 +629,7 @@ pci_set_master(struct pci_dev *dev) pci_read_config_word(dev, PCI_COMMAND, &cmd); if (! (cmd & PCI_COMMAND_MASTER)) { - DBG("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); + pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); cmd |= PCI_COMMAND_MASTER; pci_write_config_word(dev, PCI_COMMAND, cmd); } @@ -713,7 +707,7 @@ pci_set_mwi(struct pci_dev *dev) pci_read_config_word(dev, PCI_COMMAND, &cmd); if (! (cmd & PCI_COMMAND_INVALIDATE)) { - DBG("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); + pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); cmd |= PCI_COMMAND_INVALIDATE; pci_write_config_word(dev, PCI_COMMAND, cmd); } diff --git a/drivers/pci/pci.ids b/drivers/pci/pci.ids index 6007a75900541..93481b41b613e 100644 --- a/drivers/pci/pci.ids +++ b/drivers/pci/pci.ids @@ -7,7 +7,7 @@ # so if you have anything to contribute, please visit the home page or # send a diff -u against the most recent pci.ids to pci-ids@ucw.cz. # -# Partial sync-up to daily snapshot on Tue 2005-02-08 11:00:09 +# Daily snapshot on Tue 2005-03-08 10:11:48 # # Vendors, devices and subsystems. Please keep sorted. @@ -47,6 +47,7 @@ 0357 TTTech AG 000a TTP-Monitoring Card V2.0 0432 SCM Microsystems, Inc. + 0001 Pluto2 DVB-T Receiver for PCMCIA [EasyWatch MobilSet] 05e3 CyberDoor 0701 CBD516 0675 Dynalink @@ -225,6 +226,7 @@ 1028 0123 PowerEdge 2600 1028 014a PowerEdge 1750 1028 016c PowerEdge 1850 MPT Fusion SCSI/RAID (Perc 4) + 1028 0183 PowerEdge 1800 1028 1010 LSI U320 SCSI Controller 0031 53c1030ZC PCI-X Fusion-MPT Dual Ultra320 SCSI 0032 53c1035 PCI-X Fusion-MPT Dual Ultra320 SCSI @@ -338,6 +340,8 @@ 4152 RV350 AR [Radeon 9600] 1002 0002 Radeon 9600XT 1043 c002 Radeon 9600 XT TVD + 174b 7c29 Sapphire Radeon 9600XT + 1787 4002 Radeon 9600 XT 4153 RV350 AS [Radeon 9600 AS] 4154 RV350 AT [Fire GL T2] 4155 RV350 AU [Fire GL T2] @@ -366,6 +370,8 @@ 4172 RV350 AR [Radeon 9600] (Secondary) 1002 0003 Radeon 9600XT (Secondary) 1043 c003 A9600XT (Secondary) + 174b 7c28 Sapphire Radeon 9600XT (Secondary) + 1787 4003 Radeon 9600 XT (Secondary) 4173 RV350 ?? [Radeon 9550] (Secondary) 4237 Radeon 7000 IGP 4242 R200 BB [Radeon All in Wonder 8500DV] @@ -380,11 +386,17 @@ 4345 EHCI USB Controller 4347 OHCI USB Controller #1 4348 OHCI USB Controller #2 + 4349 ATI Dual Channel Bus Master PCI IDE Controller 434d IXP AC'97 Modem -# Radeon 9100 IGP integrated 4353 ATI SMBus 4354 215CT [Mach64 CT] 4358 210888CX [Mach64 CX] + 4363 ATI SMBus + 436e ATI 436E Serial ATA Controller + 4372 ATI SMBus + 4376 Standard Dual Channel PCI IDE Controller ATI + 4379 ATI 4379 Serial ATA Controller + 437a ATI 437A Serial ATA Controller 4437 Radeon Mobility 7000 IGP 4554 210888ET [Mach64 ET] 4654 Mach64 VT @@ -505,6 +517,7 @@ 1002 0084 Xpert 98 AGP 2X (Mobility) 1014 0154 ThinkPad A20m 1028 00aa Latitude CPt + 1028 00bb Latitude CPx 4c4e Rage Mobility L AGP 2x 4c50 3D Rage LT Pro 1002 4c50 Rage LT Pro @@ -526,7 +539,7 @@ 4c5a Radeon Mobility M6 LZ 4c64 Radeon R250 Ld [Radeon Mobility 9000 M9] 4c65 Radeon R250 Le [Radeon Mobility 9000 M9] - 4c66 Radeon R250 Lf [Radeon Mobility 9000 M9] + 4c66 Radeon R250 Lf [FireGL 9000] 4c67 Radeon R250 Lg [Radeon Mobility 9000 M9] # Secondary chip to the Lf 4c6e Radeon R250 Ln [Radeon Mobility 9000 M9] [Secondary] @@ -548,7 +561,8 @@ # New PCI ID provided by ATI developer relations 4e50 RV350 [Mobility Radeon 9600 M10] 1025 005a TravelMate 290 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1734 1055 Amilo M1420W 4e51 M10 NQ [Radeon Mobility 9600] 4e52 RV350 [Mobility Radeon 9600 M10] @@ -567,6 +581,7 @@ # New PCI ID provided by ATI developer relations 4e69 Radeon R350 [Radeon 9800] (Secondary) 4e6a RV350 NJ [Radeon 9800 XT] (Secondary) + 1002 4e71 ATI Technologies Inc M10 NQ [Radeon Mobility 9600] 5041 Rage 128 PA/PRO 5042 Rage 128 PB/PRO AGP 2x 5043 Rage 128 PC/PRO AGP 4x @@ -739,6 +754,7 @@ 5835 RS300M AGP [Radeon Mobility 9100IGP] 5838 Radeon 9100 IGP AGP Bridge 5941 RV280 [Radeon 9200] (Secondary) + 1458 4019 Gigabyte Radeon 9200 174b 7c12 Sapphire Radeon 9200 # http://www.hightech.com.hk/html/9200.htm 17af 200d Excalibur Radeon 9200 @@ -747,6 +763,7 @@ 5960 RV280 [Radeon 9200 PRO] 5961 RV280 [Radeon 9200] 1002 2f72 All-in-Wonder 9200 Series + 1019 4c30 Radeon 9200 VIVO 12ab 5961 YUAN SMARTVGA Radeon 9200 1458 4018 Gigabyte Radeon 9200 174b 7c13 Sapphire Radeon 9200 @@ -767,12 +784,13 @@ # 128MB DDR, DVI/VGA/TV out 18bc 0173 GC-R9200L(SE)-C3H [Radeon 9200 Game Buster] 5b60 RV370 5B60 [Radeon X300 (PCIE)] - 1043 002a EAX300SE + 1043 002a Extreme AX300SE-X + 1043 032e Extreme AX300/TD 5b62 RV370 5B62 [Radeon X600 (PCIE)] 5b64 RV370 5B64 [FireGL V3100 (PCIE)] 5b65 RV370 5B65 [FireGL D1100 (PCIE)] - 5c61 RV250 5c61 [Radeon Mobility 9200 M9+] - 5c63 RV250 5c63 [Radeon Mobility 9200 M9+] + 5c61 M9+ 5C61 [Radeon Mobility 9200 (AGP)] + 5c63 M9+ 5C63 [Radeon Mobility 9200 (AGP)] 5d44 RV280 [Radeon 9200 SE] (Secondary) 1458 4019 Radeon 9200 SE (Secondary) 174b 7c12 Sapphire Radeon 9200 SE (Secondary) @@ -780,6 +798,7 @@ 17af 2013 Radeon 9200 SE Excalibur (Secondary) 18bc 0171 Radeon 9200 SE 128MB Game Buster (Secondary) 18bc 0172 GC-R9200L(SE)-C3H [Radeon 9200 Game Buster] + 5d4d R480 [Radeon X850XT Platinum] 5d57 R423 5F57 [Radeon X800XT (PCIE)] 700f PCI Bridge [IGP 320M] 7010 PCI Bridge [IGP 340M] @@ -845,12 +864,13 @@ 103c 0024 Pavilion ze4400 builtin Network 1385 f311 FA311 / FA312 (FA311 with WoL HW) 0022 DP83820 10/100/1000 Ethernet Controller - 0028 CS5535 Host bridge + 0028 Geode GX2 Host Bridge + 002a CS5535 South Bridge 002b CS5535 ISA bridge 002d CS5535 IDE 002e CS5535 Audio 002f CS5535 USB - 0030 CS5535 Video + 0030 Geode GX2 Graphics Processor 0035 DP83065 [Saturn] 10/100/1000 Ethernet Controller 0500 SCx200 Bridge 0501 SCx200 SMI @@ -997,11 +1017,13 @@ 1200 GD 7542 [Nordic] 1202 GD 7543 [Viking] 1204 GD 7541 [Nordic Light] + 4000 MD 5620 [CLM Data Fax Voice] 4400 CD 4400 6001 CS 4610/11 [CrystalClear SoundFusion Audio Accelerator] 1014 1010 CS4610 SoundFusion Audio Accelerator 6003 CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator] 1013 4280 Crystal SoundFusion PCI Audio Accelerator + 153b 1136 SiXPack 5.1+ 1681 0050 Game Theater XP 1681 a011 Fortissimo III 7.1 6004 CS 4614/22/24 [CrystalClear SoundFusion Audio Accelerator] @@ -1121,7 +1143,7 @@ 0266 PCI-X Dual Channel SCSI 0268 Gigabit Ethernet-SX Adapter (PCI-X) 0269 10/100/1000 Base-TX Ethernet Adapter (PCI-X) - 028C Citrine chipset SCSI controller + 028c Citrine chipset SCSI controller 1014 028D Dual Channel PCI-X DDR SAS RAID Adapter (572E) 1014 02BE Dual Channel PCI-X DDR U320 SCSI RAID Adapter (571B) 1014 02C0 Dual Channel PCI-X DDR U320 SCSI Adapter (571A) @@ -1263,6 +1285,7 @@ 2001 4DWave NX 122d 1400 Trident PCI288-Q3DII (NX) 2100 CyberBlade XP4m32 + 2200 XGI Volari XP5 8400 CyberBlade/i7 1023 8400 CyberBlade i7 AGP 8420 CyberBlade/i7d @@ -1625,6 +1648,7 @@ 1010 00a0 PowerVR Neon 250 AGP 32Mb 1010 00a8 PowerVR Neon 250 32Mb 1010 0120 PowerVR Neon 250 AGP 32Mb + 0072 uPD72874 IEEE1394 OHCI 1.1 3-port PHY-Link Ctrlr 0074 56k Voice Modem 1033 8014 RCV56ACF 56k Voice Modem 009b Vrc5476 @@ -1719,7 +1743,6 @@ 1039 5513 SiS5513 EIDE Controller (A,B step) 1043 8035 CUSI-FX motherboard 5517 5517 - 5518 5518 [IDE] 5571 5571 5581 5581 Pentium Chipset 5582 5582 @@ -1818,6 +1841,8 @@ 108b Visualize FXe 10c1 NetServer Smart IRQ Router 10ed TopTools Remote Control + 10f0 rio System Bus Adapter + 10f1 rio I/O Controller 1200 82557B 10/100 NIC 1219 NetServer PCI Hot-Plug Controller 121a NetServer SMIC Controller @@ -1828,6 +1853,7 @@ 122e zx1 Local Bus Adapter 127c sx1000 I/O Controller 1290 Auxiliary Diva Serial Port + 12b4 zx1 QuickSilver AGP8x Local Bus Adapter 2910 E2910A PCIBus Exerciser 2925 E2925A 32 Bit, 33 MHzPCI Exerciser & Analyzer 103e Solliday Engineering @@ -1848,6 +1874,8 @@ 8043 v8240 PAL 128M [P4T] Motherboard 807b v9280/TD [Geforce4 TI4200 8X With TV-Out and DVI] 80bb v9180 Magic/T [GeForce4 MX440 AGP 8x 64MB TV-out] + 80c5 nForce3 chipset motherboard [SK8N] + 80df v9520 Magic/T 1044 Adaptec (formerly DPT) 1012 Domino RAID Engine a400 SmartCache/Raid I-IV Controller @@ -1886,7 +1914,7 @@ 1044 c05a 2400A UDMA Four Channel 1044 c05b 2400A UDMA Four Channel DAC 1044 c064 3010S Ultra3 Dual Channel - 1044 c065 3010S Ultra3 Four Channel + 1044 c065 3410S Ultra160 Four Channel 1044 c066 3010S Fibre Channel a511 SmartRAID V Controller 1044 c032 ASR-2005S I2O Zero Channel @@ -1983,11 +2011,13 @@ 11bd 000e Studio DV e4bf 1010 CF2-1-CYMBAL 8020 TSB12LV26 IEEE-1394 Controller (Link) + 11bd 000f Studio DV500-1394 8021 TSB43AA22 IEEE-1394 Controller (PHY/Link Integrated) 104d 80df Vaio PCG-FX403 104d 80e7 VAIO PCG-GR214EP/GR214MP/GR215MP/GR314MP/GR315MP 8022 TSB43AB22 IEEE-1394a-2000 Controller (PHY/Link) 8023 TSB43AB22/A IEEE-1394a-2000 Controller (PHY/Link) + 103c 088c nc8000 laptop 8024 TSB43AB23 IEEE-1394a-2000 Controller (PHY/Link) 8025 TSB82AA2 IEEE-1394b Link Layer Controller 55aa 55aa FireWire 800 PCI Card @@ -1997,8 +2027,17 @@ 8029 PCI4510 IEEE-1394 Controller 1028 0163 Latitude D505 1071 8160 MIM2900 + 802b PCI7410,7510,7610 OHCI-Lynx Controller + 1028 014e PCI7410,7510,7610 OHCI-Lynx Controller (Dell Latitude D800) 802e PCI7x20 1394a-2000 OHCI Two-Port PHY/Link-Layer Controller + 8031 Texas Instruments PCIxx21/x515 Cardbus Controller + 8032 Texas Instruments OHCI Compliant IEEE 1394 Host Controller + 8033 Texas Instruments PCIxx21 Integrated FlashMedia Controller + 8034 Texas Instruments PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Secure Digital (SD) Controller + 8035 Texas Instruments PCI6411, PCI6421, PCI6611, PCI6621, PCI7411, PCI7421, PCI7611, PCI7621 Smart Card Controller (SMC) 8201 PCI1620 Firmware Loading Function + 8204 PCI7410,7510,7610 PCI Firmware Loading Function + 1028 014e Latitude D800 8400 ACX 100 22Mbps Wireless Interface 00fc 16ec U.S. Robotics 22 Mbps Wireless PC Card (model 2210) 00fd 16ec U.S. Robotics 22Mbps Wireless PCI Adapter (model 2216) @@ -2047,6 +2086,10 @@ 1028 0163 Latitude D505 1071 8160 MIM2000 ac46 PCI4520 PC card Cardbus Controller + ac47 PCI7510 PC card Cardbus Controller + 1028 014e Latitude D800 + ac4a PCI7510,7610 PC card Cardbus Controller + 1028 014e Latitude D800 ac50 PCI1410 PC card Cardbus Controller ac51 PCI1420 1014 023b ThinkPad T23 (2647-4MG) @@ -2068,10 +2111,11 @@ 175c 6200 ASI62xx Audio Adapter ac8d PCI 7620 ac8e PCI7420 CardBus Controller - ac8f PCI7420/PCI7620 Dual Socket CardBus and Smart Card Cont. + ac8f PCI7420/PCI7620 Dual Socket CardBus and Smart Card Cont. w/ 1394a-2000 OHCI Two-Port PHY/Link-Layer Cont. and SD/MS-Pro Sockets fe00 FireWire Host Controller fe03 12C01A FireWire Host Controller 104d Sony Corporation + 8004 DTL-H2500 [Playstation development board] 8009 CXD1947Q i.LINK Controller 8039 CXD3222 i.LINK Controller 8056 Rockwell HCF 56K modem @@ -2132,9 +2176,32 @@ 175c 4200 ASI4215 Audio Adapter 175c 4300 ASI43xx Audio Adapter 175c 4400 ASI4401 Audio Adapter - ecc0 0030 Layla + ecc0 0010 Darla + ecc0 0020 Gina + ecc0 0030 Layla rev.0 + ecc0 0031 Layla rev.1 + ecc0 0040 Darla24 rev.0 + ecc0 0041 Darla24 rev.1 + ecc0 0050 Gina24 rev.0 + ecc0 0051 Gina24 rev.1 + ecc0 0070 Mona rev.0 + ecc0 0071 Mona rev.1 + ecc0 0072 Mona rev.2 18c0 MPC8265A/MPC8266 18c1 MPC8271/MPC8272 + 3410 DSP56361 Digital Signal Processor + ecc0 0050 Gina24 rev.0 + ecc0 0051 Gina24 rev.1 + ecc0 0060 Layla24 + ecc0 0070 Mona rev.0 + ecc0 0071 Mona rev.1 + ecc0 0072 Mona rev.2 + ecc0 0080 Mia rev.0 + ecc0 0081 Mia rev.1 + ecc0 0090 Indigo + ecc0 00a0 Indigo IO + ecc0 00b0 Indigo DJ + ecc0 0100 3G 4801 Raven 4802 Falcon 4803 Hawk @@ -2175,13 +2242,14 @@ 8086 3427 S875WP1-E mainboard 3371 PDC20371 (FastTrak S150 TX2plus) 3373 PDC20378 (FastTrak 378/SATA 378) - 1043 80f5 PC-DL Deluxe motherboard + 1043 80f5 K8V Deluxe/PC-DL Deluxe motherboard 1462 702e K8T NEO FIS2R motherboard 3375 PDC20375 (SATA150 TX2plus) 3376 PDC20376 (FastTrak 376) 1043 809e A7V8X motherboard 3574 PDC20579 SATAII 150 IDE Controller - 3d18 PDC20518 SATAII 150 IDE Controller + 3d18 PDC20518/PDC40518 (SATAII 150 TX4) + 3d75 PDC20575 (SATAII150 TX2plus) 4d30 PDC20267 (FastTrak100/Ultra100) 105a 4d33 Ultra100 105a 4d39 FastTrak100 @@ -2302,8 +2370,8 @@ 1014 0242 iSeries 2872 DASD IOA 1014 0266 Dual Channel PCI-X U320 SCSI Adapter 1014 0278 Dual Channel PCI-X U320 SCSI RAID Adapter - 1014 02D3 Dual Channel PCI-X U320 SCSI Adapter - 1014 02D4 Dual Channel PCI-X U320 SCSI RAID Adapter + 1014 02d3 Dual Channel PCI-X U320 SCSI Adapter + 1014 02d4 Dual Channel PCI-X U320 SCSI RAID Adapter ba55 eXtremeRAID 1100 support Device ba56 eXtremeRAID 2000/3000 support Device 106a Aten Research Inc @@ -2313,6 +2381,7 @@ 0003 Control Video 0004 PlanB Video-In 0007 O'Hare I/O + 000c DOS on Mac 000e Hydra Mac I/O 0010 Heathrow Mac I/O 0017 Paddington Mac I/O @@ -2512,11 +2581,13 @@ 1101 RIO GEM 1102 RIO 1394 1103 RIO USB + 1648 [bge] Gigabit Ethernet 2bad GEM 5000 Simba Advanced PCI Bridge 5043 SunPCI Co-processor 8000 Psycho PCI Bus Module 8001 Schizo PCI Bus Module + 8002 Schizo+ PCI Bus Module a000 Ultra IIi a001 Ultra IIe a801 Tomatillo PCI Bus Module @@ -2560,6 +2631,7 @@ 1170 PCI-MIO-16XE-10 1180 PCI-MIO-16E-1 1190 PCI-MIO-16E-4 + 1310 PCI-6602 1330 PCI-6031E 1350 PCI-6071E 14e0 PCI-6110 @@ -2575,6 +2647,7 @@ 2a80 PCI-6025E 2c80 PCI-6035E 2ca0 PCI-6034E + 70b8 PCI-6251 [M Series - High Speed Multifunction DAQ] b001 IMAQ-PCI-1408 b011 IMAQ-PXI-1408 b021 IMAQ-PCI-1424 @@ -2589,13 +2662,13 @@ c831 PCI-GPIB bridge 1094 First International Computers [FIC] 1095 Silicon Image, Inc. (formerly CMD Technology Inc) - 0240 Adaptec AAR-1210SA SATA HostRAID Contr. + 0240 Adaptec AAR-1210SA SATA HostRAID Controller 0640 PCI0640 0643 PCI0643 0646 PCI0646 0647 PCI0647 0648 PCI0648 - 0649 SiI 0649 Ultra ATA-100 Host Controller + 0649 SiI 0649 Ultra ATA/100 PCI to ATA Host Controller 0e11 005d Integrated Ultra ATA-100 Dual Channel Controller 0e11 007e Integrated Ultra ATA-100 IDE RAID Controller 101e 0649 AMI MegaRAID IDE 100 Controller @@ -2647,6 +2720,7 @@ 127a 0048 Bt878/832 Mediastream Controller 144f 3000 MagicTView CPH060 - Video 1461 0002 TV98 Series (TV/No FM/Remote) + 1461 0003 AverMedia UltraTV PCI 350 1461 0004 AVerTV WDM Video Capture 1461 0761 AverTV DVB-T 14f1 0001 Bt878 Mediastream Controller NTSC @@ -2822,10 +2896,14 @@ 1146 VScom 010 1 port parallel adaptor 1147 VScom 020 2 port parallel adaptor 2724 Thales PCSM Security Card + 8516 PEX 8516 Versatile PCI Express Switch + 8532 PEX 8532 Versatile PCI Express Switch 9030 PCI <-> IOBus Bridge Hot Swap 10b5 2862 Alpermann+Velte PCL PCI LV (3V/5V): Timecode Reader Board 10b5 2906 Alpermann+Velte PCI TS (3V/5V): Time Synchronisation Board 10b5 2940 Alpermann+Velte PCL PCI D (3V/5V): Timecode Reader Board + 10b5 3025 Alpermann+Velte PCL PCI L (3V/5V): Timecode Reader Board + 10b5 3068 Alpermann+Velte PCL PCI HD (3V/5V): Timecode Reader Board 15ed 1002 MCCS 8-port Serial Hot Swap 15ed 1003 MCCS 16-port Serial Hot Swap 9036 9036 @@ -2934,7 +3012,7 @@ 1201 3c982-TXM 10/100baseTX Dual Port A [Hydra] 1202 3c982-TXM 10/100baseTX Dual Port B [Hydra] 1700 3c940 10/100/1000Base-T [Marvell] - 1043 80eb P4P800 Mainboard + 1043 80eb P4P800/K8V Deluxe motherboard 10b7 0010 3C940 Gigabit LOM Ethernet Adapter 10b7 0020 3C941 Gigabit LOM Ethernet Adapter 147b 1407 KV8-MAX3 motherboard @@ -3125,6 +3203,7 @@ 5217 M5217H 5219 M5219 5225 M5225 + 5228 M5228 ALi ATA/RAID Controller 5229 M5229 IDE 1014 050f ThinkPad R30 1014 053d ThinkPad R40e (2684-HVG) builtin IDE @@ -3144,6 +3223,8 @@ 5261 M5261 Ethernet Controller 5263 M5263 Ethernet Controller 5281 ALi M5281 Serial ATA / RAID Host Controller + 5287 ULi 5287 SATA + 5289 ULi 5289 SATA 5450 Lucent Technologies Soft Modem AMR 5451 M5451 PCI AC-Link Controller Audio Device 1014 0506 ThinkPad R30 @@ -3210,7 +3291,7 @@ 10f7 8312 MagicGraph 128XD 0005 NM2200 [MagicGraph 256AV] 1014 00dd ThinkPad 570 - 1028 0088 Latitude CPi A400XT + 1028 0088 Latitude CPi A 0006 NM2360 [MagicMedia 256ZX] 0016 NM2380 [MagicMedia 256XL+] 10c8 0016 MagicMedia 256XL+ @@ -3258,6 +3339,7 @@ 10d7 BCM Advanced Research 10d8 Advanced Peripherals Labs 10d9 Macronix, Inc. [MXIC] + 0431 MX98715 0512 MX98713 0531 MX987x5 1186 1200 DFE-540TX ProFAST 10/100 Adapter @@ -3346,6 +3428,7 @@ 1102 102c CT6931 RIVA TNT2 Value [Jumper] 1462 8808 MSI-8808 1554 1041 Pixelview RIVA TNT2 M64 + 1569 002d Palit Microsystems Daytona TNT2 M64 002e NV6 [Vanta] 002f NV6 [Vanta] 0034 MCP04 SMBus @@ -3358,13 +3441,14 @@ 003c MCP04 USB Controller 003d MCP04 PCI Bridge 003e MCP04 Serial ATA Controller - 0040 NV40 [GeForce 6800 Ultra] + 0040 nv40 [GeForce 6800 Ultra] 0041 NV40 [GeForce 6800] 0042 NV40.2 0043 NV40.3 0045 NV40 [GeForce 6800 GT] 0049 NV40GL 004e NV40GL [Quadro FX 4000] + 0051 CK804 ISA Bridge 0052 CK804 SMBus 0053 CK804 IDE 0054 CK804 Serial ATA Controller @@ -3388,7 +3472,7 @@ 0068 nForce2 USB Controller 1043 0c11 A7N8X Mainboard 006a nForce2 AC97 Audio Controler (MCP) - 006b nForce MultiMedia audio [Via VT82C686B] + 006b nForce Audio Processing Unit 10de 006b nForce2 MCP Audio Processing Unit 006c nForce2 External PCI Bridge 006d nForce2 PCI Bridge @@ -3421,6 +3505,7 @@ 00da nForce3 Audio 00dd nForce3 PCI Bridge 00df CK8S Ethernet Controller + 00e0 nForce3 250Gb LPC Bridge 00e1 nForce3 250Gb Host Bridge 00e2 nForce3 250Gb AGP Host to PCI Bridge 00e3 CK8S Serial ATA Controller (v2.5) @@ -3428,7 +3513,7 @@ 00e5 CK8S Parallel ATA Controller (v2.5) 00e6 CK8S Ethernet Controller 00e7 CK8S USB Controller - 00e8 CK8S USB Controller + 00e8 nForce3 EHCI USB 2.0 Controller 00ea nForce3 250Gb AC'97 Audio Controller 00ed nForce3 250Gb PCI-to-PCI Bridge 00ee CK8S Serial ATA Controller (v2.5) @@ -3436,7 +3521,8 @@ 00f1 NV43 [GeForce 6600/GeForce 6600 GT] 00f2 NV43 [GeForce 6600 GT] 00f8 NV45GL [Quadro FX 3400] - 00f9 NV40 [GeForce 6800 Ultra] + 00f9 NV40 [GeForce 6800 Ultra/GeForce 6800 GT] + 1682 2120 GEFORCE 6800 GT PCI-E 00fa NV36 [GeForce PCX 5750] 00fb NV35 [GeForce PCX 5900] 00fc NV37GL [Quadro FX 330/GeForce PCX 5300] @@ -3468,6 +3554,8 @@ 0111 NV11DDR [GeForce2 MX 100 DDR/200 DDR] 0112 NV11 [GeForce2 Go] 0113 NV11GL [Quadro2 MXR/EX] + 0140 NV43 [MSI NX6600GT-TD128E] + 014f NV43 [GeForce 6200] 0150 NV15 [GeForce2 GTS/Pro] 1043 4016 V7700 AGP Video Card 107d 2840 WinFast GeForce2 GTS with TV output @@ -3545,6 +3633,22 @@ 1043 405b V8200 T5 1545 002f Xtasy 6964 0203 NV20DCC [Quadro DCC] + 0240 C51 PCI Express Bridge + 0241 C51 PCI Express Bridge + 0242 C51 PCI Express Bridge + 0243 C51 PCI Express Bridge + 0244 C51 PCI Express Bridge + 0245 C51 PCI Express Bridge + 0246 C51 PCI Express Bridge + 0247 C51 PCI Express Bridge + 0248 C51 PCI Express Bridge + 0249 C51 PCI Express Bridge + 024a C51 PCI Express Bridge + 024b C51 PCI Express Bridge + 024c C51 PCI Express Bridge + 024d C51 PCI Express Bridge + 024e C51 PCI Express Bridge + 024f C51 PCI Express Bridge 0250 NV25 [GeForce4 Ti 4600] 0251 NV25 [GeForce4 Ti 4400] 1043 8023 v8440 GeForce 4 Ti4400 @@ -3555,6 +3659,27 @@ 0258 NV25GL [Quadro4 900 XGL] 0259 NV25GL [Quadro4 750 XGL] 025b NV25GL [Quadro4 700 XGL] + 0260 MCP51 LPC Bridge + 0261 MCP51 LPC Bridge + 0262 MCP51 LPC Bridge + 0263 MCP51 LPC Bridge + 0264 MCP51 SMBus + 0265 MCP51 IDE + 0266 MCP51 Serial ATA Controller + 0267 MCP51 Serial ATA Controller + 0268 MCP51 Ethernet Controller + 0269 MCP51 Ethernet Controller + 026a MCP51 MCI + 026b MCP51 AC97 Audio Controller + 026c MCP51 High Definition Audio + 026d MCP51 USB Controller + 026e MCP51 USB Controller + 026f MCP51 PCI Bridge + 0270 MCP51 Host Bridge + 0271 MCP51 PMU + 0272 MCP51 Memory Controller 0 + 027e C51 Memory Controller 2 + 027f C51 Memory Controller 3 0280 NV28 [GeForce4 Ti 4800] 0281 NV28 [GeForce4 Ti 4200 AGP 8x] 0282 NV28 [GeForce4 Ti 4800 SE] @@ -3562,6 +3687,22 @@ 0288 NV28GL [Quadro4 980 XGL] 0289 NV28GL [Quadro4 780 XGL] 028c NV28GLM [Quadro4 700 GoGL] + 02f0 C51 Host Bridge + 02f1 C51 Host Bridge + 02f2 C51 Host Bridge + 02f3 C51 Host Bridge + 02f4 C51 Host Bridge + 02f5 C51 Host Bridge + 02f6 C51 Host Bridge + 02f7 C51 Host Bridge + 02f8 C51 Memory Controller 5 + 02f9 C51 Memory Controller 4 + 02fa C51 Memory Controller 0 + 02fb C51 PCI Express Bridge + 02fc C51 PCI Express Bridge + 02fd C51 PCI Express Bridge + 02fe C51 Memory Controller 1 + 02ff C51 Host Bridge 0300 NV30 [GeForce FX] 0301 NV30 [GeForce FX 5800 Ultra] 0302 NV30 [GeForce FX 5800] @@ -3621,27 +3762,25 @@ 1ae5 LP6000 Fibre Channel Host Adapter 1ae6 LP 8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) 1ae7 LP 8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:2-3) - f015 LP1150e - f085 LP850 Fibre Channel Adapter - f095 LP952 Fibre Channel Adapter - f098 LP982 Fibre Channel Adapter - f0a1 LightPulse Fibre Channel Adapter - f0a5 LP1050 - f0d5 LP1150 - f100 LP11000e + f005 LP1150e Fibre Channel Host Adapter + f085 LP850 Fibre Channel Host Adapter + f095 LP952 Fibre Channel Host Adapter + f098 LP982 Fibre Channel Host Adapter + f0a5 LP1050 Fibre Channel Host Adapter + f0d5 LP1150 Fibre Channel Host Adapter + f100 LP11000e Fibre Channel Host Adapter f700 LP7000 Fibre Channel Host Adapter f701 LP 7000EFibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) f800 LP8000 Fibre Channel Host Adapter f801 LP 8000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) f900 LP9000 Fibre Channel Host Adapter f901 LP 9000 Fibre Channel Host Adapter Alternate ID (JX1:2-3, JX2:1-2) - f980 LP9802 Fibre Channel Adapter + f980 LP9802 Fibre Channel Host Adapter f981 LP 9802 Fibre Channel Host Adapter Alternate ID f982 LP 9802 Fibre Channel Host Adapter Alternate ID fa00 LP10000 Fibre Channel Host Adapter - fa01 LP101 - fb00 LightPulse Fibre Channel Adapter - fd00 LP11000 + fa01 LP101 Fibre Channel Host Adapter + fd00 LP11000 Fibre Channel Host Adapter 10e0 Integrated Micro Solutions Inc. 5026 IMS5026/27/28 5027 IMS5027 @@ -3823,11 +3962,13 @@ 1102 0051 SB0090 Audigy Player 1102 0053 SB0090 Audigy Player/OEM 1102 0058 SB0090 Audigy Player/OEM + 1102 1007 SB0240 Audigy 2 Platinum 6.1 1102 2002 SB Audigy 2 ZS (SB0350) 0006 [SB Live! Value] EMU10k1X 0007 SB Audigy LS 1102 1001 SB0310 Audigy LS 1102 1002 SB0312 Audigy LS + 1102 1006 SB0410 SBLive! 24-bit 0008 SB0400 Audigy2 Value 4001 SB Audigy FireWire Port 1102 0010 SB Audigy FireWire Port @@ -3841,10 +3982,24 @@ 1102 1002 SB0312 Audigy LS MIDI/Game port 8064 SB0100 [SBLive! 5.1 OEM] 8938 Ectiva EV1938 + 1033 80e5 SlimTower-Jim (NEC) + 1071 7150 Mitac 7150 + 110a 5938 Siemens Scenic Mobile 510PIII + 13bd 100c Ceres-C (Sharp, Intel BX) + 13bd 100d Sharp, Intel Banister + 13bd 100e TwinHead P09S/P09S3 (Sharp) + 13bd f6f1 Marlin (Sharp) + 14ff 0e70 P88TE (TWINHEAD INTERNATIONAL Corp) + 14ff c401 Notebook 9100/9200/2000 (TWINHEAD INTERNATIONAL Corp) + 156d b400 G400 - Geo (AlphaTop (Taiwan)) + 156d b550 G560 (AlphaTop (Taiwan)) + 156d b560 G560 (AlphaTop (Taiwan)) + 156d b700 G700/U700 (AlphaTop (Taiwan)) + 156d b795 G795 (AlphaTop (Taiwan)) + 156d b797 G797 (AlphaTop (Taiwan)) 1103 Triones Technologies, Inc. 0003 HPT343 -# Revisions: 01=HPT366, 03=HPT370, 04=HPT370A, 05=HPT372 - 0004 HPT366/368/370/370A/372 + 0004 HPT366/368/370/370A/372/372N 1103 0001 HPT370A 1103 0003 HPT343 / HPT345 / HPT363 UDMA33 1103 0004 HPT366 UDMA66 (r1) / HPT368 UDMA66 (r2) / HPT370 UDMA100 (r3) / HPT370 UDMA100 RAID (r4) @@ -3852,9 +4007,9 @@ 1103 0006 HPT302 1103 0007 HPT371 UDMA133 1103 0008 HPT374 UDMA/ATA133 RAID Controller - 0005 HPT372A + 0005 HPT372A/372N 0006 HPT302 - 0007 HPT371 + 0007 HPT371/371N 0008 HPT374 0009 HPT372N 1104 RasterOps Corp. @@ -3945,6 +4100,7 @@ 1458 5004 GA-7VAX Mainboard 1462 7020 K8T NEO 2 motherboard 147b 1407 KV8-MAX3 motherboard + 182d 201d CN-029 USB2.0 4 port PCI Card 3040 VT82C586B ACPI 3043 VT86C100A [Rhine] 10bd 0000 VT86C100A Fast Ethernet Adapter @@ -3978,7 +4134,7 @@ 1019 0a81 L7VTA v1.0 Motherboard (KT400-8235) 1043 8095 A7V8X Motherboard (Realtek ALC650 codec) 1043 80a1 A7V8X-X Motherboard - 1043 80b0 A7V600 motherboard (ADI AD1980 codec [SoundMAX]) + 1043 80b0 A7V600/K8V Deluxe motherboard (ADI AD1980 codec [SoundMAX]) 1106 3059 L7VMM2 Motherboard 1106 4161 K7VT2 motherboard 1297 c160 FX41 motherboard (Realtek ALC650 codec) @@ -4014,6 +4170,7 @@ 1458 5004 GA-7VAX Mainboard 1462 7020 K8T NEO 2 motherboard 147b 1407 KV8-MAX3 motherboard + 182d 201d CN-029 USB 2.0 4 port PCI Card 3106 VT6105 [Rhine-III] 1186 1403 DFE-530TX rev C 3108 S3 Unichrome Pro VGA Adapter @@ -4032,9 +4189,10 @@ 3147 VT8233A ISA Bridge 3148 P4M266 Host Bridge 3149 VIA VT6420 SATA RAID Controller - 1043 80ed A7V600 motherboard + 1043 80ed A7V600/K8V Deluxe motherboard 1458 b003 GA-7VM400AM(F) Motherboard - 1462 7020 MSI Neo K8T FIS2R mainboard + 1462 7020 K8T Neo 2 Motherboard + 147b 1407 KV8-MAX3 motherboard 3156 P/KN266 Host Bridge # on ASUS P4P800 3164 VT6410 ATA133 RAID controller @@ -4046,7 +4204,9 @@ 1297 f641 FX41 motherboard 1458 5001 GA-7VAX Mainboard 1849 3177 K7VT2 motherboard + 3178 ProSavageDDR P4N333 Host Bridge 3188 VT8385 [K8T800 AGP] Host Bridge + 1043 80a3 K8V Deluxe motherboard 147b 1407 KV8-MAX3 motherboard 3189 VT8377 [KT400/KT600 AGP] Host Bridge 1043 807f A7V8X motherboard @@ -4054,11 +4214,13 @@ 3204 K8M800 3205 VT8378 [KM400/A] Chipset Host Bridge 1458 5000 GA-7VM400M Motherboard + 3218 K8T800M Host Bridge 3227 VT8237 ISA bridge [KT600/K8T800 South] 1043 80ed A7V600 motherboard 1106 3227 DFI KT600-AL Motherboard 1458 5001 GA-7VT600 Motherboard 147b 1407 KV8-MAX3 motherboard + 3249 VT6421 IDE RAID Controller 4149 VIA VT6420 (ATA133) Controller 5030 VT82C596 ACPI [Apollo PRO] 6100 VT85C100A [Rhine II] @@ -4114,7 +4276,7 @@ 007c FSC Remote Service Controller, shared memory device 007d FSC Remote Service Controller, SMIC device # Superfastcom-PCI (Commtech, Inc.) or DSCC4 WAN Adapter - 2102 DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Contr. + 2102 DSCC4 PEB/PEF 20534 DMA Supported Serial Communication Controller with 4 Channels 2104 Eicon Diva 2.02 compatible passive ISDN card 3142 SIMATIC NET CP 5613A1 (Profibus Adapter) 4021 SIMATIC NET CP 5512 (Profibus and MPI Cardbus Adapter) @@ -4301,13 +4463,16 @@ 3400 SmartPCI56(UCB1500) 56K Modem 5400 TriMedia TM1000/1100 5402 TriMedia TM-1300 + 1244 0f00 Fritz!Card DSL 7130 SAA7130 Video Broadcast Decoder 5168 0138 LiveView FlyVideo 2000 7133 SAA713X Audio+video broadcast decoder 5168 0138 LifeView FlyVideo 3000 5168 0212 LifeView FlyTV Platinum mini + 5168 0502 LifeView FlyDVB-T Duo CardBus # PCI audio and video broadcast decoder (http://www.semiconductors.philips.com/pip/saa7134hl) 7134 SAA7134 + 1043 4842 TV-FM Card 7134 7135 SAA7135 Audio+video broadcast decoder 7145 SAA7145 7146 SAA7146 @@ -4318,6 +4483,7 @@ 114b 2003 DVRaptor Video Edit/Capture Card 11bd 0006 DV500 Overlay 11bd 000a DV500 Overlay + 11bd 000f DV500 Overlay 13c2 0000 Siemens/Technotrend/Hauppauge DVB card rev1.3 or rev1.5 13c2 0001 Technotrend/Hauppauge DVB card rev1.3 or rev1.6 13c2 0002 Technotrend/Hauppauge DVB card rev2.1 @@ -4368,37 +4534,45 @@ e011 Diva Server BRI S/T Rev 2 e012 Diva Server 4BRI-8M PCI 8001 0014 Diva Server 4BRI-8M PCI Cornet NQ - e013 Diva Server 4BRI-8M Rev 2 - 8001 0014 Diva Server 4BRI-8M Cornet NQ 2 + e013 Diva Server 4BRI Rev 2 + 1133 1300 Diva Server V-4BRI-8 + 1133 e013 Diva Server 4BRI-8M 2.0 PCI + 8001 0014 Diva Server 4BRI-8M 2.0 PCI Cornet NQ e014 Diva Server PRI-30M PCI 0008 0100 Diva Server PRI-30M PCI 8001 0014 Diva Server PRI-30M PCI Cornet NQ - e015 DIVA Server PRI-30M 2.0 - 8001 0014 Diva Server PRI Cornet NQ 2 + e015 DIVA Server PRI Rev 2 + 1133 e015 Diva Server PRI 2.0 PCI + 8001 0014 Diva Server PRI 2.0 PCI Cornet NQ e016 Diva Server Voice 4BRI PCI 8001 0014 Diva Server PRI Cornet NQ - e017 Diva Server Voice 4BRI PCI Rev 2 - 8001 0014 Diva Server Voice 4BRI PCI Cornet NQ 2 - e018 Diva Server BRI 2M Revision 2 - 8001 0014 Diva Server BRI 2M Cornet NQ 2 - e019 Diva Server Voice PRI PCI Rev 2 - 8001 0014 Diva Server Voice PRI PCI Cornet NQ 2 + e017 Diva Server Voice 4BRI Rev 2 + 1133 e017 Diva Server Voice 4BRI-8M 2.0 PCI + 8001 0014 Diva Server Voice 4BRI-8M 2.0 PCI Cornet NQ + e018 Diva Server BRI-2M 2.0 PCI + 1133 1800 Diva Server V-BRI-2 + 1133 e018 Diva Server BRI-2M 2.0 PCI + 8001 0014 Diva Server BRI-2M 2.0 PCI Cornet NQ + e019 Diva Server Voice PRI Rev 2 + 1133 e019 Diva Server Voice PRI 2.0 PCI + 8001 0014 Diva Server Voice PRI 2.0 PCI Cornet NQ e01a Diva Server 2FX - e01b Diva Server BRI-2M Voice Revision 2 - 8001 0014 Diva Server BRI-2M Voice Cornet NQ 2 - e01c Diva Server PRI Rev 3.0 - 1133 1c01 Diva Server PRI/E1/T1-8 Rev 3.0 - 1133 1c02 Diva Server PRI/T1-24 Rev 3.0 - 1133 1c03 Diva Server PRI/E1-30 Rev 3.0 - 1133 1c04 Diva Server V-PRI/E1/T1 Rev 3.0 - 1133 1c05 Diva Server V-PRI/T1-24 Rev 3.0 - 1133 1c06 Diva Server V-PRI/E1-30 Rev 3.0 - 1133 1c07 Diva Server PRI/E1/T1-8 Cornet NQ 3 - 1133 1c08 Diva Server PRI/T1-24 Cornet NQ 3 - 1133 1c09 Diva Server PRI/E1-30 Cornet NQ 3 - 1133 1c0a Diva Server V-PRI/E1/T1 Cornet NQ 3 - 1133 1c0b Diva Server V-PRI/T1-24 Cornet NQ 3 - 1133 1c0c Diva Server V-PRI/E1-30 Cornet NQ 3 + e01b Diva Server Voice BRI-2M 2.0 PCI + 1133 e01b Diva Server Voice BRI-2M 2.0 PCI + 8001 0014 Diva Server Voice BRI-2M 2.0 PCI Cornet NQ + e01c Diva Server PRI Rev 3 + 1133 1c01 Diva Server PRI/E1/T1-8 + 1133 1c02 Diva Server PRI/T1-24 + 1133 1c03 Diva Server PRI/E1-30 + 1133 1c04 Diva Server PRI/E1/T1 + 1133 1c05 Diva Server V-PRI/T1-24 + 1133 1c06 Diva Server V-PRI/E1-30 + 1133 1c07 Diva Server PRI/E1/T1-8 Cornet NQ + 1133 1c08 Diva Server PRI/T1-24 Cornet NQ + 1133 1c09 Diva Server PRI/E1-30 Cornet NQ + 1133 1c0a Diva Server PRI/E1/T1 Cornet NQ + 1133 1c0b Diva Server V-PRI/T1-24 Cornet NQ + 1133 1c0c Diva Server V-PRI/E1-30 Cornet NQ e01e Diva Server 2PRI 1133 1e00 Diva Server V-2PRI/E1-60 1133 1e01 Diva Server V-2PRI/T1-48 @@ -4524,6 +4698,8 @@ 1148 9521 SK-9521 10/100/1000Base-T Adapter 4400 SK-9Dxx Gigabit Ethernet Adapter 4500 SK-9Mxx Gigabit Ethernet Adapter + 9000 SK-9Sxx Gigabit Ethernet Server Adapter PCI-X + 9843 [Fujitsu] Gigabit Ethernet 9e00 SK-9Exx 10/100/1000Base-T Adapter 1148 2100 SK-9E21 Server Adapter 1148 21d0 SK-9E21D 10/100/1000Base-T Adapter @@ -4696,6 +4872,8 @@ 0230 CSB5 LPC bridge 4c53 1080 CT8 mainboard 0240 K2 SATA + 0241 K2 SATA + 0242 K2 SATA 1167 Mutoh Industries Inc 1168 Thine Electronics Inc 1169 Centre for Development of Advanced Computing @@ -4724,7 +4902,7 @@ 0404 DVD Decoder card 0406 Tecra Video Capture device 0407 DVD Decoder card (Version 2) - 0601 601 + 0601 CPU to PCI bridge 0603 ToPIC95 PCI to CardBus Bridge for Notebooks 060a ToPIC95 060f ToPIC97 @@ -4761,6 +4939,8 @@ 144d c006 vpr Matrix 170B4 0552 R5C552 IEEE 1394 Controller 1014 0511 ThinkPad A/T/X Series + 0576 R5C576 SD Bus Host Adapter + 0592 R5C592 Memory Stick Bus Host Adapter 1181 Telmatics International 1183 Fujikura Ltd 1184 Forks Inc @@ -4795,6 +4975,7 @@ 3a63 AirXpert DWL-AG660 Wireless Cardbus Adapter 3b05 DWL-G650+ CardBus PC Card 4000 DL2000-based Gigabit Ethernet + 4300 DGE-528T Gigabit Ethernet Adapter 4c00 Gigabit Ethernet Adapter 1186 4c00 DGE-530T Gigabit Ethernet Adapter 8400 D-Link DWL-650+ CardBus PC Card @@ -4842,6 +5023,10 @@ 8030 AEC6712S SCSI 8040 AEC6712D SCSI 8050 AEC6712SUW SCSI + 8060 AEC6712 SCSI + 8080 AEC67160 SCSI + 8081 AEC67160S SCSI + 808a AEC67162 2-ch. LVD SCSI 1192 Densan Company Ltd 1193 Zeitnet Inc. 0001 1221 @@ -4879,7 +5064,7 @@ 0146 GT-64010/64010A System Controller 138f W8300 802.11 Adapter (rev 07) 1fa6 Marvell W8300 802.11 Adapter - 4146 GT-64011/GT-64111 System Controller + 1fa7 88W8310 and 88W8000G [Libertas] 802.11g client chipset 4320 Gigabit Ethernet Controller 1019 0f38 Marvell 88E8001 Gigabit Ethernet Controller (ECS) 1019 8001 Marvell 88E8001 Gigabit Ethernet Controller (ECS) @@ -4992,6 +5177,7 @@ 4611 GT-64115 System Controller 4620 GT-64120/64120A/64121A System Controller 4801 GT-48001 + 5005 Belkin F5D5005 Gigabit Desktop Network PCI Card 5040 MV88SX5040 4-port SATA I PCI-X Controller 5041 MV88SX5041 4-port SATA I PCI-X Controller 5080 MV88SX5080 8-port SATA I PCI-X Controller @@ -5332,25 +5518,29 @@ 1217 O2 Micro, Inc. 6729 OZ6729 673a OZ6730 - 6832 OZ6832/6833 Cardbus Controller - 6836 OZ6836/6860 Cardbus Controller - 6872 OZ6812 Cardbus Controller - 6925 OZ6922 Cardbus Controller - 6933 OZ6933 Cardbus Controller + 6832 OZ6832/6833 CardBus Controller + 6836 OZ6836/6860 CardBus Controller + 6872 OZ6812 CardBus Controller + 6925 OZ6922 CardBus Controller + 6933 OZ6933/711E1 CardBus/SmartCardBus Controller 1025 1016 Travelmate 612 TX - 6972 OZ6912 Cardbus Controller + 6972 OZ601/6912/711E0 CardBus/SmartCardBus Controller 1014 020c ThinkPad R30 1179 0001 Magnia Z310 - 7110 OZ711Mx MultiMediaBay Accelerator - 103c 0890 NC6000 laptop - 7112 OZ711EC1/M1 SmartCardBus MultiMediaBay Controller + 7110 OZ711Mx 4-in-1 MemoryCardBus Accelerator + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop + 7112 OZ711EC1/M1 SmartCardBus/MemoryCardBus Controller 7113 OZ711EC1 SmartCardBus Controller - 7114 OZ711M1 SmartCardBus MultiMediaBay Controller + 7114 OZ711M1/MC1 4-in-1 MemoryCardBus Controller + 7134 OZ711MP1/MS1 MemoryCardBus Controller 71e2 OZ711E2 SmartCardBus Controller - 7212 OZ711M2 SmartCardBus MultiMediaBay Controller + 7212 OZ711M2 4-in-1 MemoryCardBus Controller 7213 OZ6933E CardBus Controller - 7223 OZ711M3 SmartCardBus MultiMediaBay Controller - 103c 0890 NC6000 laptop + 7223 OZ711M3/MC3 4-in-1 MemoryCardBus Controller + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop + 7233 OZ711MP3/MS3 4-in-1 MemoryCardBus Controller 1218 Hybricon Corp. 1219 First Virtual Corporation 121a 3Dfx Interactive, Inc. @@ -5459,6 +5649,7 @@ 8120 E4? 11bd 0006 DV500 E4 11bd 000a DV500 E4 + 11bd 000f DV500 E4 8888 Cinemaster C 3.0 DVD Decoder 1002 0001 Cinemaster C 3.0 DVD Decoder 1002 0002 Cinemaster C 3.0 DVD Decoder @@ -5537,6 +5728,7 @@ 1969 ES1969 Solo-1 Audiodrive 1014 0166 ES1969 SOLO-1 AudioDrive on IBM Aptiva Mainboard 125d 8888 Solo-1 Audio Adapter + 153b 111b Terratec 128i PCI 1978 ES1978 Maestro 2E 0e11 b112 Armada M700/E500 1033 803c ES1978 Maestro-2E Audiodrive @@ -5586,6 +5778,7 @@ 10b8 2835 SMC2835W Wireless Cardbus Adapter 10b8 a835 SMC2835W V2 Wireless Cardbus Adapter 1113 ee03 SMC2802W V2 Wireless PCI Adapter + 1113 ee08 SMC2835W V3 EU Wireless Cardbus Adapter 1186 3202 DWL-G650 A1 Wireless Adapter 1259 c104 CG-WLCB54GT Wireless Adapter 1385 4800 WG511 Wireless Adapter @@ -5735,6 +5928,7 @@ 1048 1500 MicroLink 56k Modem 10cf 1059 Fujitsu 229-DFRT 1005 HCF 56k Data/Fax/Voice/Spkp (w/Handset) Modem + 1005 127a AOpen FM56-P 1033 8029 229-DFSV 1033 8054 Modem 10cf 103c Fujitsu @@ -5836,7 +6030,7 @@ 9132 Ethernet 100/10 MBit 1283 Integrated Technology Express, Inc. 673a IT8330G - 8212 IT/ITE8212 Dual channel ATA RAID controller + 8212 IT/ITE8212 Dual channel ATA RAID controller (PCI version seems to be IT8212, embedded seems to be ITE8212) 1283 0001 IT/ITE8212 Dual channel ATA RAID controller 8330 IT8330G 8872 IT8874F PCI Dual Serial Port Controller @@ -5952,6 +6146,34 @@ 0058 PCI NE2K Ethernet 5598 PCI NE2K Ethernet 12c4 Connect Tech Inc + 0001 Blue HEAT/PCI 8 (RS232/CL/RJ11) + 0002 Blue HEAT/PCI 4 (RS232) + 0003 Blue HEAT/PCI 2 (RS232) + 0004 Blue HEAT/PCI 8 (UNIV, RS485) + 0005 Blue HEAT/PCI 4+4/6+2 (UNIV, RS232/485) + 0006 Blue HEAT/PCI 4 (OPTO, RS485) + 0007 Blue HEAT/PCI 2+2 (RS232/485) + 0008 Blue HEAT/PCI 2 (OPTO, Tx, RS485) + 0009 Blue HEAT/PCI 2+6 (RS232/485) + 000a Blue HEAT/PCI 8 (Tx, RS485) + 000b Blue HEAT/PCI 4 (Tx, RS485) + 000c Blue HEAT/PCI 2 (20 MHz, RS485) + 000d Blue HEAT/PCI 2 PTM + 0100 NT960/PCI + 0201 cPCI Titan - 2 Port + 0202 cPCI Titan - 4 Port + 0300 CTI PCI UART 2 (RS232) + 0301 CTI PCI UART 4 (RS232) + 0302 CTI PCI UART 8 (RS232) + 0310 CTI PCI UART 1+1 (RS232/485) + 0311 CTI PCI UART 2+2 (RS232/485) + 0312 CTI PCI UART 4+4 (RS232/485) + 0320 CTI PCI UART 2 + 0321 CTI PCI UART 4 + 0322 CTI PCI UART 8 + 0330 CTI PCI UART 2 (RS485) + 0331 CTI PCI UART 4 (RS485) + 0332 CTI PCI UART 8 (RS485) 12c5 Picture Elements Incorporated 007e Imaging/Scanning Subsystem Engine 007f Imaging/Scanning Subsystem Engine @@ -6002,6 +6224,8 @@ 12d4 Ulticom (Formerly DGM&S) 0200 T1 Card 12d5 Equator Technologies Inc + 0003 BSP16 + 1000 BSP15 12d6 Analogic Corp 12d7 Biotronic SRL 12d8 Pericom Semiconductor @@ -6353,12 +6577,20 @@ 1381 Brains Co. Ltd 1382 Marian - Electronic & Software 0001 ARC88 audio recording card - 2088 Marc-8 MIDI 8 channel audio card + 2008 Prodif 96 Pro sound system + 2088 Marc 8 Midi sound system + 20c8 Marc A sound system + 4008 Marc 2 sound system + 4010 Marc 2 Pro sound system + 4048 Marc 4 MIDI sound system + 4088 Marc 4 Digi sound system + 4248 Marc X sound system 1383 Controlnet Inc 1384 Reality Simulation Systems Inc 1385 Netgear # Note: This lists as Atheros Communications, Inc. AR5212 802.11abg NIC because of Madwifi 0013 WG311T + 311a GA511 Gigabit Ethernet 4100 802.11b Wireless Adapter (MA301) 4105 MA311 802.11b wireless adapter 4400 WAG511 802.11a/b/g Dual Band Wireless PC Card @@ -6424,6 +6656,8 @@ 0016 8065 Security Processor 0017 8165 Security Processor 0018 8154 Security Processor + 001d 7956 Security Processor + 0020 7955 Security Processor 13a4 Rascom Inc 13a5 Audio Digital Imaging Inc 13a6 Videonics Inc @@ -6551,7 +6785,7 @@ 13fc Computer Peripherals International 13fd Micro Science Inc 13fe Advantech Co. Ltd - 1240 PCI-1240 4-channel stepper motor controller card + 1240 PCI-1240 4-channel stepper motor controller card w. Nova Electronics MCX314 1600 PCI-1612 4-port RS-232/422/485 PCI Communication Card 1752 PCI-1752 1754 PCI-1754 @@ -6569,6 +6803,8 @@ 0100 Lava Dual Serial 0101 Lava Quatro A 0102 Lava Quatro B + 0110 Lava DSerial-PCI Port A + 0111 Lava DSerial-PCI Port B 0120 Quattro-PCI A 0121 Quattro-PCI B 0180 Lava Octo A @@ -6599,18 +6835,47 @@ # formerly IC Ensemble Inc. 1412 VIA Technologies Inc. 1712 ICE1712 [Envy24] PCI Multi-Channel I/O Controller + 1412 1712 Hoontech ST Audio DSP 24 + 1412 d630 M-Audio Delta 1010 + 1412 d631 M-Audio Delta DiO + 1412 d632 M-Audio Delta 66 + 1412 d633 M-Audio Delta 44 + 1412 d634 M-Audio Delta Audiophile + 1412 d635 M-Audio Delta TDIF + 1412 d637 M-Audio Delta RBUS 1412 d638 M-Audio Delta 410 + 1412 d63b M-Audio Delta 1010LT + 1412 d63c Digigram VX442 + 1416 1712 Hoontech ST Audio DSP 24 Media 7.1 + 153b 1115 EWS88 MT + 153b 1125 EWS88 MT (Master) + 153b 112b EWS88 D + 153b 112c EWS88 D (Master) + 153b 1130 EWX 24/96 + 153b 1138 DMX 6fire 24/96 + 153b 1151 PHASE88 + 16ce 1040 Edirol DA-2496 1724 VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller + 1412 1724 AMP Ltd AUDIO2000 + 1412 3630 M-Audio Revolution 7.1 + 153b 1145 Aureon 7.1 Space + 153b 1147 Aureon 5.1 Sky + 153b 1153 Aureon 7.1 Universe + 270f f641 ZNF3-150 + 270f f645 ZNF3-250 1413 Addonics 1414 Microsoft Corporation 1415 Oxford Semiconductor Ltd 8403 VScom 011H-EP1 1 port parallel adaptor 9501 OX16PCI954 (Quad 16950 UART) function 0 131f 2050 CyberPro (4-port) +# Model IO1085, Part No: JJ-P46012 + 131f 2051 CyberSerial 4S Plus 15ed 2000 MCCR Serial p0-3 of 8 15ed 2001 MCCR Serial p0-3 of 16 950a EXSYS EX-41092 Dual 16950 Serial adapter 950b OXCB950 Cardbus 16950 UART + 9510 OX16PCI954 (Quad 16950 UART) function 1 (Disabled) 9511 OX16PCI954 (Quad 16950 UART) function 1 15ed 2000 MCCR Serial p4-7 of 8 15ed 2001 MCCR Serial p4-15 of 16 @@ -6694,6 +6959,7 @@ 1456 Advanced Hardware Architectures 1457 Nuera Communications Inc 1458 Giga-byte Technology + 0c11 K8NS Pro Mainboard 1459 DOOIN Electronics 145a Escalate Networks Inc 145b PRAIM SRL @@ -6705,11 +6971,15 @@ 1460 DYNARC INC 1461 Avermedia Technologies Inc 1462 Micro-Star International Co., Ltd. +# MSI CB54G Wireless PC Card that seems to use the Broadcom 4306 Chipset + 6819 Broadcom Corporation BCM4306 802.11b/g Wireless LAN Controller [MSI CB54G] 6825 PCI Card wireless 11g [PC54G] 8725 NVIDIA NV25 [GeForce4 Ti 4600] VGA Adapter # MSI G4Ti4800, 128MB DDR SDRAM, TV-Out, DVI-I 9000 NVIDIA NV28 [GeForce4 Ti 4800] VGA Adapter + 9110 GeFORCE FX5200 9119 NVIDIA NV31 [GeForce FX 5600XT] VGA Adapter + 9591 nVidia Corporation NV36 [GeForce FX 5700LE] 1463 Fast Corporation 1464 Interactive Circuits & Systems Ltd 1465 GN NETTEST Telecom DIV. @@ -6816,7 +7086,7 @@ 0340 PC4800 0350 PC4800 4500 PC4500 - 4800 Cisco Aironet 340 802.11b WLAN Adapter/Aironet PC4800 + 4800 Cisco Aironet 340 802.11b Wireless LAN Adapter/Aironet PC4800 a504 Cisco Aironet Wireless 802.11b a505 Cisco Aironet CB20a 802.11a Wireless LAN Adapter a506 Cisco Aironet Mini PCI b/g @@ -6976,7 +7246,8 @@ 1659 NetXtreme BCM5721 Gigabit Ethernet PCI Express 165d NetXtreme BCM5705M Gigabit Ethernet 165e NetXtreme BCM5705M_2 Gigabit Ethernet - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 166e 570x 10/100 Integrated Controller 1677 NetXtreme BCM5751 Gigabit Ethernet PCI Express 1028 0179 Optiplex GX280 @@ -7059,9 +7330,9 @@ 4403 BCM4402 V.90 56k Modem 4410 BCM4413 iLine32 HomePNA 2.0 4411 BCM4413 V.90 56k modem - 4412 BCM4413 10/100BaseT + 4412 BCM4412 10/100BaseT 4430 BCM44xx CardBus iLine32 HomePNA 2.0 - 4432 BCM44xx CardBus 10/100BaseT + 4432 BCM4432 CardBus 10/100BaseT 4610 BCM4610 Sentry5 PCI to SB Bridge 4611 BCM4610 Sentry5 iLine32 HomePNA 1.0 4612 BCM4610 Sentry5 V.90 56k Modem @@ -7253,7 +7524,10 @@ 2f02 HSF 56k HSFi Data/Fax 2f11 HSF 56k HSFi Modem 8234 RS8234 ATM SAR Controller [ServiceSAR Plus] - 8800 Winfast TV2000 XP + 8800 CX22702 DVB-T 2k/8k + 17de 08a1 XPert DVB-T PCI BDA DVBT 23880 Video Capture + 8802 CX23883 Broadcast Decoder + 17de 08a1 Xpert DVB-T PCI 2388x Transport Stream Capture 14f2 MOBILITY Electronics 0120 EV1000 bridge 0121 EV1000 Parallel port @@ -7326,6 +7600,8 @@ 1008 PCI-1008 151b COMBOX Ltd 151c DIGITAL AUDIO LABS Inc + 0003 Prodif T 2496 + 4000 Prodif 88 151d Fujitsu Computer Products Of America 151e MATRIX Corp 151f TOPIC SEMICONDUCTOR Corp @@ -7466,6 +7742,7 @@ 1575 Voltaire Advanced Data Security Ltd 1576 Viewcast COM 1578 HITT + 5615 VPMK3 [Video Processor Mk III] 1579 Dual Technology Corp 157a Japan Elecronics Ind Inc 157b Star Multimedia Corp @@ -7655,7 +7932,7 @@ 1637 Linksys 3874 Linksys 802.11b WMP11 PCI Wireless card 1638 Standard Microsystems Corp [SMC] - 1100 SMC2602W EZConnect/Addtron AWA-100/Eumitcom PCI WL11000 + 1100 SMC2602W EZConnect / Addtron AWA-100 / Eumitcom PCI WL11000 163c Smart Link Ltd. 3052 SmartLink SmartPCI562 56K Modem 5449 SmartPCI561 Modem @@ -7676,9 +7953,12 @@ 104e 5LS172.6 B&R Dual CAN Interface Card 12d7 5LS172.61 B&R Dual CAN Interface Card 167b ZyDAS Technology Corp. + 2102 ZyDAS ZD1202 + 187e 3406 ZyAIR B-122 CardBus 11Mbs Wireless LAN Card 1681 Hercules # More specs, more accurate desc. 0010 Hercules 3d Prophet II Ultra 64MB [ 350 MHz NV15BR core, 128-bit DDR @ 460 MHz, 1.5v AGP4x ] +1682 XFX Pine Group Inc. 1688 CastleNet Technology Inc. 1170 WLAN 802.11b card 168c Atheros Communications, Inc. @@ -7686,6 +7966,7 @@ 0011 AR5210 802.11a NIC 0012 AR5211 802.11ab NIC 0013 AR5212 802.11abg NIC + 1113 d301 Philips CPWNA100 Wireless CardBus adapter 1186 3202 D-link DWL-G650 B3 Wireless cardbus adapter 1186 3203 DWL-G520 Wireless PCI Adapter 1186 3a13 DWL-G520 Wireless PCI Adapter rev. B @@ -7694,13 +7975,19 @@ 14b7 0a60 8482-WD ORiNOCO 11a/b/g Wireless PCI Adapter 168c 0013 WG511T Wireless CardBus Adapter 168c 1025 DWL-G650B2 Wireless CardBus Adapter + 168c 1027 Netgate NL-3054CB ARIES b/g CardBus Adapter 168c 2026 Netgate 5354MP ARIES a(108Mb turbo)/b/g MiniPCI Adapter + 168c 2041 Netgate 5354MP Plus ARIES2 b/g MiniPCI Adapter + 168c 2042 Netgate 5354MP Plus ARIES2 a/b/g MiniPCI Adapter 1014 AR5212 802.11abg NIC +169c Netcell Corporation + 0044 SyncRAID SR3000/5000 Series SATA RAID Controllers 16a5 Tekram Technology Co.,Ltd. 16ab Global Sun Technology Inc 1100 GL24110P 1101 PLX9052 PCMCIA-to-PCI Wireless LAN 1102 PCMCIA-to-PCI Wireless Network Bridge + 8501 WL-8305 Wireless LAN PCI Adapter 16ae Safenet Inc 1141 SafeXcel-1141 16b4 Aspex Semiconductor Ltd @@ -7715,6 +8002,7 @@ 1e0f LEON2FT Processor 16ec U.S. Robotics 00ff USR997900 10/100 Mbps PCI Network Card + 0116 USR997902 10/100/1000 Mbps PCI Network Card 3685 Wireless Access PCI Adapter Model 022415 16ed Sycron N. V. 1001 UMIO communication card @@ -7783,13 +8071,24 @@ 17cc NetChip Technology, Inc 2280 USB 2.0 17d3 Areca Technology Corp. + 1110 ARC-1110 4-Port PCI-X to SATA RAID Controller + 1120 ARC-1120 8-Port PCI-X to SATA RAID Controller + 1130 ARC-1130 12-Port PCI-X to SATA RAID Controller + 1160 ARC-1160 16-Port PCI-X to SATA RAID Controller + 1210 ARC-1210 4-Port PCI-Express to SATA RAID Controller + 1220 ARC-1220 8-Port PCI-Express to SATA RAID Controller + 1230 ARC-1230 12-Port PCI-Express to SATA RAID Controller + 1260 ARC-1260 16-Port PCI-Express to SATA RAID Controller # S2io ships 10Gb PCI-X Ethernet adapters www.s2io.com 17d5 S2io Inc. + 5831 Xframe 10 Gigabit Ethernet PCI-X + 103c 12d5 HP PCI-X 133MHz 10GbE SR Fiber [AB287A] 17de KWorld Computer Co. Ltd. # http://www.connect3d.com 17ee Connect Components Ltd 17fe Linksys, A Division of Cisco Systems - 2220 [AirConn] INPROCOMM IPN 2220 WLAN Adapter (rev 01) + 2120 WMP11v4 802.11b PCI card + 2220 [AirConn] INPROCOMM IPN 2220 Wireless LAN Adapter (rev 01) 1813 Ambient Technologies Inc 4000 HaM controllerless modem 16be 0001 V9x HAM Data Fax Modem @@ -7797,15 +8096,18 @@ 16be 0002 V9x HAM 1394 1814 RaLink 0101 Wireless PCI Adpator RT2400 / RT2460 + 3306 1113 Quidway WL100M 0201 Ralink RT2500 802.11 Cardbus Reference Card 1371 001e CWC-854 Wireless-G CardBus Adapter 1371 001f CWM-854 Wireless-G Mini PCI Adapter 1371 0020 CWP-854 Wireless-G PCI Adapter + 1458 e381 GN-WMKG 802.11b/g Wireless CardBus Adapter 1820 InfiniCon Systems Inc. 1822 Twinhan Technology Co. Ltd 182d SiteCom Europe BV # HFC-based ISDN card 3069 ISDN PCI DC-105V2 + 9790 WL-121 Wireless Network Adapter 100g+ [Ver.3] 1830 Credence Systems Corporation 183b MikroM GmbH 08a7 MVC100 DVI @@ -7834,6 +8136,7 @@ 18ac DViCO Corporation d810 FusionHDTV 3 Gold 18b8 Ammasso + b001 AMSO 1100 iWARP/RDMA Gigabit Ethernet Coprocessor 18bc Info-Tek Corp. # assigned to Octigabay System, which has been acquired by Cray 18c8 Cray Inc @@ -7851,8 +8154,10 @@ 18fb Resilience Corporation 1924 Level 5 Networks Inc. 1966 Orad Hi-Tec Systems -1975 Pudlis Co. Ltd. + 1975 DVG64 family 1993 Innominate Security Technologies AG +# http://www.progeny.net +19ae Progeny Systems Corporation 1a08 Sierra semiconductor 0000 SC15064 1b13 Jaton Corp @@ -7964,15 +8269,19 @@ 1360 RTL8139 Ethernet 4143 Digital Equipment Corp 4144 Alpha Data + 0044 ADM-XRCIIPro 416c Aladdin Knowledge Systems 0100 AladdinCARD 0200 CPC 4444 Internext Compression Inc 0016 iTVC16 (CX23416) MPEG-2 Encoder 0070 4009 WinTV PVR 250 + 0070 8003 WinTV PVR 150 0803 iTVC15 MPEG-2 Encoder 0070 4000 WinTV PVR-350 0070 4001 WinTV PVR-250 +# video capture card + 1461 a3cf M179 4468 Bridgeport machines 4594 Cogetec Informatique Inc 45fb Baldor Electric Company @@ -8136,6 +8445,7 @@ 8c11 82C270-294 Savage/MX 8c12 86C270-294 Savage/IX-MV 1014 017f ThinkPad T20 + 1179 0001 86C584 SuperSavage/IXC Toshiba 8c13 86C270-294 Savage/IX 1179 0001 Magnia Z310 8c22 SuperSavage MX/128 @@ -8343,6 +8653,7 @@ 8086 1018 PRO/1000 MT Desktop Adapter 1019 82547EI Gigabit Ethernet Controller (LOM) 1458 1019 GA-8IPE1000 Pro2 motherboard (865PE) + 1458 e000 Intel Gigabit Ethernet (Kenai II) 8086 1019 PRO/1000 CT Desktop Connection 8086 301f D865PERL mainboard 8086 3427 S875WP1-E mainboard @@ -8399,6 +8710,7 @@ 1050 82562EZ 10/100 Ethernet Controller 1462 728c 865PE Neo2 (MS-6728) 1462 758c MS-6758 (875P Neo) + 8086 3020 D865PERL mainboard 8086 3427 S875WP1-E mainboard 1051 82801EB/ER (ICH5/ICH5R) integrated LAN Controller 1059 82551QM Ethernet Controller @@ -8745,10 +9057,10 @@ 1462 3370 STAC9721 AC 147b 0507 TH7II-RAID 8086 4557 D815EGEW Mainboard - 2446 Intel 537 [82801BA/BAM AC'97 Modem] + 2446 82801BA/BAM AC'97 Modem 1025 1016 Travelmate 612 TX 104d 80df Vaio PCG-FX403 - 2448 82801 PCI Bridge + 2448 82801 Mobile PCI Bridge 2449 82801BA/BAM/CA/CAM Ethernet Controller 0e11 0012 EtherExpress PRO/100 VM 0e11 0091 EtherExpress PRO/100 VE @@ -8857,7 +9169,8 @@ 1025 005a TravelMate 290 1028 0126 Optiplex GX260 1028 0163 Latitude D505 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1071 8160 MIM2000 1462 5800 845PE Max (MS-6580) 1509 2990 Averatec 5110H laptop @@ -8866,7 +9179,8 @@ 1014 0267 NetVista A30p 1025 005a TravelMate 290 1028 0126 Optiplex GX260 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1071 8160 MIM2000 1458 24c2 GA-8PE667 Ultra 1462 5800 845PE Max (MS-6580) @@ -8876,7 +9190,8 @@ 1025 005a TravelMate 290 1028 0126 Optiplex GX260 1028 0163 Latitude D505 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1071 8160 MIM2000 1462 5800 845PE Max (MS-6580) 1509 2990 Averatec 5110H @@ -8886,57 +9201,63 @@ 1014 0267 NetVista A30p 1025 005a TravelMate 290 1028 0163 Latitude D505 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1071 8160 MIM2000 1458 a002 GA-8PE667 Ultra 1462 5800 845PE Max (MS-6580) 24c6 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) AC'97 Modem Controller 1025 005a TravelMate 290 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1071 8160 MIM2000 24c7 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) USB UHCI Controller #3 1014 0267 NetVista A30p 1025 005a TravelMate 290 1028 0126 Optiplex GX260 1028 0163 Latitude D505 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1071 8160 MIM2000 1462 5800 845PE Max (MS-6580) 1509 2990 Averatec 5110H 4c53 1090 Cx9 / Vx9 mainboard - 24ca 82801DBM (ICH4) Ultra ATA Storage Controller + 24ca 82801DBM (ICH4-M) IDE Controller 1025 005a TravelMate 290 1028 0163 Latitude D505 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1071 8160 MIM2000 - 24cb 82801DB/DBL (ICH4/ICH4-L) UltraATA-100 IDE Controller + 24cb 82801DB (ICH4) IDE Controller 1014 0267 NetVista A30p 1028 0126 Optiplex GX260 1458 24c2 GA-8PE667 Ultra 1462 5800 845PE Max (MS-6580) 4c53 1090 Cx9 / Vx9 mainboard - 24cc 82801DBM LPC Interface Controller - 24cd 82801DB/DBM (ICH4/ICH4-M) USB 2.0 EHCI Controller + 24cc 82801DBM (ICH4-M) LPC Interface Bridge + 24cd 82801DB/DBM (ICH4/ICH4-M) USB2 EHCI Controller 1014 0267 NetVista A30p 1025 005a TravelMate 290 1028 0126 Optiplex GX260 1028 0163 Latitude D505 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 1071 8160 MIM2000 1462 3981 845PE Max (MS-6580) 1509 1968 Averatec 5110H 4c53 1090 Cx9 / Vx9 mainboard 24d0 82801EB/ER (ICH5/ICH5R) LPC Interface Bridge - 24d1 82801EB (ICH5) Serial ATA 150 Storage Controller + 24d1 82801EB (ICH5) SATA Controller 103c 12bc d530 CMT (DG746A) 1458 24d1 GA-8IPE1000 Pro2 motherboard (865PE) 1462 7280 865PE Neo2 (MS-6728) 8086 3427 S875WP1-E mainboard 8086 524c D865PERL mainboard 24d2 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #1 + 1028 0183 PowerEdge 1800 103c 12bc d530 CMT (DG746A) 1043 80a6 P4P800 Mainboard - 1458 24d2 GA-8KNXP motherboard (875P) + 1458 24d2 GA-8IPE1000/8KNXP motherboard 1462 7280 865PE Neo2 (MS-6728) 8086 3427 S875WP1-E mainboard 8086 524c D865PERL mainboard @@ -8947,6 +9268,7 @@ 8086 3427 S875WP1-E mainboard 8086 524c D865PERL mainboard 24d4 82801EB/ER (ICH5/ICH5R) USB UHCI Controller #2 + 1028 0183 PowerEdge 1800 103c 12bc d530 CMT (DG746A) 1043 80a6 P4P800 Mainboard 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) @@ -8956,27 +9278,32 @@ 24d5 82801EB/ER (ICH5/ICH5R) AC'97 Audio Controller 103c 12bc Analog Devices codec [SoundMAX Integrated Digital Audio] 1043 80f3 P4P800 Mainboard - 1458 a002 GA-8KNXP motherboard (875P) +# Again, I suppose they use the same in different subsystems + 1458 a002 GA-8IPE1000/8KNXP motherboard 1462 7280 865PE Neo2 (MS-6728) 8086 a000 D865PERL mainboard + 8086 e000 D865PERL mainboard 24d6 82801EB/ER (ICH5/ICH5R) AC'97 Modem Controller 24d7 82801EB/ER (ICH5/ICH5R) USB UHCI #3 + 1028 0183 PowerEdge 1800 103c 12bc d530 CMT (DG746A) 1043 80a6 P4P800 Mainboard 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) 1462 7280 865PE Neo2 (MS-6728) 8086 3427 S875WP1-E mainboard 8086 524c D865PERL mainboard - 24db 82801EB/ER (ICH5/ICH5R) Ultra ATA 100 Storage Controller + 24db 82801EB/ER (ICH5/ICH5R) IDE Controller 103c 12bc d530 CMT (DG746A) 1043 80a6 P4P800 Mainboard 1458 24d2 GA-8IPE1000 Pro2 motherboard (865PE) 1462 7280 865PE Neo2 (MS-6728) 1462 7580 MSI 875P + 8086 24db P4C800 Mainboard 8086 3427 S875WP1-E mainboard 8086 524c D865PERL mainboard 24dc 82801EB (ICH5) LPC Interface Bridge 24dd 82801EB/ER (ICH5/ICH5R) USB2 EHCI Controller + 1028 0183 PowerEdge 1800 103c 12bc d530 CMT (DG746A) 1043 80a6 P4P800 Mainboard 1458 5006 GA-8IPE1000 Pro2 motherboard (865PE) @@ -8989,7 +9316,7 @@ 1462 7280 865PE Neo2 (MS-6728) 8086 3427 S875WP1-E mainboard 8086 524c D865PERL mainboard - 24df 82801EB (ICH5R) SATA (cc=RAID) + 24df 82801ER (ICH5R) SATA Controller 2500 82820 820 (Camino) Chipset Host Bridge (MCH) 1028 0095 Precision Workstation 220 Chipset 1043 801c P3C-2000 system chipset @@ -9049,8 +9376,8 @@ 2579 82875P Processor to AGP Controller 257b 82875P/E7210 Processor to PCI to CSA Bridge 257e 82875P/E7210 Processor to I/O Memory Interface - 2580 915G/P/GV Processor to I/O Controller - 2581 915G/P/GV PCI Express Root Port + 2580 915G/P/GV/GL/PL/910GL Processor to I/O Controller + 2581 915G/P/GV/GL/PL/910GL PCI Express Root Port 2582 82915G/GV/910GL Express Chipset Family Graphics Controller 1028 1079 Optiplex GX280 2584 925X/XE Memory Controller Hub @@ -9082,40 +9409,40 @@ 25ad 6300ESB USB2 Enhanced Host Controller 25ae 6300ESB 64-bit PCI-X Bridge 25b0 6300ESB SATA RAID Controller - 2600 Server Hub Interface - 2601 Server Hub PCI Express x4 Port D - 2602 Server Hub PCI Express x4 Port C0 - 2603 Server Hub PCI Express x4 Port C1 - 2604 Server Hub PCI Express x4 Port B0 - 2605 Server Hub PCI Express x4 Port B1 - 2606 Server Hub PCI Express x4 Port A0 - 2607 Server Hub PCI Express x4 Port A1 - 2608 Server Hub PCI Express x8 Port C - 2609 Server Hub PCI Express x8 Port B - 260a Server Hub PCI Express x8 Port A - 260c Server Hub IMI Registers - 2610 Server Hub System Bus, Boot, and Interrupt Registers - 2611 Server Hub Address Mapping Registers - 2612 Server Hub RAS Registers - 2613 Server Hub Performance Monitoring Registers - 2614 Server Hub Performance Monitoring Registers - 2615 Server Hub Performance Monitoring Registers - 2617 Server Hub Debug Registers - 2618 Server Hub Debug Registers - 2619 Server Hub Debug Registers - 261a Server Hub Debug Registers - 261b Server Hub Debug Registers - 261c Server Hub Debug Registers - 261d Server Hub Debug Registers - 261e Server Hub Debug Registers - 2620 External Memory Bridge - 2621 External Memory Bridge Control Registers - 2622 External Memory Bridge Memory Interleaving Registers - 2623 External Memory Bridge DDR Initialization and Calibration - 2624 External Memory Bridge Reserved Registers - 2625 External Memory Bridge Reserved Registers - 2626 External Memory Bridge Reserved Registers - 2627 External Memory Bridge Reserved Registers + 2600 E8500 Hub Interface + 2601 E8500 PCI Express x4 Port D + 2602 E8500 PCI Express x4 Port C0 + 2603 E8500 PCI Express x4 Port C1 + 2604 E8500 PCI Express x4 Port B0 + 2605 E8500 PCI Express x4 Port B1 + 2606 E8500 PCI Express x4 Port A0 + 2607 E8500 PCI Express x4 Port A1 + 2608 E8500 PCI Express x8 Port C + 2609 E8500 PCI Express x8 Port B + 260a E8500 PCI Express x8 Port A + 260c E8500 IMI Registers + 2610 E8500 System Bus, Boot, and Interrupt Registers + 2611 E8500 Address Mapping Registers + 2612 E8500 RAS Registers + 2613 E8500 Reserved Registers + 2614 E8500 Reserved Registers + 2615 E8500 Miscellaneous Registers + 2617 E8500 Reserved Registers + 2618 E8500 Reserved Registers + 2619 E8500 Reserved Registers + 261a E8500 Reserved Registers + 261b E8500 Reserved Registers + 261c E8500 Reserved Registers + 261d E8500 Reserved Registers + 261e E8500 Reserved Registers + 2620 E8500 eXternal Memory Bridge + 2621 E8500 XMB Miscellaneous Registers + 2622 E8500 XMB Memory Interleaving Registers + 2623 E8500 XMB DDR Initialization and Calibration + 2624 E8500 XMB Reserved Registers + 2625 E8500 XMB Reserved Registers + 2626 E8500 XMB Reserved Registers + 2627 E8500 XMB Reserved Registers 2640 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge 2641 82801FBM (ICH6M) LPC Interface Bridge 2642 82801FW/FRW (ICH6W/ICH6RW) LPC Interface Bridge @@ -9155,11 +9482,10 @@ 2779 PCI Express Root Port 2782 82915G Express Chipset Family Graphics Controller 2792 Mobile 915GM/GMS/910GML Express Graphics Controller - 27b1 Mobile I/O Controller Hub LPC 27b8 I/O Controller Hub LPC + 27b9 Mobile I/O Controller Hub LPC 27c0 I/O Controller Hub SATA cc=IDE 27c1 I/O Controller Hub SATA cc=AHCI - 27c2 I/O Controller Hub SATA cc=RAID 27c3 I/O Controller Hub SATA cc=RAID 27c4 Mobile I/O Controller Hub SATA cc=IDE 27c5 Mobile I/O Controller Hub SATA cc=AHCI @@ -9184,7 +9510,8 @@ 3200 GD31244 PCI-X SATA HBA 3340 82855PM Processor to I/O Controller 1025 005a TravelMate 290 - 103c 0890 NC6000 laptop + 103c 088c nc8000 laptop + 103c 0890 nc6000 laptop 3341 82855PM Processor to AGP Controller 3575 82830 830 Chipset Host Bridge 1014 021d ThinkPad A/T/X Series @@ -9308,7 +9635,9 @@ 84e4 460GX - 84460GX Memory Data Controller (MDC) 84e6 460GX - 82466GX Wide and fast PCI eXpander Bridge (WXB) 84ea 460GX - 84460GX AGP Bridge (GXB function 1) - 8500 IXP4XX Network Processor family. IXP420/IXP421/IXP422/IXP425/IXC1100 + 8500 IXP4XX - Intel Network Processor family. IXP420, IXP421, IXP422, IXP425 and IXC1100 + 1993 0dee mGuard-PCI AV#1 + 1993 0def mGuard-PCI AV#0 9000 IXP2000 Family Network Processor 9001 IXP2400 Network Processor 9004 IXP2800 Network Processor @@ -9325,7 +9654,6 @@ b154 21154 PCI-to-PCI Bridge b555 21555 Non transparent PCI-to-PCI Bridge 12d9 000a PCI VoIP Gateway - 1331 0030 ENP-2611 4c53 1050 CT7 mainboard 4c53 1051 CE7 mainboard e4bf 1000 CC8-1-BLUES @@ -9514,8 +9842,10 @@ 9005 0284 Tomcat 0285 AAC-RAID 0e11 0295 SATA 6Ch (Bearcat) + 1014 02f2 ServeRAID 8i 1028 0287 PowerEdge Expandable RAID Controller 320/DC 1028 0291 CERC SATA RAID 2 PCI SATA 6ch (DellCorsair) + 103c 3227 AAR-2610SA 17aa 0286 Legend S220 (Legend Crusader) 17aa 0287 Legend S230 (Legend Vulcan) 9005 0285 2200S (Vulcan) @@ -9627,6 +9957,10 @@ d4d4 Dy4 Systems Inc d531 I+ME ACTIA GmbH d84d Exsys dead Indigita Corporation +deaf Middle Digital Inc. + 9050 PC Weasel Virtual VGA + 9051 PC Weasel Serial Port + 9052 PC Weasel Watchdog Timer e000 Winbond e000 W89C940 # see also : http://www.schoenfeld.de/inside/Inside_CWMK3.txt maybe a misuse of TJN id or it use the TJN 3XX chip for other applic @@ -9660,13 +9994,6 @@ eace Endace Measurement Systems, Ltd ec80 Belkin Corporation ec00 F5D6000 ecc0 Echo Digital Audio Corporation - 0050 Gina24_301 - 0051 Gina24_361 - 0060 Layla24 - 0070 Mona_301_80 - 0071 Mona_301_66 - 0072 Mona_361 - 0080 Mia edd8 ARK Logic Inc a091 1000PV [Stingray] a099 2000PV [Stingray] diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 379fb2a6f72ac..6f0edadd132cf 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2,6 +2,7 @@ * probe.c - PCI detection and setup code */ +#include <linux/kernel.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/pci.h> @@ -9,14 +10,6 @@ #include <linux/module.h> #include <linux/cpumask.h> -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ #define CARDBUS_RESERVE_BUSNR 3 #define PCI_CFG_SPACE_SIZE 256 @@ -80,7 +73,7 @@ void pci_remove_legacy_files(struct pci_bus *bus) { return; } */ static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, char *buf) { - cpumask_t cpumask = pcibus_to_cpumask((to_pci_bus(class_dev))->number); + cpumask_t cpumask = pcibus_to_cpumask(to_pci_bus(class_dev)); int ret; ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask); @@ -422,8 +415,8 @@ int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); - DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", - pci_name(dev), buses & 0xffffff, pass); + pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n", + pci_name(dev), buses & 0xffffff, pass); /* Disable MasterAbortMode during probing to avoid reporting of bus errors (in some architectures) */ @@ -559,8 +552,8 @@ static int pci_setup_device(struct pci_dev * dev) dev->class = class; class >>= 8; - DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number, - dev->devfn, dev->vendor, dev->device, class, dev->hdr_type); + pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev), + dev->vendor, dev->device, class, dev->hdr_type); /* "Unknown power state" */ dev->current_state = 4; @@ -815,7 +808,7 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) unsigned int devfn, pass, max = bus->secondary; struct pci_dev *dev; - DBG("Scanning bus %02x\n", bus->number); + pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number); /* Go find them, Rover! */ for (devfn = 0; devfn < 0x100; devfn += 8) @@ -825,7 +818,7 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) * After performing arch-dependent fixup of the bus, look behind * all PCI-to-PCI bridges on this bus. */ - DBG("Fixups for bus %02x\n", bus->number); + pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number); pcibios_fixup_bus(bus); for (pass=0; pass < 2; pass++) list_for_each_entry(dev, &bus->devices, bus_list) { @@ -841,7 +834,8 @@ unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) * * Return how far we've got finding sub-buses. */ - DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max); + pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n", + pci_domain_nr(bus), bus->number, max); return max; } @@ -880,7 +874,7 @@ struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, if (pci_find_bus(pci_domain_nr(b), bus)) { /* If we already got to this bus through a different bridge, ignore it */ - DBG("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); + pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus); goto err_out; } list_add_tail(&b->node, &pci_root_buses); diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c index b53bb859ce91c..84cc4f620d8d4 100644 --- a/drivers/pci/proc.c +++ b/drivers/pci/proc.c @@ -313,13 +313,10 @@ static void *pci_seq_start(struct seq_file *m, loff_t *pos) struct pci_dev *dev = NULL; loff_t n = *pos; - dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); - while (n--) { - dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev); - if (dev == NULL) - goto exit; + for_each_pci_dev(dev) { + if (!n--) + break; } -exit: return dev; } diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index eef35c8a71e59..1cfe9538fd19f 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -19,8 +19,6 @@ #include <linux/init.h> #include <linux/delay.h> -#undef DEBUG - /* Deal with broken BIOS'es that neglect to enable passive release, which can cause problems in combination with the 82441FX/PPro MTRRs */ static void __devinit quirk_passive_release(struct pci_dev *dev) @@ -541,7 +539,7 @@ static void __devinit quirk_cardbus_legacy(struct pci_dev *dev) return; pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); } -DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy ); +DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy); /* * Following the PCI ordering rules is optional on the AMD762. I'm not @@ -659,7 +657,7 @@ static void __devinit quirk_ide_bases(struct pci_dev *dev) printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n", first_bar, last_bar, pci_name(dev)); } -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases ); +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases); /* * Ensure C0 rev restreaming is off. This is normally done by @@ -700,7 +698,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quir /* * Serverworks CSB5 IDE does not fully support native mode */ -static void __init quirk_svwks_csb5ide(struct pci_dev *pdev) +static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev) { u8 prog; pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); @@ -787,6 +785,7 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev) if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) switch (dev->subsystem_device) { case 0x1751: /* M2N notebook */ + case 0x1821: /* M5N notebook */ asus_hides_smbus = 1; } if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c index 3f70e2ffe9261..96f077f9a6594 100644 --- a/drivers/pci/remove.c +++ b/drivers/pci/remove.c @@ -2,14 +2,6 @@ #include <linux/module.h> #include "pci.h" -#undef DEBUG - -#ifdef DEBUG -#define DBG(x...) printk(x) -#else -#define DBG(x...) -#endif - static void pci_free_resources(struct pci_dev *dev) { int i; diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c index 82d877c4051f7..1ba84be0b4c0f 100644 --- a/drivers/pci/setup-bus.c +++ b/drivers/pci/setup-bus.c @@ -29,9 +29,9 @@ #define DEBUG_CONFIG 1 #if DEBUG_CONFIG -# define DBGC(args) printk args +#define DBG(x...) printk(x) #else -# define DBGC(args) +#define DBG(x...) #endif #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1)) @@ -151,8 +151,7 @@ pci_setup_bridge(struct pci_bus *bus) struct pci_bus_region region; u32 l, io_upper16; - DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n", - bus->number, pci_name(bridge))); + DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge)); /* Set up the top and bottom of the PCI I/O segment for this bus. */ pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); @@ -163,14 +162,14 @@ pci_setup_bridge(struct pci_bus *bus) l |= region.end & 0xf000; /* Set up upper 16 bits of I/O base/limit. */ io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); - DBGC((KERN_INFO " IO window: %04lx-%04lx\n", - region.start, region.end)); + DBG(KERN_INFO " IO window: %04lx-%04lx\n", + region.start, region.end); } else { /* Clear upper 16 bits of I/O base/limit. */ io_upper16 = 0; l = 0x00f0; - DBGC((KERN_INFO " IO window: disabled.\n")); + DBG(KERN_INFO " IO window: disabled.\n"); } /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); @@ -185,12 +184,12 @@ pci_setup_bridge(struct pci_bus *bus) if (bus->resource[1]->flags & IORESOURCE_MEM) { l = (region.start >> 16) & 0xfff0; l |= region.end & 0xfff00000; - DBGC((KERN_INFO " MEM window: %08lx-%08lx\n", - region.start, region.end)); + DBG(KERN_INFO " MEM window: %08lx-%08lx\n", + region.start, region.end); } else { l = 0x0000fff0; - DBGC((KERN_INFO " MEM window: disabled.\n")); + DBG(KERN_INFO " MEM window: disabled.\n"); } pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); @@ -204,12 +203,12 @@ pci_setup_bridge(struct pci_bus *bus) if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { l = (region.start >> 16) & 0xfff0; l |= region.end & 0xfff00000; - DBGC((KERN_INFO " PREFETCH window: %08lx-%08lx\n", - region.start, region.end)); + DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n", + region.start, region.end); } else { l = 0x0000fff0; - DBGC((KERN_INFO " PREFETCH window: disabled.\n")); + DBG(KERN_INFO " PREFETCH window: disabled.\n"); } pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c index d02bebfa25d43..a251289c9958e 100644 --- a/drivers/pci/setup-irq.c +++ b/drivers/pci/setup-irq.c @@ -18,14 +18,6 @@ #include <linux/cache.h> -#define DEBUG_CONFIG 0 -#if DEBUG_CONFIG -# define DBGC(args) printk args -#else -# define DBGC(args) -#endif - - static void __init pdev_fixup_irq(struct pci_dev *dev, u8 (*swizzle)(struct pci_dev *, u8 *), @@ -53,8 +45,8 @@ pdev_fixup_irq(struct pci_dev *dev, irq = 0; dev->irq = irq; - DBGC((KERN_ERR "PCI fixup irq: (%s) got %d\n", - dev->dev.kobj.name, dev->irq)); + pr_debug("PCI: fixup irq: (%s) got %d\n", + dev->dev.kobj.name, dev->irq); /* Always tell the device, so the driver knows what is the real IRQ to use; the device does not use it. */ diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c index 26a1d767c449c..1ca21d2ba11c6 100644 --- a/drivers/pci/setup-res.c +++ b/drivers/pci/setup-res.c @@ -25,13 +25,6 @@ #include <linux/slab.h> #include "pci.h" -#define DEBUG_CONFIG 0 -#if DEBUG_CONFIG -# define DBGC(args) printk args -#else -# define DBGC(args) -#endif - static void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno) @@ -42,10 +35,9 @@ pci_update_resource(struct pci_dev *dev, struct resource *res, int resno) pcibios_resource_to_bus(dev, ®ion, res); - DBGC((KERN_ERR " got res [%lx:%lx] bus [%lx:%lx] flags %lx for " - "BAR %d of %s\n", res->start, res->end, - region.start, region.end, res->flags, - resno, pci_name(dev))); + pr_debug(" got res [%lx:%lx] bus [%lx:%lx] flags %lx for " + "BAR %d of %s\n", res->start, res->end, + region.start, region.end, res->flags, resno, pci_name(dev)); new = region.start | (res->flags & PCI_REGION_FLAG_MASK); if (res->flags & IORESOURCE_IO) @@ -60,7 +52,7 @@ pci_update_resource(struct pci_dev *dev, struct resource *res, int resno) reg = dev->rom_base_reg; } else { /* Hmm, non-standard resource. */ - BUG(); + return; /* kill uninitialised var warning */ } @@ -85,9 +77,9 @@ pci_update_resource(struct pci_dev *dev, struct resource *res, int resno) } } res->flags &= ~IORESOURCE_UNSET; - DBGC((KERN_INFO "PCI: moved device %s resource %d (%lx) to %x\n", + pr_debug("PCI: moved device %s resource %d (%lx) to %x\n", pci_name(dev), resno, res->flags, - new & ~PCI_REGION_FLAG_MASK)); + new & ~PCI_REGION_FLAG_MASK); } int __devinit diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index 49071f2394527..201c3b9924f4d 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -2194,14 +2194,6 @@ static int __init serial8250_console_init(void) } console_initcall(serial8250_console_init); -static int __init serial8250_late_console_init(void) -{ - if (!(serial8250_console.flags & CON_ENABLED)) - register_console(&serial8250_console); - return 0; -} -late_initcall(serial8250_late_console_init); - static int __init find_port(struct uart_port *p) { int line; diff --git a/drivers/serial/m32r_sio.c b/drivers/serial/m32r_sio.c index bb6509f5fe8bb..08d61f13edc61 100644 --- a/drivers/serial/m32r_sio.c +++ b/drivers/serial/m32r_sio.c @@ -54,13 +54,6 @@ #include "m32r_sio_reg.h" /* - * Configuration: - * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option - * is unsafe when used on edge-triggered interrupts. - */ -unsigned int share_irqs_sio = M32R_SIO_SHARE_IRQS; - -/* * Debugging. */ #if 0 @@ -86,15 +79,36 @@ unsigned int share_irqs_sio = M32R_SIO_SHARE_IRQS; #include <asm/serial.h> +/* Standard COM flags */ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + /* * SERIAL_PORT_DFNS tells us about built-in ports that have no * standard enumeration mechanism. Platforms that can find all * serial ports via mechanisms like ACPI or PCI need not supply it. */ -#ifndef SERIAL_PORT_DFNS -#define SERIAL_PORT_DFNS +#undef SERIAL_PORT_DFNS +#if defined(CONFIG_PLAT_USRV) + +#define SERIAL_PORT_DFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \ + { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */ + +#else /* !CONFIG_PLAT_USRV */ + +#if defined(CONFIG_SERIAL_M32R_PLDSIO) +#define SERIAL_PORT_DFNS \ + { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \ + STD_COM_FLAGS }, /* ttyS0 */ +#else +#define SERIAL_PORT_DFNS \ + { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \ + STD_COM_FLAGS }, /* ttyS0 */ #endif +#endif /* !CONFIG_PLAT_USRV */ + static struct old_serial_port old_serial_port[] = { SERIAL_PORT_DFNS /* defined in asm/serial.h */ }; @@ -581,10 +595,7 @@ static void serial_unlink_irq_chain(struct uart_sio_port *up) } /* - * This function is used to handle ports that do not have an - * interrupt. This doesn't work very well for 16450's, but gives - * barely passable results for a 16550A. (Although at the expense - * of much CPU overhead). + * This function is used to handle ports that do not have an interrupt. */ static void m32r_sio_timeout(unsigned long data) { @@ -966,7 +977,7 @@ static struct uart_ops m32r_sio_pops = { static struct uart_sio_port m32r_sio_ports[UART_NR]; -static void __init m32r_sio_isa_init_ports(void) +static void __init m32r_sio_init_ports(void) { struct uart_sio_port *up; static int first = 1; @@ -986,8 +997,6 @@ static void __init m32r_sio_isa_init_ports(void) up->port.iotype = old_serial_port[i].io_type; up->port.regshift = old_serial_port[i].iomem_reg_shift; up->port.ops = &m32r_sio_pops; - if (share_irqs_sio) - up->port.flags |= UPF_SHARE_IRQ; } } @@ -995,7 +1004,7 @@ static void __init m32r_sio_register_ports(struct uart_driver *drv) { int i; - m32r_sio_isa_init_ports(); + m32r_sio_init_ports(); for (i = 0; i < UART_NR; i++) { struct uart_sio_port *up = &m32r_sio_ports[i]; @@ -1129,7 +1138,7 @@ static int __init m32r_sio_console_init(void) { sio_reset(); sio_init(); - m32r_sio_isa_init_ports(); + m32r_sio_init_ports(); register_console(&m32r_sio_console); return 0; } @@ -1151,81 +1160,6 @@ static struct uart_driver m32r_sio_reg = { .cons = M32R_SIO_CONSOLE, }; -/* - * register_serial and unregister_serial allows for 16x50 serial ports to be - * configured at run-time, to support PCMCIA modems. - */ - -static int __register_m32r_sio(struct serial_struct *req, int line) -{ - struct uart_port port; - - port.iobase = req->port; - port.membase = req->iomem_base; - port.irq = req->irq; - port.uartclk = req->baud_base * 16; - port.fifosize = req->xmit_fifo_size; - port.regshift = req->iomem_reg_shift; - port.iotype = req->io_type; - port.flags = req->flags | UPF_BOOT_AUTOCONF; - port.mapbase = req->iomap_base; - port.line = line; - - if (share_irqs_sio) - port.flags |= UPF_SHARE_IRQ; - - if (HIGH_BITS_OFFSET) - port.iobase |= (long) req->port_high << HIGH_BITS_OFFSET; - - /* - * If a clock rate wasn't specified by the low level - * driver, then default to the standard clock rate. - */ - if (port.uartclk == 0) - port.uartclk = BASE_BAUD * 16; - - return uart_register_port(&m32r_sio_reg, &port); -} - -/** - * register_m32r_sio - configure a 16x50 serial port at runtime - * @req: request structure - * - * Configure the serial port specified by the request. If the - * port exists and is in use an error is returned. If the port - * is not currently in the table it is added. - * - * The port is then probed and if necessary the IRQ is autodetected - * If this fails an error is returned. - * - * On success the port is ready to use and the line number is returned. - */ -int register_m32r_sio(struct serial_struct *req) -{ - return __register_m32r_sio(req, -1); -} - -int __init early_serial_setup(struct uart_port *port) -{ - m32r_sio_isa_init_ports(); - m32r_sio_ports[port->line].port = *port; - m32r_sio_ports[port->line].port.ops = &m32r_sio_pops; - - return 0; -} - -/** - * unregister_m32r_sio - remove a 16x50 serial port at runtime - * @line: serial line number - * - * Remove one serial port. This may be called from interrupt - * context. - */ -void unregister_m32r_sio(int line) -{ - uart_unregister_port(&m32r_sio_reg, line); -} - /** * m32r_sio_suspend_port - suspend one serial port * @line: serial line number @@ -1252,8 +1186,7 @@ static int __init m32r_sio_init(void) { int ret, i; - printk(KERN_INFO "Serial: M32R SIO driver $Revision: 1.9 $ " - "IRQ sharing %sabled\n", share_irqs_sio ? "en" : "dis"); + printk(KERN_INFO "Serial: M32R SIO driver $Revision: 1.11 $ "); for (i = 0; i < NR_IRQS; i++) spin_lock_init(&irq_lists[i].lock); @@ -1278,14 +1211,8 @@ static void __exit m32r_sio_exit(void) module_init(m32r_sio_init); module_exit(m32r_sio_exit); -EXPORT_SYMBOL(register_m32r_sio); -EXPORT_SYMBOL(unregister_m32r_sio); EXPORT_SYMBOL(m32r_sio_suspend_port); EXPORT_SYMBOL(m32r_sio_resume_port); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Generic M32R SIO serial driver $Revision: 1.9 $"); - -module_param(share_irqs_sio, bool, 0400); -MODULE_PARM_DESC(share_irqs_sio, "Share IRQs with other non-M32R SIO devices" - " (unsafe)"); +MODULE_DESCRIPTION("Generic M32R SIO serial driver $Revision: 1.11 $"); diff --git a/include/asm-arm/arch-integrator/lm.h b/include/asm-arm/arch-integrator/lm.h index d792b112974cd..28186b6f2c096 100644 --- a/include/asm-arm/arch-integrator/lm.h +++ b/include/asm-arm/arch-integrator/lm.h @@ -10,7 +10,7 @@ struct lm_driver { struct device_driver drv; int (*probe)(struct lm_device *); void (*remove)(struct lm_device *); - int (*suspend)(struct lm_device *, u32); + int (*suspend)(struct lm_device *, pm_message_t); int (*resume)(struct lm_device *); }; diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h index 4f69467327d1e..324db06b5dd4b 100644 --- a/include/asm-arm/arch-pxa/corgi.h +++ b/include/asm-arm/arch-pxa/corgi.h @@ -100,40 +100,6 @@ /* - * Corgi Parameter Area Definitions - */ -#define FLASH_MEM_BASE 0xa0000a00 -#define FLASH_MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 ) | ( b << 8 ) | a ) - -#define FLASH_COMADJ_MAJIC FLASH_MAGIC_CHG('C','M','A','D') -#define FLASH_COMADJ_MAGIC_ADR 0x00 -#define FLASH_COMADJ_DATA_ADR 0x04 - -#define FLASH_PHAD_MAJIC FLASH_MAGIC_CHG('P','H','A','D') -#define FLASH_PHAD_MAGIC_ADR 0x38 -#define FLASH_PHAD_DATA_ADR 0x3C - -struct sharpsl_flash_param_info { - unsigned int comadj_keyword; - unsigned int comadj; - - unsigned int uuid_keyword; - unsigned char uuid[16]; - - unsigned int touch_keyword; - unsigned int touch1; - unsigned int touch2; - unsigned int touch3; - unsigned int touch4; - - unsigned int adadj_keyword; - unsigned int adadj; - - unsigned int phad_keyword; - unsigned int phadadj; -}; - -/* * Shared data structures */ extern struct platform_device corgiscoop_device; diff --git a/include/asm-arm/arch-pxa/poodle.h b/include/asm-arm/arch-pxa/poodle.h index 027573d38ee47..58bda9d571a5a 100644 --- a/include/asm-arm/arch-pxa/poodle.h +++ b/include/asm-arm/arch-pxa/poodle.h @@ -67,45 +67,4 @@ #define POODLE_SCOOP_IO_DIR ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT ) #define POODLE_SCOOP_IO_OUT ( 0 ) -/* - * Flash Memory mappings - * - * We have the following mapping: - * phys virt - * boot ROM 00000000 ef800000 - */ -#define FLASH_MEM_BASE 0xa0000a00 -#define FLASH_DATA(adr) (*(volatile unsigned int*)(FLASH_MEM_BASE+(adr))) -#define FLASH_DATA_F(adr) (*(volatile float32 *)(FLASH_MEM_BASE+(adr))) -#define FLASH_MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 ) | ( b << 8 ) | a ) - -/* COMADJ */ -#define FLASH_COMADJ_MAJIC FLASH_MAGIC_CHG('C','M','A','D') -#define FLASH_COMADJ_MAGIC_ADR 0x00 -#define FLASH_COMADJ_DATA_ADR 0x04 - -/* UUID */ -#define FLASH_UUID_MAJIC FLASH_MAGIC_CHG('U','U','I','D') -#define FLASH_UUID_MAGIC_ADR 0x08 -#define FLASH_UUID_DATA_ADR 0x0C - -/* TOUCH PANEL */ -#define FLASH_TOUCH_MAJIC FLASH_MAGIC_CHG('T','U','C','H') -#define FLASH_TOUCH_MAGIC_ADR 0x1C -#define FLASH_TOUCH_XP_DATA_ADR 0x20 -#define FLASH_TOUCH_YP_DATA_ADR 0x24 -#define FLASH_TOUCH_XD_DATA_ADR 0x28 -#define FLASH_TOUCH_YD_DATA_ADR 0x2C - -/* AD */ -#define FLASH_AD_MAJIC FLASH_MAGIC_CHG('B','V','A','D') -#define FLASH_AD_MAGIC_ADR 0x30 -#define FLASH_AD_DATA_ADR 0x34 - -/* PHAD */ -#define FLASH_PHAD_MAJIC FLASH_MAGIC_CHG('P','H','A','D') -#define FLASH_PHAD_MAGIC_ADR 0x38 -#define FLASH_PHAD_DATA_ADR 0x3C - - #endif /* __ASM_ARCH_POODLE_H */ diff --git a/include/asm-arm/arch-sa1100/collie.h b/include/asm-arm/arch-sa1100/collie.h index 01e60d7c30f68..d49e5ff63ca43 100644 --- a/include/asm-arm/arch-sa1100/collie.h +++ b/include/asm-arm/arch-sa1100/collie.h @@ -66,34 +66,6 @@ #define COLLIE_LCM_IRQ_GPIO_nSD_DETECT IRQ_LOCOMO_GPIO13 #define COLLIE_LCM_IRQ_GPIO_nSD_WP IRQ_LOCOMO_GPIO14 -/* - * Flash Memory mappings - * - */ - -#define FLASH_MEM_BASE 0xe8ffc000 -#define FLASH_DATA(adr) (*(volatile unsigned int*)(FLASH_MEM_BASE+(adr))) -#define FLASH_DATA_F(adr) (*(volatile float32 *)(FLASH_MEM_BASE+(adr))) -#define FLASH_MAGIC_CHG(a,b,c,d) ( ( d << 24 ) | ( c << 16 ) | ( b << 8 ) | a ) - -// COMADJ -#define FLASH_COMADJ_MAJIC FLASH_MAGIC_CHG('C','M','A','D') -#define FLASH_COMADJ_MAGIC_ADR 0x00 -#define FLASH_COMADJ_DATA_ADR 0x04 - -// TOUCH PANEL -#define FLASH_TOUCH_MAJIC FLASH_MAGIC_CHG('T','U','C','H') -#define FLASH_TOUCH_MAGIC_ADR 0x1C -#define FLASH_TOUCH_XP_DATA_ADR 0x20 -#define FLASH_TOUCH_YP_DATA_ADR 0x24 -#define FLASH_TOUCH_XD_DATA_ADR 0x28 -#define FLASH_TOUCH_YD_DATA_ADR 0x2C - -// AD -#define FLASH_AD_MAJIC FLASH_MAGIC_CHG('B','V','A','D') -#define FLASH_AD_MAGIC_ADR 0x30 -#define FLASH_AD_DATA_ADR 0x34 - /* GPIO's on the TC35143AF (Toshiba Analog Frontend) */ #define COLLIE_TC35143_GPIO_VERSION0 UCB_IO_0 /* GPIO0=Version */ #define COLLIE_TC35143_GPIO_TBL_CHK UCB_IO_1 /* GPIO1=TBL_CHK */ diff --git a/include/asm-arm/hardware/amba.h b/include/asm-arm/hardware/amba.h index 0cc74f7f7e0e0..51e6e54b2aa15 100644 --- a/include/asm-arm/hardware/amba.h +++ b/include/asm-arm/hardware/amba.h @@ -31,7 +31,7 @@ struct amba_driver { int (*probe)(struct amba_device *, void *); int (*remove)(struct amba_device *); void (*shutdown)(struct amba_device *); - int (*suspend)(struct amba_device *, u32); + int (*suspend)(struct amba_device *, pm_message_t); int (*resume)(struct amba_device *); struct amba_id *id_table; }; diff --git a/include/asm-arm/hardware/locomo.h b/include/asm-arm/hardware/locomo.h index 5f9218c151429..5f10048ec54e7 100644 --- a/include/asm-arm/hardware/locomo.h +++ b/include/asm-arm/hardware/locomo.h @@ -181,7 +181,7 @@ struct locomo_driver { unsigned int devid; int (*probe)(struct locomo_dev *); int (*remove)(struct locomo_dev *); - int (*suspend)(struct locomo_dev *, u32); + int (*suspend)(struct locomo_dev *, pm_message_t); int (*resume)(struct locomo_dev *); }; diff --git a/include/asm-arm/hardware/sa1111.h b/include/asm-arm/hardware/sa1111.h index 8fd4f528c38df..319aea064c367 100644 --- a/include/asm-arm/hardware/sa1111.h +++ b/include/asm-arm/hardware/sa1111.h @@ -567,7 +567,7 @@ struct sa1111_driver { unsigned int devid; int (*probe)(struct sa1111_dev *); int (*remove)(struct sa1111_dev *); - int (*suspend)(struct sa1111_dev *, u32); + int (*suspend)(struct sa1111_dev *, pm_message_t); int (*resume)(struct sa1111_dev *); }; diff --git a/include/asm-arm/mach/sharpsl_param.h b/include/asm-arm/mach/sharpsl_param.h new file mode 100644 index 0000000000000..7a24ecf042200 --- /dev/null +++ b/include/asm-arm/mach/sharpsl_param.h @@ -0,0 +1,37 @@ +/* + * Hardware parameter area specific to Sharp SL series devices + * + * Copyright (c) 2005 Richard Purdie + * + * Based on Sharp's 2.4 kernel patches + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +struct sharpsl_param_info { + unsigned int comadj_keyword; + unsigned int comadj; + + unsigned int uuid_keyword; + unsigned char uuid[16]; + + unsigned int touch_keyword; + unsigned int touch_xp; + unsigned int touch_yp; + unsigned int touch_xd; + unsigned int touch_yd; + + unsigned int adadj_keyword; + unsigned int adadj; + + unsigned int phad_keyword; + unsigned int phadadj; +} __attribute__((packed)); + + +extern struct sharpsl_param_info sharpsl_param; +extern void sharpsl_save_param(void); + diff --git a/include/asm-i386/topology.h b/include/asm-i386/topology.h index 63e5cfc3ee6cb..98f9e6850cbab 100644 --- a/include/asm-i386/topology.h +++ b/include/asm-i386/topology.h @@ -60,11 +60,12 @@ static inline int node_to_first_cpu(int node) return first_cpu(mask); } -/* Returns the number of the node containing PCI bus 'bus' */ -static inline cpumask_t pcibus_to_cpumask(int bus) +/* Returns the number of the node containing PCI bus number 'busnr' */ +static inline cpumask_t __pcibus_to_cpumask(int busnr) { - return node_to_cpumask(mp_bus_id_to_node[bus]); + return node_to_cpumask(mp_bus_id_to_node[busnr]); } +#define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus->number) /* sched_domains SD_NODE_INIT for NUMAQ machines */ #define SD_NODE_INIT (struct sched_domain) { \ diff --git a/include/asm-m32r/serial.h b/include/asm-m32r/serial.h index d0e56b1bf4511..1bf480f58493e 100644 --- a/include/asm-m32r/serial.h +++ b/include/asm-m32r/serial.h @@ -1,47 +1,10 @@ #ifndef _ASM_M32R_SERIAL_H #define _ASM_M32R_SERIAL_H -/* - * include/asm-m32r/serial.h - */ +/* include/asm-m32r/serial.h */ #include <linux/config.h> -#include <asm/m32r.h> -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD ( 1843200 / 16 ) - -/* Standard COM flags */ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) - -/* Standard PORT definitions */ -#if defined(CONFIG_PLAT_USRV) - -#define STD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */ - -#else /* !CONFIG_PLAT_USRV */ - -#if defined(CONFIG_SERIAL_M32R_PLDSIO) -#define STD_SERIAL_PORT_DEFNS \ - { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \ - STD_COM_FLAGS }, /* ttyS0 */ -#else -#define STD_SERIAL_PORT_DEFNS \ - { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \ - STD_COM_FLAGS }, /* ttyS0 */ -#endif - -#endif /* !CONFIG_PLAT_USRV */ - -#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS +#define BASE_BAUD 115200 #endif /* _ASM_M32R_SERIAL_H */ diff --git a/include/asm-parisc/unaligned.h b/include/asm-parisc/unaligned.h index 0896a9f66529d..53c905838d933 100644 --- a/include/asm-parisc/unaligned.h +++ b/include/asm-parisc/unaligned.h @@ -1,7 +1,7 @@ #ifndef _ASM_PARISC_UNALIGNED_H_ #define _ASM_PARISC_UNALIGNED_H_ -#include <asm-parisc/unaligned.h> +#include <asm-generic/unaligned.h> #ifdef __KERNEL__ struct pt_regs; diff --git a/include/asm-sparc/pgtable.h b/include/asm-sparc/pgtable.h index 3d2418c28ff58..373a6c327590d 100644 --- a/include/asm-sparc/pgtable.h +++ b/include/asm-sparc/pgtable.h @@ -150,6 +150,7 @@ BTFIXUPDEF_CALL_CONST(unsigned long, pgd_page, pgd_t) BTFIXUPDEF_SETHI(none_mask) BTFIXUPDEF_CALL_CONST(int, pte_present, pte_t) BTFIXUPDEF_CALL(void, pte_clear, pte_t *) +BTFIXUPDEF_CALL(int, pte_read, pte_t) extern __inline__ int pte_none(pte_t pte) { @@ -158,6 +159,7 @@ extern __inline__ int pte_none(pte_t pte) #define pte_present(pte) BTFIXUP_CALL(pte_present)(pte) #define pte_clear(mm,addr,pte) BTFIXUP_CALL(pte_clear)(pte) +#define pte_read(pte) BTFIXUP_CALL(pte_read)(pte) BTFIXUPDEF_CALL_CONST(int, pmd_bad, pmd_t) BTFIXUPDEF_CALL_CONST(int, pmd_present, pmd_t) @@ -186,31 +188,10 @@ BTFIXUPDEF_CALL(void, pgd_clear, pgd_t *) * The following only work if pte_present() is true. * Undefined behaviour if not.. */ -BTFIXUPDEF_HALF(pte_readi) BTFIXUPDEF_HALF(pte_writei) BTFIXUPDEF_HALF(pte_dirtyi) BTFIXUPDEF_HALF(pte_youngi) -extern int pte_read(pte_t pte) __attribute_const__; -extern __inline__ int pte_read(pte_t pte) -{ - switch (sparc_cpu_model){ - case sun4: - case sun4c: - return pte_val(pte) & BTFIXUP_HALF(pte_readi); - case sun4d: - case sun4e: - case sun4m: - return !(pte_val(pte) & BTFIXUP_HALF(pte_readi)); - /* pacify gcc warnings */ - case sun4u: - case sun_unknown: - case ap1000: - default: - return 0; - } -} - extern int pte_write(pte_t pte) __attribute_const__; extern __inline__ int pte_write(pte_t pte) { diff --git a/include/asm-sparc64/cacheflush.h b/include/asm-sparc64/cacheflush.h index f1f8661cf83a8..86f02937ff1b7 100644 --- a/include/asm-sparc64/cacheflush.h +++ b/include/asm-sparc64/cacheflush.h @@ -2,6 +2,17 @@ #define _SPARC64_CACHEFLUSH_H #include <linux/config.h> +#include <asm/page.h> + +/* Flushing for D-cache alias handling is only needed if + * the page size is smaller than 16K. + */ +#if PAGE_SHIFT < 14 +#define DCACHE_ALIASING_POSSIBLE +#endif + +#ifndef __ASSEMBLY__ + #include <linux/mm.h> /* Cache flush operations. */ @@ -20,9 +31,9 @@ * module load, so we need this. */ extern void flush_icache_range(unsigned long start, unsigned long end); +extern void __flush_icache_page(unsigned long); extern void __flush_dcache_page(void *addr, int flush_icache); -extern void __flush_icache_page(unsigned long); extern void flush_dcache_page_impl(struct page *page); #ifdef CONFIG_SMP extern void smp_flush_dcache_page_impl(struct page *page, int cpu); @@ -33,6 +44,7 @@ extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page); #endif extern void __flush_dcache_range(unsigned long start, unsigned long end); +extern void flush_dcache_page(struct page *page); #define flush_icache_page(vma, pg) do { } while(0) #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) @@ -49,11 +61,12 @@ extern void __flush_dcache_range(unsigned long start, unsigned long end); memcpy(dst, src, len); \ } while (0) -extern void flush_dcache_page(struct page *page); #define flush_dcache_mmap_lock(mapping) do { } while (0) #define flush_dcache_mmap_unlock(mapping) do { } while (0) #define flush_cache_vmap(start, end) do { } while (0) #define flush_cache_vunmap(start, end) do { } while (0) +#endif /* !__ASSEMBLY__ */ + #endif /* _SPARC64_CACHEFLUSH_H */ diff --git a/include/asm-sparc64/checksum.h b/include/asm-sparc64/checksum.h index 91136a643c27f..dc8bed246fc98 100644 --- a/include/asm-sparc64/checksum.h +++ b/include/asm-sparc64/checksum.h @@ -38,47 +38,44 @@ extern unsigned int csum_partial(const unsigned char * buff, int len, unsigned i * here even more important to align src and dst on a 32-bit (or even * better 64-bit) boundary */ -extern unsigned int csum_partial_copy_sparc64(const unsigned char *src, unsigned char *dst, +extern unsigned int csum_partial_copy_nocheck(const unsigned char *src, + unsigned char *dst, int len, unsigned int sum); - -static inline unsigned int -csum_partial_copy_nocheck (const unsigned char *src, unsigned char *dst, int len, - unsigned int sum) -{ - int ret; - unsigned char cur_ds = get_thread_current_ds(); - __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "i" (ASI_P)); - ret = csum_partial_copy_sparc64(src, dst, len, sum); - __asm__ __volatile__ ("wr %%g0, %0, %%asi" : : "r" (cur_ds)); - return ret; -} -static inline unsigned int -csum_partial_copy_from_user(const unsigned char __user *src, unsigned char *dst, int len, +extern long __csum_partial_copy_from_user(const unsigned char __user *src, + unsigned char *dst, int len, + unsigned int sum); + +static inline unsigned int +csum_partial_copy_from_user(const unsigned char __user *src, + unsigned char *dst, int len, unsigned int sum, int *err) { - __asm__ __volatile__ ("stx %0, [%%sp + 0x7ff + 128]" - : : "r" (err)); - return csum_partial_copy_sparc64((__force const char *) src, - dst, len, sum); + long ret = __csum_partial_copy_from_user(src, dst, len, sum); + if (ret < 0) + *err = -EFAULT; + return (unsigned int) ret; } /* * Copy and checksum to user */ #define HAVE_CSUM_COPY_USER -extern unsigned int csum_partial_copy_user_sparc64(const unsigned char *src, unsigned char __user *dst, - int len, unsigned int sum); +extern long __csum_partial_copy_to_user(const unsigned char *src, + unsigned char __user *dst, int len, + unsigned int sum); -static inline unsigned int -csum_and_copy_to_user(const unsigned char *src, unsigned char __user *dst, int len, +static inline unsigned int +csum_and_copy_to_user(const unsigned char *src, + unsigned char __user *dst, int len, unsigned int sum, int *err) { - __asm__ __volatile__ ("stx %0, [%%sp + 0x7ff + 128]" - : : "r" (err)); - return csum_partial_copy_user_sparc64(src, dst, len, sum); + long ret = __csum_partial_copy_to_user(src, dst, len, sum); + if (ret < 0) + *err = -EFAULT; + return (unsigned int) ret; } - + /* ihl is always 5 or greater, almost always is 5, and iph is word aligned * the majority of the time. */ diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h index d7625ffc0b85a..cc7198aaac505 100644 --- a/include/asm-sparc64/cpudata.h +++ b/include/asm-sparc64/cpudata.h @@ -19,12 +19,13 @@ typedef struct { /* Dcache line 2 */ unsigned int pgcache_size; - unsigned int pgdcache_size; + unsigned int __pad1; unsigned long *pte_cache[2]; unsigned long *pgd_cache; } cpuinfo_sparc; DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data); -#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu)) +#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu)) +#define local_cpu_data() __get_cpu_var(__cpu_data) #endif /* _SPARC64_CPUDATA_H */ diff --git a/include/asm-sparc64/ide.h b/include/asm-sparc64/ide.h index 6b327402277fd..4c1098474c73f 100644 --- a/include/asm-sparc64/ide.h +++ b/include/asm-sparc64/ide.h @@ -13,8 +13,8 @@ #include <linux/config.h> #include <asm/pgalloc.h> #include <asm/io.h> -#include <asm/page.h> #include <asm/spitfire.h> +#include <asm/cacheflush.h> #ifndef MAX_HWIFS # ifdef CONFIG_BLK_DEV_IDEPCI @@ -51,7 +51,7 @@ static inline unsigned int inw_be(void __iomem *addr) static inline void __ide_insw(void __iomem *port, void *dst, u32 count) { -#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */ +#ifdef DCACHE_ALIASING_POSSIBLE unsigned long end = (unsigned long)dst + (count << 1); #endif u16 *ps = dst; @@ -74,7 +74,7 @@ static inline void __ide_insw(void __iomem *port, void *dst, u32 count) if(count) *ps++ = inw_be(port); -#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */ +#ifdef DCACHE_ALIASING_POSSIBLE __flush_dcache_range((unsigned long)dst, end); #endif } @@ -88,7 +88,7 @@ static inline void outw_be(unsigned short w, void __iomem *addr) static inline void __ide_outsw(void __iomem *port, void *src, u32 count) { -#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */ +#ifdef DCACHE_ALIASING_POSSIBLE unsigned long end = (unsigned long)src + (count << 1); #endif const u16 *ps = src; @@ -111,7 +111,7 @@ static inline void __ide_outsw(void __iomem *port, void *src, u32 count) if(count) outw_be(*ps, port); -#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */ +#ifdef DCACHE_ALIASING_POSSIBLE __flush_dcache_range((unsigned long)src, end); #endif } diff --git a/include/asm-sparc64/mmu.h b/include/asm-sparc64/mmu.h index ccd36d26615a7..8627eed6e83df 100644 --- a/include/asm-sparc64/mmu.h +++ b/include/asm-sparc64/mmu.h @@ -1,7 +1,99 @@ #ifndef __MMU_H #define __MMU_H -/* Default "unsigned long" context */ -typedef unsigned long mm_context_t; +#include <linux/config.h> +#include <asm/page.h> +#include <asm/const.h> +/* + * For the 8k pagesize kernel, use only 10 hw context bits to optimize some + * shifts in the fast tlbmiss handlers, instead of all 13 bits (specifically + * for vpte offset calculation). For other pagesizes, this optimization in + * the tlbhandlers can not be done; but still, all 13 bits can not be used + * because the tlb handlers use "andcc" instruction which sign extends 13 + * bit arguments. + */ +#if PAGE_SHIFT == 13 +#define CTX_NR_BITS 10 +#else +#define CTX_NR_BITS 12 #endif + +#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL)) + +/* UltraSPARC-III+ and later have a feature whereby you can + * select what page size the various Data-TLB instances in the + * chip. In order to gracefully support this, we put the version + * field in a spot outside of the areas of the context register + * where this parameter is specified. + */ +#define CTX_VERSION_SHIFT 22 +#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT) + +#define CTX_PGSZ_8KB _AC(0x0,UL) +#define CTX_PGSZ_64KB _AC(0x1,UL) +#define CTX_PGSZ_512KB _AC(0x2,UL) +#define CTX_PGSZ_4MB _AC(0x3,UL) +#define CTX_PGSZ_BITS _AC(0x7,UL) +#define CTX_PGSZ0_NUC_SHIFT 61 +#define CTX_PGSZ1_NUC_SHIFT 58 +#define CTX_PGSZ0_SHIFT 16 +#define CTX_PGSZ1_SHIFT 19 +#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \ + (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT)) + +#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB) +#define CTX_PGSZ_BASE CTX_PGSZ_8KB +#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB) +#define CTX_PGSZ_BASE CTX_PGSZ_64KB +#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB) +#define CTX_PGSZ_BASE CTX_PGSZ_512KB +#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB) +#define CTX_PGSZ_BASE CTX_PGSZ_4MB +#else +#error No page size specified in kernel configuration +#endif + +#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB) +#define CTX_PGSZ_HUGE CTX_PGSZ_4MB +#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K) +#define CTX_PGSZ_HUGE CTX_PGSZ_512KB +#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K) +#define CTX_PGSZ_HUGE CTX_PGSZ_64KB +#endif + +#define CTX_PGSZ_KERN CTX_PGSZ_4MB + +/* Thus, when running on UltraSPARC-III+ and later, we use the following + * PRIMARY_CONTEXT register values for the kernel context. + */ +#define CTX_CHEETAH_PLUS_NUC \ + ((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \ + (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT)) + +#define CTX_CHEETAH_PLUS_CTX0 \ + ((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \ + (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT)) + +/* If you want "the TLB context number" use CTX_NR_MASK. If you + * want "the bits I program into the context registers" use + * CTX_HW_MASK. + */ +#define CTX_NR_MASK TAG_CONTEXT_BITS +#define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK) + +#define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL)) +#define CTX_VALID(__ctx) \ + (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK)) +#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK) +#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK) + +#ifndef __ASSEMBLY__ + +typedef struct { + unsigned long sparc64_ctx_val; +} mm_context_t; + +#endif /* !__ASSEMBLY__ */ + +#endif /* __MMU_H */ diff --git a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h index 08275bc3478ac..87c43c67866e9 100644 --- a/include/asm-sparc64/mmu_context.h +++ b/include/asm-sparc64/mmu_context.h @@ -4,23 +4,6 @@ /* Derived heavily from Linus's Alpha/AXP ASN code... */ -#include <asm/page.h> - -/* - * For the 8k pagesize kernel, use only 10 hw context bits to optimize some shifts in - * the fast tlbmiss handlers, instead of all 13 bits (specifically for vpte offset - * calculation). For other pagesizes, this optimization in the tlbhandlers can not be - * done; but still, all 13 bits can not be used because the tlb handlers use "andcc" - * instruction which sign extends 13 bit arguments. - */ -#if PAGE_SHIFT == 13 -#define CTX_VERSION_SHIFT 10 -#define TAG_CONTEXT_BITS 0x3ff -#else -#define CTX_VERSION_SHIFT 12 -#define TAG_CONTEXT_BITS 0xfff -#endif - #ifndef __ASSEMBLY__ #include <linux/spinlock.h> @@ -35,19 +18,14 @@ extern spinlock_t ctx_alloc_lock; extern unsigned long tlb_context_cache; extern unsigned long mmu_context_bmap[]; -#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT) -#define CTX_FIRST_VERSION ((1UL << CTX_VERSION_SHIFT) + 1UL) -#define CTX_VALID(__ctx) \ - (!(((__ctx) ^ tlb_context_cache) & CTX_VERSION_MASK)) -#define CTX_HWBITS(__ctx) ((__ctx) & ~CTX_VERSION_MASK) - extern void get_new_mmu_context(struct mm_struct *mm); /* Initialize a new mmu context. This is invoked when a new * address space instance (unique or shared) is instantiated. * This just needs to set mm->context to an invalid context. */ -#define init_new_context(__tsk, __mm) (((__mm)->context = 0UL), 0) +#define init_new_context(__tsk, __mm) \ + (((__mm)->context.sparc64_ctx_val = 0UL), 0) /* Destroy a dead context. This occurs when mmput drops the * mm_users count to zero, the mmaps have been released, and @@ -59,7 +37,7 @@ extern void get_new_mmu_context(struct mm_struct *mm); #define destroy_context(__mm) \ do { spin_lock(&ctx_alloc_lock); \ if (CTX_VALID((__mm)->context)) { \ - unsigned long nr = CTX_HWBITS((__mm)->context); \ + unsigned long nr = CTX_NRBITS((__mm)->context); \ mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); \ } \ spin_unlock(&ctx_alloc_lock); \ @@ -101,7 +79,7 @@ do { \ "flush %%g6" \ : /* No outputs */ \ : "r" (CTX_HWBITS((__mm)->context)), \ - "r" (0x10), "i" (ASI_DMMU)) + "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU)) extern void __flush_tlb_mm(unsigned long, unsigned long); @@ -135,7 +113,8 @@ static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, str */ if (!ctx_valid || !cpu_isset(cpu, mm->cpu_vm_mask)) { cpu_set(cpu, mm->cpu_vm_mask); - __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT); + __flush_tlb_mm(CTX_HWBITS(mm->context), + SECONDARY_CONTEXT); } } spin_unlock(&mm->page_table_lock); diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h index c3dc444563e07..219ea043a14a8 100644 --- a/include/asm-sparc64/page.h +++ b/include/asm-sparc64/page.h @@ -6,7 +6,18 @@ #include <linux/config.h> #include <asm/const.h> +#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB) #define PAGE_SHIFT 13 +#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB) +#define PAGE_SHIFT 16 +#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB) +#define PAGE_SHIFT 19 +#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB) +#define PAGE_SHIFT 22 +#else +#error No page size specified in kernel configuration +#endif + #define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT) #define PAGE_MASK (~(PAGE_SIZE-1)) diff --git a/include/asm-sparc64/percpu.h b/include/asm-sparc64/percpu.h index 8571d6d1a9dfe..aea4e51e7cd13 100644 --- a/include/asm-sparc64/percpu.h +++ b/include/asm-sparc64/percpu.h @@ -1,6 +1,49 @@ #ifndef __ARCH_SPARC64_PERCPU__ #define __ARCH_SPARC64_PERCPU__ -#include <asm-generic/percpu.h> +#include <linux/compiler.h> + +#ifdef CONFIG_SMP + +extern void setup_per_cpu_areas(void); + +extern unsigned long __per_cpu_base; +extern unsigned long __per_cpu_shift; +#define __per_cpu_offset(__cpu) \ + (__per_cpu_base + ((unsigned long)(__cpu) << __per_cpu_shift)) + +/* Separate out the type, so (int[3], foo) works. */ +#define DEFINE_PER_CPU(type, name) \ + __attribute__((__section__(".data.percpu"))) __typeof__(type) per_cpu__##name + +register unsigned long __local_per_cpu_offset asm("g5"); + +/* var is in discarded region: offset to particular copy we want */ +#define per_cpu(var, cpu) (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset(cpu))) +#define __get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __local_per_cpu_offset)) + +/* A macro to avoid #include hell... */ +#define percpu_modcopy(pcpudst, src, size) \ +do { \ + unsigned int __i; \ + for (__i = 0; __i < NR_CPUS; __i++) \ + if (cpu_possible(__i)) \ + memcpy((pcpudst)+__per_cpu_offset(__i), \ + (src), (size)); \ +} while (0) +#else /* ! SMP */ + +#define DEFINE_PER_CPU(type, name) \ + __typeof__(type) per_cpu__##name + +#define per_cpu(var, cpu) (*((void)cpu, &per_cpu__##var)) +#define __get_cpu_var(var) per_cpu__##var + +#endif /* SMP */ + +#define DECLARE_PER_CPU(type, name) extern __typeof__(type) per_cpu__##name + +#define EXPORT_PER_CPU_SYMBOL(var) EXPORT_SYMBOL(per_cpu__##var) +#define EXPORT_PER_CPU_SYMBOL_GPL(var) EXPORT_SYMBOL_GPL(per_cpu__##var) #endif /* __ARCH_SPARC64_PERCPU__ */ diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h index 167d514bdf6ee..2c28e1f605b76 100644 --- a/include/asm-sparc64/pgalloc.h +++ b/include/asm-sparc64/pgalloc.h @@ -9,84 +9,23 @@ #include <asm/spitfire.h> #include <asm/cpudata.h> +#include <asm/cacheflush.h> /* Page table allocation/freeing. */ #ifdef CONFIG_SMP /* Sliiiicck */ -#define pgt_quicklists cpu_data(smp_processor_id()) +#define pgt_quicklists local_cpu_data() #else extern struct pgtable_cache_struct { unsigned long *pgd_cache; unsigned long *pte_cache[2]; unsigned int pgcache_size; - unsigned int pgdcache_size; } pgt_quicklists; #endif #define pgd_quicklist (pgt_quicklists.pgd_cache) #define pmd_quicklist ((unsigned long *)0) #define pte_quicklist (pgt_quicklists.pte_cache) #define pgtable_cache_size (pgt_quicklists.pgcache_size) -#define pgd_cache_size (pgt_quicklists.pgdcache_size) - -#ifndef CONFIG_SMP - -static __inline__ void free_pgd_fast(pgd_t *pgd) -{ - struct page *page = virt_to_page(pgd); - - preempt_disable(); - if (!page->lru.prev) { - page->lru.next = (void *) pgd_quicklist; - pgd_quicklist = (unsigned long *)page; - } - page->lru.prev = (void *) - (((unsigned long)page->lru.prev) | - (((unsigned long)pgd & (PAGE_SIZE / 2)) ? 2 : 1)); - pgd_cache_size++; - preempt_enable(); -} - -static __inline__ pgd_t *get_pgd_fast(void) -{ - struct page *ret; - - preempt_disable(); - if ((ret = (struct page *)pgd_quicklist) != NULL) { - unsigned long mask = (unsigned long)ret->lru.prev; - unsigned long off = 0; - - if (mask & 1) - mask &= ~1; - else { - off = PAGE_SIZE / 2; - mask &= ~2; - } - ret->lru.prev = (void *) mask; - if (!mask) - pgd_quicklist = (unsigned long *)ret->lru.next; - ret = (struct page *)(__page_address(ret) + off); - pgd_cache_size--; - preempt_enable(); - } else { - struct page *page; - - preempt_enable(); - page = alloc_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); - if (page) { - ret = (struct page *)page_address(page); - page->lru.prev = (void *) 2UL; - - preempt_disable(); - page->lru.next = (void *) pgd_quicklist; - pgd_quicklist = (unsigned long *)page; - pgd_cache_size++; - preempt_enable(); - } - } - return (pgd_t *)ret; -} - -#else /* CONFIG_SMP */ static __inline__ void free_pgd_fast(pgd_t *pgd) { @@ -121,9 +60,7 @@ static __inline__ void free_pgd_slow(pgd_t *pgd) free_page((unsigned long)pgd); } -#endif /* CONFIG_SMP */ - -#if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */ +#ifdef DCACHE_ALIASING_POSSIBLE #define VPTE_COLOR(address) (((address) >> (PAGE_SHIFT + 10)) & 1UL) #define DCACHE_COLOR(address) (((address) >> PAGE_SHIFT) & 1UL) #else diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h index dfb8a88863186..ca04ac105b694 100644 --- a/include/asm-sparc64/pgtable.h +++ b/include/asm-sparc64/pgtable.h @@ -60,44 +60,24 @@ #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) #define PMD_SIZE (1UL << PMD_SHIFT) #define PMD_MASK (~(PMD_SIZE-1)) -#define PMD_BITS 11 +#define PMD_BITS (PAGE_SHIFT - 2) /* PGDIR_SHIFT determines what a third-level page table entry can map */ #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) +#define PGDIR_BITS (PAGE_SHIFT - 2) #ifndef __ASSEMBLY__ #include <linux/sched.h> /* Entries per page directory level. */ -#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) - -/* We the first one in this file, what we export to the kernel - * is different so we can optimize correctly for 32-bit tasks. - */ -#define REAL_PTRS_PER_PMD (1UL << PMD_BITS) - -/* This is gross, but unless we do this gcc retests the - * thread flag every interation in pmd traversal loops. - */ -extern unsigned long __ptrs_per_pmd(void) __attribute_const__; -#define PTRS_PER_PMD __ptrs_per_pmd() - -/* - * We cannot use the top address range because VPTE table lives there. This - * formula finds the total legal virtual space in the processor, subtracts the - * vpte size, then aligns it to the number of bytes mapped by one pgde, and - * thus calculates the number of pgdes needed. - */ -#define PTRS_PER_PGD (((1UL << VA_BITS) - VPTE_SIZE + (1UL << (PAGE_SHIFT + \ - (PAGE_SHIFT-3) + PMD_BITS)) - 1) / (1UL << (PAGE_SHIFT + \ - (PAGE_SHIFT-3) + PMD_BITS))) +#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) +#define PTRS_PER_PMD (1UL << PMD_BITS) +#define PTRS_PER_PGD (1UL << PGDIR_BITS) /* Kernel has a separate 44bit address space. */ -#define USER_PTRS_PER_PGD ((const int)(test_thread_flag(TIF_32BIT)) ? \ - (1) : (PTRS_PER_PGD)) #define FIRST_USER_PGD_NR 0 #define pte_ERROR(e) __builtin_trap() @@ -236,8 +216,8 @@ extern struct page *mem_map_zero; /* PFNs are real physical page numbers. However, mem_map only begins to record * per-page information starting at pfn_base. This is to handle systems where - * the first physical page in the machine is at some huge physical address, such - * as 4GB. This is common on a partitioned E10000, for example. + * the first physical page in the machine is at some huge physical address, + * such as 4GB. This is common on a partitioned E10000, for example. */ #define pfn_pte(pfn, prot) \ @@ -308,7 +288,7 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W)) /* to find an entry in a page-table-directory. */ -#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD)) +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) /* to find an entry in a kernel page-table-directory */ @@ -322,7 +302,7 @@ static inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot) /* Find an entry in the second-level page table.. */ #define pmd_offset(pudp, address) \ ((pmd_t *) pud_page(*(pudp)) + \ - (((address) >> PMD_SHIFT) & (REAL_PTRS_PER_PMD-1))) + (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) /* Find an entry in the third-level page table.. */ #define pte_index(dir, address) \ diff --git a/include/asm-sparc64/rwsem-const.h b/include/asm-sparc64/rwsem-const.h new file mode 100644 index 0000000000000..a303c9d64d845 --- /dev/null +++ b/include/asm-sparc64/rwsem-const.h @@ -0,0 +1,12 @@ +/* rwsem-const.h: RW semaphore counter constants. */ +#ifndef _SPARC64_RWSEM_CONST_H +#define _SPARC64_RWSEM_CONST_H + +#define RWSEM_UNLOCKED_VALUE 0x00000000 +#define RWSEM_ACTIVE_BIAS 0x00000001 +#define RWSEM_ACTIVE_MASK 0x0000ffff +#define RWSEM_WAITING_BIAS 0xffff0000 +#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS +#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) + +#endif /* _SPARC64_RWSEM_CONST_H */ diff --git a/include/asm-sparc64/rwsem.h b/include/asm-sparc64/rwsem.h index 82fffac5b0b81..bf2ae90ed3df8 100644 --- a/include/asm-sparc64/rwsem.h +++ b/include/asm-sparc64/rwsem.h @@ -15,17 +15,12 @@ #include <linux/list.h> #include <linux/spinlock.h> +#include <asm/rwsem-const.h> struct rwsem_waiter; struct rw_semaphore { signed int count; -#define RWSEM_UNLOCKED_VALUE 0x00000000 -#define RWSEM_ACTIVE_BIAS 0x00000001 -#define RWSEM_ACTIVE_MASK 0x0000ffff -#define RWSEM_WAITING_BIAS 0xffff0000 -#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS -#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) spinlock_t wait_lock; struct list_head wait_list; }; @@ -56,16 +51,16 @@ static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem) int tmp = delta; __asm__ __volatile__( - "1:\tlduw [%2], %%g5\n\t" - "add %%g5, %1, %%g7\n\t" - "cas [%2], %%g5, %%g7\n\t" - "cmp %%g5, %%g7\n\t" + "1:\tlduw [%2], %%g1\n\t" + "add %%g1, %1, %%g7\n\t" + "cas [%2], %%g1, %%g7\n\t" + "cmp %%g1, %%g7\n\t" "bne,pn %%icc, 1b\n\t" " membar #StoreLoad | #StoreStore\n\t" "mov %%g7, %0\n\t" : "=&r" (tmp) : "0" (tmp), "r" (sem) - : "g5", "g7", "memory", "cc"); + : "g1", "g7", "memory", "cc"); return tmp + delta; } diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h index 6ee83ff2fde36..ad78ce64d69ee 100644 --- a/include/asm-sparc64/spitfire.h +++ b/include/asm-sparc64/spitfire.h @@ -34,6 +34,9 @@ #define PHYS_WATCHPOINT 0x0000000000000040 #define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1) +#define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1) + +#define L1DCACHE_SIZE 0x4000 #ifndef __ASSEMBLY__ @@ -45,10 +48,6 @@ enum ultra_tlb_layout { extern enum ultra_tlb_layout tlb_type; -#define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1) - -#define L1DCACHE_SIZE 0x4000 - #define sparc64_highest_locked_tlbent() \ (tlb_type == spitfire ? \ SPITFIRE_HIGHEST_LOCKED_TLBENT : \ @@ -100,46 +99,6 @@ static __inline__ void spitfire_put_dsfsr(unsigned long sfsr) : "r" (sfsr), "r" (TLB_SFSR), "i" (ASI_DMMU)); } -static __inline__ unsigned long spitfire_get_primary_context(void) -{ - unsigned long ctx; - - __asm__ __volatile__("ldxa [%1] %2, %0" - : "=r" (ctx) - : "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); - return ctx; -} - -static __inline__ void spitfire_set_primary_context(unsigned long ctx) -{ - __asm__ __volatile__("stxa %0, [%1] %2\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (ctx & 0x3ff), - "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); - __asm__ __volatile__ ("membar #Sync" : : : "memory"); -} - -static __inline__ unsigned long spitfire_get_secondary_context(void) -{ - unsigned long ctx; - - __asm__ __volatile__("ldxa [%1] %2, %0" - : "=r" (ctx) - : "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU)); - return ctx; -} - -static __inline__ void spitfire_set_secondary_context(unsigned long ctx) -{ - __asm__ __volatile__("stxa %0, [%1] %2\n\t" - "membar #Sync" - : /* No outputs */ - : "r" (ctx & 0x3ff), - "r" (SECONDARY_CONTEXT), "i" (ASI_DMMU)); - __asm__ __volatile__ ("membar #Sync" : : : "memory"); -} - /* The data cache is write through, so this just invalidates the * specified line. */ diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h index e8ba9d5277e15..fd12ca386f486 100644 --- a/include/asm-sparc64/system.h +++ b/include/asm-sparc64/system.h @@ -182,7 +182,7 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ __asm__ __volatile__("wr %%g0, %0, %%asi" \ : : "r" (__thread_flag_byte_ptr(next->thread_info)[TI_FLAG_BYTE_CURRENT_DS]));\ __asm__ __volatile__( \ - "mov %%g4, %%g5\n\t" \ + "mov %%g4, %%g7\n\t" \ "wrpr %%g0, 0x95, %%pstate\n\t" \ "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \ "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \ @@ -207,7 +207,7 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ "wrpr %%g0, 0x96, %%pstate\n\t" \ "andcc %%o7, %6, %%g0\n\t" \ "beq,pt %%icc, 1f\n\t" \ - " mov %%g5, %0\n\t" \ + " mov %%g7, %0\n\t" \ "b,a ret_from_syscall\n\t" \ "1:\n\t" \ : "=&r" (last) \ @@ -215,7 +215,7 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_FLAGS), "i" (TI_CWP), \ "i" (_TIF_NEWCHILD), "i" (TI_TASK) \ : "cc", \ - "g1", "g2", "g3", "g5", "g7", \ + "g1", "g2", "g3", "g7", \ "l2", "l3", "l4", "l5", "l6", "l7", \ "i0", "i1", "i2", "i3", "i4", "i5", \ "o0", "o1", "o2", "o3", "o4", "o5", "o7" EXTRA_CLOBBER);\ @@ -226,37 +226,41 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \ } \ } while(0) -static __inline__ unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) +static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) { + unsigned long tmp1, tmp2; + __asm__ __volatile__( " membar #StoreLoad | #LoadLoad\n" -" mov %0, %%g5\n" -"1: lduw [%2], %%g7\n" -" cas [%2], %%g7, %0\n" -" cmp %%g7, %0\n" +" mov %0, %1\n" +"1: lduw [%4], %2\n" +" cas [%4], %2, %0\n" +" cmp %2, %0\n" " bne,a,pn %%icc, 1b\n" -" mov %%g5, %0\n" +" mov %1, %0\n" " membar #StoreLoad | #StoreStore\n" - : "=&r" (val) + : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2) : "0" (val), "r" (m) - : "g5", "g7", "cc", "memory"); + : "cc", "memory"); return val; } -static __inline__ unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val) +static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val) { + unsigned long tmp1, tmp2; + __asm__ __volatile__( " membar #StoreLoad | #LoadLoad\n" -" mov %0, %%g5\n" -"1: ldx [%2], %%g7\n" -" casx [%2], %%g7, %0\n" -" cmp %%g7, %0\n" +" mov %0, %1\n" +"1: ldx [%4], %2\n" +" casx [%4], %2, %0\n" +" cmp %2, %0\n" " bne,a,pn %%xcc, 1b\n" -" mov %%g5, %0\n" +" mov %1, %0\n" " membar #StoreLoad | #StoreStore\n" - : "=&r" (val) + : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2) : "0" (val), "r" (m) - : "g5", "g7", "cc", "memory"); + : "cc", "memory"); return val; } diff --git a/include/asm-sparc64/tlb.h b/include/asm-sparc64/tlb.h index fa0ebf6786fc9..9baf57db01d20 100644 --- a/include/asm-sparc64/tlb.h +++ b/include/asm-sparc64/tlb.h @@ -44,7 +44,7 @@ extern void flush_tlb_pending(void); static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush) { - struct mmu_gather *mp = &per_cpu(mmu_gathers, smp_processor_id()); + struct mmu_gather *mp = &__get_cpu_var(mmu_gathers); BUG_ON(mp->tlb_nr); @@ -89,9 +89,7 @@ static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, un tlb_flush_mmu(mp); if (mp->tlb_frozen) { - unsigned long context = mm->context; - - if (CTX_VALID(context)) + if (CTX_VALID(mm->context)) do_flush_tlb_mm(mm); mp->tlb_frozen = 0; } else diff --git a/include/asm-x86_64/topology.h b/include/asm-x86_64/topology.h index c5fea186bdf28..67f24e0ea819f 100644 --- a/include/asm-x86_64/topology.h +++ b/include/asm-x86_64/topology.h @@ -35,8 +35,7 @@ static inline cpumask_t __pcibus_to_cpumask(int bus) cpus_and(res, busmask, online); return res; } -/* broken generic file uses #ifndef later on this */ -#define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus) +#define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus->number) #ifdef CONFIG_NUMA /* sched_domains SD_NODE_INIT for x86_64 machines */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 87da80182983d..bea13a99e6fb4 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -561,7 +561,7 @@ struct pci_dev { int rom_attr_enabled; /* has display of the rom attribute been enabled? */ struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ #ifdef CONFIG_PCI_NAMES -#define PCI_NAME_SIZE 96 +#define PCI_NAME_SIZE 255 #define PCI_NAME_HALF __stringify(43) /* less than half to handle slop */ char pretty_name[PCI_NAME_SIZE]; /* pretty name for users to see */ #endif diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index a27d42d3e6522..de33f6724867e 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2122,6 +2122,8 @@ #define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44 #define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278 #define PCI_DEVICE_ID_MELLANOX_ARBEL 0x6282 +#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c +#define PCI_DEVICE_ID_MELLANOX_SINAI 0x6274 #define PCI_VENDOR_ID_PDC 0x15e9 #define PCI_DEVICE_ID_PDC_1841 0x1841 @@ -2390,7 +2392,7 @@ #define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e #define PCI_DEVICE_ID_INTEL_ICH6_19 0x266f #define PCI_DEVICE_ID_INTEL_ICH7_0 0x27b8 -#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b1 +#define PCI_DEVICE_ID_INTEL_ICH7_1 0x27b9 #define PCI_DEVICE_ID_INTEL_ICH7_2 0x27c0 #define PCI_DEVICE_ID_INTEL_ICH7_3 0x27c1 #define PCI_DEVICE_ID_INTEL_ICH7_5 0x27c4 |