From 24ee9b048e7c5d0446840f4f3ed03882a6d2cd78 Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Mon, 1 Feb 2010 18:58:13 +0800 Subject: [PATCH] MIPS: cavium-octeon: rewrite the sched_clock() based on mips_sched_clock() commit 4bf235ddf271eeb96f0fd08f2dbeef26495ebd10 in tip. The commit "MIPS: add a common mips_sched_clock()" have abstracted the solution of the 64bit calculation's overflow problem into a common mips_sched_clock() function in arch/mips/include/asm/time.h, This patch just rewrites the sched_clock() for cavium-octeon on it. Signed-off-by: Wu Zhangjin Signed-off-by: Paul Gortmaker --- arch/mips/cavium-octeon/csrc-octeon.c | 27 +-------------------------- 1 files changed, 1 insertions(+), 26 deletions(-) diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c index 0bf4bbe..53b1c32 100644 --- a/arch/mips/cavium-octeon/csrc-octeon.c +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -52,34 +52,9 @@ static struct clocksource clocksource_mips = { unsigned long long notrace sched_clock(void) { - /* 64-bit arithmatic can overflow, so use 128-bit. */ -#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3)) - u64 t1, t2, t3; - unsigned long long rv; - u64 mult = clocksource_mips.mult; - u64 shift = clocksource_mips.shift; u64 cnt = read_c0_cvmcount(); - asm ( - "dmultu\t%[cnt],%[mult]\n\t" - "nor\t%[t1],$0,%[shift]\n\t" - "mfhi\t%[t2]\n\t" - "mflo\t%[t3]\n\t" - "dsll\t%[t2],%[t2],1\n\t" - "dsrlv\t%[rv],%[t3],%[shift]\n\t" - "dsllv\t%[t1],%[t2],%[t1]\n\t" - "or\t%[rv],%[t1],%[rv]\n\t" - : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) - : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift) - : "hi", "lo"); - return rv; -#else - /* GCC > 4.3 do it the easy way. */ - unsigned int __attribute__((mode(TI))) t; - t = read_c0_cvmcount(); - t = t * clocksource_mips.mult; - return (unsigned long long)(t >> clocksource_mips.shift); -#endif + return mips_sched_clock(&clocksource_mips, cnt); } void __init plat_time_init(void) -- 1.7.0.4