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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2017-02-16 11:26:56 +0530 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2017-02-16 18:07:15 +0530 |
| commit | c389b99bdd67a5201f5c88f4e47d08bb872f1ff5 (patch) | |
| tree | 397196ba1d941d39e3e84f9376f69f58b99faaf4 | |
| parent | 70a4856de38b3220cbfeec4a190c018350d07397 (diff) | |
| download | pci-ep-c389b99bdd67a5201f5c88f4e47d08bb872f1ff5.tar.gz | |
PCI: dwc: designware: Add new *ops* for cpu addr fixup
Some platforms (like dra7xx) require only the least 28 bits of the
corresponding 32 bit CPU address to be programmed in the address
translation unit. This modified address is stored in io_base/mem_base/
cfg0_base/cfg1_base in dra7xx_pcie_host_init. While this is okay for
host mode where the address range is fixed, device mode requires
different addresses to be programmed based on the host buffer address.
Add a new ops to get the least 28 bits of the corresponding 32 bit
CPU address and invoke it before programming the address translation
unit.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| -rw-r--r-- | drivers/pci/dwc/pcie-designware.c | 3 | ||||
| -rw-r--r-- | drivers/pci/dwc/pcie-designware.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c index 7e1fb7d6643cfe..14ee7a33a91d0e 100644 --- a/drivers/pci/dwc/pcie-designware.c +++ b/drivers/pci/dwc/pcie-designware.c @@ -97,6 +97,9 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type, { u32 retries, val; + if (pp->ops->cpu_addr_fixup) + cpu_addr = pp->ops->cpu_addr_fixup(cpu_addr); + if (pci->iatu_unroll_enabled) { dw_pcie_writel_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE, lower_32_bits(cpu_addr)); diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h index cd3b8713fe5044..8f3dcb2b099b03 100644 --- a/drivers/pci/dwc/pcie-designware.h +++ b/drivers/pci/dwc/pcie-designware.h @@ -143,6 +143,7 @@ struct pcie_port { }; struct dw_pcie_ops { + u64 (*cpu_addr_fixup)(u64 cpu_addr); u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg); void (*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val); int (*link_up)(struct dw_pcie *pcie); |