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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-01 22:00:39 -0700 |
|---|---|---|
| committer | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2022-06-05 22:07:23 +0200 |
| commit | b296539554213125eb8f61291c862eec190e4c9b (patch) | |
| tree | e61ded885dc846c6dc20a8331a20cc127f326024 | |
| parent | dcb3887d85c10c96cc56d2715bf21566e3c31d9b (diff) | |
| download | sparse-b296539554213125eb8f61291c862eec190e4c9b.tar.gz | |
RISC-V: Remove "g" from the extension list
"g" goes along with the base ISA, but it was being treated as an
extension. This allows for all sorts of odd ISA strings to be accepted
by sparse, things like "rv32ig" or "rv32gg". We're still allowing
some oddities, like "rv32ga", but this one was easy to catch.
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
| -rw-r--r-- | target-riscv.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/target-riscv.c b/target-riscv.c index d6dbb7d5..217ab7e8 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -38,7 +38,6 @@ static void parse_march_riscv(const char *arg) { "a", RISCV_ATOMIC }, { "f", RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR }, { "d", RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR }, - { "g", RISCV_GENERIC }, { "c", RISCV_COMP }, { "_zicsr", RISCV_ZICSR }, { "_zifencei", RISCV_ZIFENCEI }, |