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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-01 22:00:41 -0700 |
|---|---|---|
| committer | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2022-05-21 21:10:05 +0200 |
| commit | 76d40fa9e54fdf790f9d1a4b97be93f94d26abfc (patch) | |
| tree | a0b1b6234f3b1d3b768af498ce39604db21a669f | |
| parent | 54cb689f2b664d379ac070b23fa3d8c814421d3a (diff) | |
| download | sparse-76d40fa9e54fdf790f9d1a4b97be93f94d26abfc.tar.gz | |
RISC-V: Add the Zifencei extension
Recent versions of binutils default to an ISA spec version that doesn't
include Zifencei as part of I, so Linux has recently started passing
this in -march.
[ Luc Van Oostenryck: move this patch at the start of the series ]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
| -rw-r--r-- | target-riscv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-riscv.c b/target-riscv.c index dd25bfb9..3bba7c15 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -17,6 +17,7 @@ #define RISCV_FPU (RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV) #define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU) #define RISCV_ZICSR (1 << 10) +#define RISCV_ZIFENCEI (1 << 11) static unsigned int riscv_flags; @@ -49,6 +50,7 @@ static void parse_march_riscv(const char *arg) { "h", 0 }, { "s", 0 }, { "_zicsr", RISCV_ZICSR }, + { "_zifencei", RISCV_ZIFENCEI }, }; int i; @@ -131,6 +133,8 @@ static void predefine_riscv(const struct target *self) predefine("__riscv_muldiv", 1, "1"); if (riscv_flags & RISCV_ZICSR) predefine("__riscv_zicsr", 1, "1"); + if (riscv_flags & RISCV_ZIFENCEI) + predefine("__riscv_zifencei", 1, "1"); if (cmodel) predefine_strong("__riscv_cmodel_%s", cmodel); |