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author | Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-01 22:00:40 -0700 |
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committer | Luc Van Oostenryck <luc.vanoostenryck@gmail.com> | 2022-05-21 21:09:30 +0200 |
commit | 54cb689f2b664d379ac070b23fa3d8c814421d3a (patch) | |
tree | 6d8c3359af961f3fa530a9848ce26d4eeab2a16b | |
parent | c4706aa764f3ae68258ba60be6325a5662900362 (diff) | |
download | sparse-54cb689f2b664d379ac070b23fa3d8c814421d3a.tar.gz |
RISC-V: Add the Zicsr extension
Recent versions of binutils default to an ISA spec version that doesn't
include Zicsr as part of I, so Linux has recently started passing this
in -march.
[ Luc Van Oostenryck: move this patch at the start of the series ]
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
-rw-r--r-- | target-riscv.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/target-riscv.c b/target-riscv.c index 6d9113c1..dd25bfb9 100644 --- a/target-riscv.c +++ b/target-riscv.c @@ -16,6 +16,7 @@ #define RISCV_EMBD (1 << 9) #define RISCV_FPU (RISCV_FLOAT|RISCV_DOUBLE|RISCV_FDIV) #define RISCV_GENERIC (RISCV_MUL|RISCV_DIV|RISCV_ATOMIC|RISCV_FPU) +#define RISCV_ZICSR (1 << 10) static unsigned int riscv_flags; @@ -33,8 +34,8 @@ static void parse_march_riscv(const char *arg) }, extensions[] = { { "m", RISCV_MUL|RISCV_DIV }, { "a", RISCV_ATOMIC }, - { "f", RISCV_FLOAT|RISCV_FDIV }, - { "d", RISCV_DOUBLE|RISCV_FDIV }, + { "f", RISCV_FLOAT|RISCV_FDIV|RISCV_ZICSR }, + { "d", RISCV_DOUBLE|RISCV_FDIV|RISCV_ZICSR }, { "g", RISCV_GENERIC }, { "q", 0 }, { "l", 0 }, @@ -47,6 +48,7 @@ static void parse_march_riscv(const char *arg) { "n", 0 }, { "h", 0 }, { "s", 0 }, + { "_zicsr", RISCV_ZICSR }, }; int i; @@ -127,6 +129,8 @@ static void predefine_riscv(const struct target *self) predefine("__riscv_mul", 1, "1"); if ((riscv_flags & RISCV_MUL) && (riscv_flags & RISCV_DIV)) predefine("__riscv_muldiv", 1, "1"); + if (riscv_flags & RISCV_ZICSR) + predefine("__riscv_zicsr", 1, "1"); if (cmodel) predefine_strong("__riscv_cmodel_%s", cmodel); |