From 51a956f198e4aa2c7cf0ff01432b12a12d0eb88d Mon Sep 17 00:00:00 2001 From: Thomas Hellstrom Date: Wed, 18 Mar 2009 20:47:43 -0700 Subject: Staging: add Intel Poulsbo/Morrestown DRM driver This patch adds Intel Poulsbo/Moorestown DRM support. [added to the build and fix minor issue changes by gregkh] Signed-off-by: Thomas Hellstrom Signed-off-by: Richard Purdie Signed-off-by: Greg Kroah-Hartman --- drivers/staging/Kconfig | 2 drivers/staging/Makefile | 2 drivers/staging/psb/Kconfig | 9 drivers/staging/psb/Makefile | 36 drivers/staging/psb/intel_display.c | 2435 +++++++++++++++++++++++++ drivers/staging/psb/intel_display.h | 31 drivers/staging/psb/intel_drv.h | 192 + drivers/staging/psb/intel_dsi.c | 1644 ++++++++++++++++ drivers/staging/psb/intel_i2c.c | 179 + drivers/staging/psb/intel_lvds.c | 1023 ++++++++++ drivers/staging/psb/intel_modes.c | 64 drivers/staging/psb/intel_reg.h | 972 +++++++++ drivers/staging/psb/intel_sdvo.c | 1232 ++++++++++++ drivers/staging/psb/intel_sdvo_regs.h | 328 +++ drivers/staging/psb/lnc_topaz.c | 695 +++++++ drivers/staging/psb/lnc_topaz.h | 803 ++++++++ drivers/staging/psb/lnc_topazinit.c | 1896 +++++++++++++++++++ drivers/staging/psb/psb_buffer.c | 504 +++++ drivers/staging/psb/psb_drm.h | 444 ++++ drivers/staging/psb/psb_drv.c | 1447 ++++++++++++++ drivers/staging/psb/psb_drv.h | 1129 +++++++++++ drivers/staging/psb/psb_fb.c | 1687 +++++++++++++++++ drivers/staging/psb/psb_fb.h | 47 drivers/staging/psb/psb_fence.c | 343 +++ drivers/staging/psb/psb_gtt.c | 257 ++ drivers/staging/psb/psb_irq.c | 420 ++++ drivers/staging/psb/psb_mmu.c | 1069 ++++++++++ drivers/staging/psb/psb_msvdx.c | 681 ++++++ drivers/staging/psb/psb_msvdx.h | 442 ++++ drivers/staging/psb/psb_msvdxinit.c | 668 ++++++ drivers/staging/psb/psb_reg.h | 569 +++++ drivers/staging/psb/psb_reset.c | 423 ++++ drivers/staging/psb/psb_scene.c | 523 +++++ drivers/staging/psb/psb_scene.h | 119 + drivers/staging/psb/psb_schedule.c | 1539 +++++++++++++++ drivers/staging/psb/psb_schedule.h | 176 + drivers/staging/psb/psb_setup.c | 18 drivers/staging/psb/psb_sgx.c | 1869 +++++++++++++++++++ drivers/staging/psb/psb_sgx.h | 41 drivers/staging/psb/psb_ttm_glue.c | 345 +++ drivers/staging/psb/psb_xhw.c | 629 ++++++ drivers/staging/psb/ttm/ttm_agp_backend.c | 151 + drivers/staging/psb/ttm/ttm_bo.c | 1717 +++++++++++++++++ drivers/staging/psb/ttm/ttm_bo_api.h | 578 +++++ drivers/staging/psb/ttm/ttm_bo_driver.h | 859 ++++++++ drivers/staging/psb/ttm/ttm_bo_util.c | 530 +++++ drivers/staging/psb/ttm/ttm_bo_vm.c | 597 ++++++ drivers/staging/psb/ttm/ttm_execbuf_util.c | 116 + drivers/staging/psb/ttm/ttm_execbuf_util.h | 110 + drivers/staging/psb/ttm/ttm_fence.c | 607 ++++++ drivers/staging/psb/ttm/ttm_fence_api.h | 277 ++ drivers/staging/psb/ttm/ttm_fence_driver.h | 309 +++ drivers/staging/psb/ttm/ttm_fence_user.c | 242 ++ drivers/staging/psb/ttm/ttm_fence_user.h | 147 + drivers/staging/psb/ttm/ttm_lock.c | 162 + drivers/staging/psb/ttm/ttm_lock.h | 181 + drivers/staging/psb/ttm/ttm_memory.c | 232 ++ drivers/staging/psb/ttm/ttm_memory.h | 154 + drivers/staging/psb/ttm/ttm_object.c | 444 ++++ drivers/staging/psb/ttm/ttm_object.h | 269 ++ drivers/staging/psb/ttm/ttm_pat_compat.c | 178 + drivers/staging/psb/ttm/ttm_pat_compat.h | 41 drivers/staging/psb/ttm/ttm_placement_common.h | 96 drivers/staging/psb/ttm/ttm_placement_user.c | 469 ++++ drivers/staging/psb/ttm/ttm_placement_user.h | 259 ++ drivers/staging/psb/ttm/ttm_regman.h | 74 drivers/staging/psb/ttm/ttm_tt.c | 655 ++++++ drivers/staging/psb/ttm/ttm_userobj_api.h | 79 68 files changed, 36465 insertions(+) --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -113,5 +113,7 @@ source "drivers/staging/heci/Kconfig" source "drivers/staging/line6/Kconfig" +source "drivers/staging/psb/Kconfig" + endif # !STAGING_EXCLUDE_BUILD endif # STAGING --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -39,3 +39,5 @@ obj-$(CONFIG_IDE_PHISON) += phison/ obj-$(CONFIG_PLAN9AUTH) += p9auth/ obj-$(CONFIG_HECI) += heci/ obj-$(CONFIG_LINE6_USB) += line6/ +obj-$(CONFIG_DRM_PSB) += psb/ + --- /dev/null +++ b/drivers/staging/psb/intel_display.c @@ -0,0 +1,2435 @@ +/* + * Copyright © 2006-2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + */ + +#include + +#include +#include "psb_fb.h" +#include "intel_display.h" + + +struct intel_clock_t { + /* given values */ + int n; + int m1, m2; + int p1, p2; + /* derived values */ + int dot; + int vco; + int m; + int p; +}; + +struct intel_range_t { + int min, max; +}; + +struct intel_p2_t { + int dot_limit; + int p2_slow, p2_fast; +}; + +#define INTEL_P2_NUM 2 + +struct intel_limit_t { + struct intel_range_t dot, vco, n, m, m1, m2, p, p1; + struct intel_p2_t p2; +}; + +#define I8XX_DOT_MIN 25000 +#define I8XX_DOT_MAX 350000 +#define I8XX_VCO_MIN 930000 +#define I8XX_VCO_MAX 1400000 +#define I8XX_N_MIN 3 +#define I8XX_N_MAX 16 +#define I8XX_M_MIN 96 +#define I8XX_M_MAX 140 +#define I8XX_M1_MIN 18 +#define I8XX_M1_MAX 26 +#define I8XX_M2_MIN 6 +#define I8XX_M2_MAX 16 +#define I8XX_P_MIN 4 +#define I8XX_P_MAX 128 +#define I8XX_P1_MIN 2 +#define I8XX_P1_MAX 33 +#define I8XX_P1_LVDS_MIN 1 +#define I8XX_P1_LVDS_MAX 6 +#define I8XX_P2_SLOW 4 +#define I8XX_P2_FAST 2 +#define I8XX_P2_LVDS_SLOW 14 +#define I8XX_P2_LVDS_FAST 14 /* No fast option */ +#define I8XX_P2_SLOW_LIMIT 165000 + +#define I9XX_DOT_MIN 20000 +#define I9XX_DOT_MAX 400000 +#define I9XX_VCO_MIN 1400000 +#define I9XX_VCO_MAX 2800000 +#define I9XX_N_MIN 3 +#define I9XX_N_MAX 8 +#define I9XX_M_MIN 70 +#define I9XX_M_MAX 120 +#define I9XX_M1_MIN 10 +#define I9XX_M1_MAX 20 +#define I9XX_M2_MIN 5 +#define I9XX_M2_MAX 9 +#define I9XX_P_SDVO_DAC_MIN 5 +#define I9XX_P_SDVO_DAC_MAX 80 +#define I9XX_P_LVDS_MIN 7 +#define I9XX_P_LVDS_MAX 98 +#define I9XX_P1_MIN 1 +#define I9XX_P1_MAX 8 +#define I9XX_P2_SDVO_DAC_SLOW 10 +#define I9XX_P2_SDVO_DAC_FAST 5 +#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000 +#define I9XX_P2_LVDS_SLOW 14 +#define I9XX_P2_LVDS_FAST 7 +#define I9XX_P2_LVDS_SLOW_LIMIT 112000 + +#define INTEL_LIMIT_I8XX_DVO_DAC 0 +#define INTEL_LIMIT_I8XX_LVDS 1 +#define INTEL_LIMIT_I9XX_SDVO_DAC 2 +#define INTEL_LIMIT_I9XX_LVDS 3 + +static const struct intel_limit_t intel_limits[] = { + { /* INTEL_LIMIT_I8XX_DVO_DAC */ + .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX}, + .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX}, + .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX}, + .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX}, + .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX}, + .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX}, + .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX}, + .p1 = {.min = I8XX_P1_MIN, .max = I8XX_P1_MAX}, + .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT, + .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST}, + }, + { /* INTEL_LIMIT_I8XX_LVDS */ + .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX}, + .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX}, + .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX}, + .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX}, + .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX}, + .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX}, + .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX}, + .p1 = {.min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX}, + .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT, + .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST}, + }, + { /* INTEL_LIMIT_I9XX_SDVO_DAC */ + .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, + .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX}, + .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX}, + .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX}, + .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX}, + .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX}, + .p = {.min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX}, + .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX}, + .p2 = {.dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT, + .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = + I9XX_P2_SDVO_DAC_FAST}, + }, + { /* INTEL_LIMIT_I9XX_LVDS */ + .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX}, + .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX}, + .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX}, + .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX}, + .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX}, + .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX}, + .p = {.min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX}, + .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX}, + /* The single-channel range is 25-112Mhz, and dual-channel + * is 80-224Mhz. Prefer single channel as much as possible. + */ + .p2 = {.dot_limit = I9XX_P2_LVDS_SLOW_LIMIT, + .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST}, + }, +}; + +static const struct intel_limit_t *intel_limit(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + const struct intel_limit_t *limit; + + if (IS_I9XX(dev)) { + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) + limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS]; + else + limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC]; + } else { + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) + limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS]; + else + limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC]; + } + return limit; +} + +/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ + +static void i8xx_clock(int refclk, struct intel_clock_t *clock) +{ + clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); + clock->p = clock->p1 * clock->p2; + clock->vco = refclk * clock->m / (clock->n + 2); + clock->dot = clock->vco / clock->p; +} + +/** Derive the pixel clock for the given refclk and divisors for 9xx chips. */ + +static void i9xx_clock(int refclk, struct intel_clock_t *clock) +{ + clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); + clock->p = clock->p1 * clock->p2; + clock->vco = refclk * clock->m / (clock->n + 2); + clock->dot = clock->vco / clock->p; +} + +static void intel_clock(struct drm_device *dev, int refclk, + struct intel_clock_t *clock) +{ + if (IS_I9XX(dev)) + return i9xx_clock(refclk, clock); + else + return i8xx_clock(refclk, clock); +} + +/** + * Returns whether any output on the specified pipe is of the specified type + */ +bool intel_pipe_has_type(struct drm_crtc *crtc, int type) +{ + struct drm_device *dev = crtc->dev; + struct drm_mode_config *mode_config = &dev->mode_config; + struct drm_connector *l_entry; + + list_for_each_entry(l_entry, &mode_config->connector_list, head) { + if (l_entry->encoder && l_entry->encoder->crtc == crtc) { + struct intel_output *intel_output = + to_intel_output(l_entry); + if (intel_output->type == type) + return true; + } + } + return false; +} + +#define INTELPllInvalid(s) { /* ErrorF (s) */; return false; } +/** + * Returns whether the given set of divisors are valid for a given refclk with + * the given connectors. + */ + +static bool intel_PLL_is_valid(struct drm_crtc *crtc, + struct intel_clock_t *clock) +{ + const struct intel_limit_t *limit = intel_limit(crtc); + + if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) + INTELPllInvalid("p1 out of range\n"); + if (clock->p < limit->p.min || limit->p.max < clock->p) + INTELPllInvalid("p out of range\n"); + if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) + INTELPllInvalid("m2 out of range\n"); + if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) + INTELPllInvalid("m1 out of range\n"); + if (clock->m1 <= clock->m2) + INTELPllInvalid("m1 <= m2\n"); + if (clock->m < limit->m.min || limit->m.max < clock->m) + INTELPllInvalid("m out of range\n"); + if (clock->n < limit->n.min || limit->n.max < clock->n) + INTELPllInvalid("n out of range\n"); + if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) + INTELPllInvalid("vco out of range\n"); + /* XXX: We may need to be checking "Dot clock" + * depending on the multiplier, connector, etc., + * rather than just a single range. + */ + if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) + INTELPllInvalid("dot out of range\n"); + + return true; +} + +/** + * Returns a set of divisors for the desired target clock with the given + * refclk, or FALSE. The returned values represent the clock equation: + * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. + */ +static bool intel_find_best_PLL(struct drm_crtc *crtc, int target, + int refclk, + struct intel_clock_t *best_clock) +{ + struct drm_device *dev = crtc->dev; + struct intel_clock_t clock; + const struct intel_limit_t *limit = intel_limit(crtc); + int err = target; + + if (IS_I9XX(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && + (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { + /* + * For LVDS, if the panel is on, just rely on its current + * settings for dual-channel. We haven't figured out how to + * reliably set up different single/dual channel state, if we + * even can. + */ + if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == + LVDS_CLKB_POWER_UP) + clock.p2 = limit->p2.p2_fast; + else + clock.p2 = limit->p2.p2_slow; + } else { + if (target < limit->p2.dot_limit) + clock.p2 = limit->p2.p2_slow; + else + clock.p2 = limit->p2.p2_fast; + } + + memset(best_clock, 0, sizeof(*best_clock)); + + for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; + clock.m1++) { + for (clock.m2 = limit->m2.min; + clock.m2 < clock.m1 && clock.m2 <= limit->m2.max; + clock.m2++) { + for (clock.n = limit->n.min; + clock.n <= limit->n.max; clock.n++) { + for (clock.p1 = limit->p1.min; + clock.p1 <= limit->p1.max; + clock.p1++) { + int this_err; + + intel_clock(dev, refclk, &clock); + + if (!intel_PLL_is_valid + (crtc, &clock)) + continue; + + this_err = abs(clock.dot - target); + if (this_err < err) { + *best_clock = clock; + err = this_err; + } + } + } + } + } + + return err != target; +} + +void intel_wait_for_vblank(struct drm_device *dev) +{ + /* Wait for 20ms, i.e. one cycle at 50hz. */ + udelay(20000); +} + +int intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) +{ + struct drm_device *dev = crtc->dev; + /* struct drm_i915_master_private *master_priv; */ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); + struct intel_mode_device *mode_dev = intel_crtc->mode_dev; + int pipe = intel_crtc->pipe; + unsigned long Start, Offset; + int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE); + int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF); + int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE; + int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; + u32 dspcntr; + + /* no fb bound */ + if (!crtc->fb) { + DRM_DEBUG("No FB bound\n"); + return 0; + } + + if (IS_MRST(dev) && (pipe == 0)) + dspbase = MRST_DSPABASE; + + Start = mode_dev->bo_offset(dev, psbfb->bo); + Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8); + + REG_WRITE(dspstride, crtc->fb->pitch); + + dspcntr = REG_READ(dspcntr_reg); + switch (crtc->fb->bits_per_pixel) { + case 8: + dspcntr |= DISPPLANE_8BPP; + break; + case 16: + if (crtc->fb->depth == 15) + dspcntr |= DISPPLANE_15_16BPP; + else + dspcntr |= DISPPLANE_16BPP; + break; + case 24: + case 32: + dspcntr |= DISPPLANE_32BPP_NO_ALPHA; + break; + default: + DRM_ERROR("Unknown color depth\n"); + return -EINVAL; + } + REG_WRITE(dspcntr_reg, dspcntr); + + DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y); + if (IS_I965G(dev) || IS_MRST(dev)) { + REG_WRITE(dspbase, Offset); + REG_READ(dspbase); + REG_WRITE(dspsurf, Start); + REG_READ(dspsurf); + } else { + REG_WRITE(dspbase, Start + Offset); + REG_READ(dspbase); + } + + if (!dev->primary->master) + return 0; + +#if 0 /* JB: Enable sarea later */ + master_priv = dev->primary->master->driver_priv; + if (!master_priv->sarea_priv) + return 0; + + switch (pipe) { + case 0: + master_priv->sarea_priv->planeA_x = x; + master_priv->sarea_priv->planeA_y = y; + break; + case 1: + master_priv->sarea_priv->planeB_x = x; + master_priv->sarea_priv->planeB_y = y; + break; + default: + DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); + break; + } +#endif +} + + + +/** + * Sets the power management mode of the pipe and plane. + * + * This code should probably grow support for turning the cursor off and back + * on appropriately at the same time as we're turning the pipe off/on. + */ +static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct drm_device *dev = crtc->dev; + /* struct drm_i915_master_private *master_priv; */ + /* struct drm_i915_private *dev_priv = dev->dev_private; */ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; + int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; + int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE; + int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; + u32 temp; + bool enabled; + + /* XXX: When our outputs are all unaware of DPMS modes other than off + * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. + */ + switch (mode) { + case DRM_MODE_DPMS_ON: + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + /* Enable the DPLL */ + temp = REG_READ(dpll_reg); + if ((temp & DPLL_VCO_ENABLE) == 0) { + REG_WRITE(dpll_reg, temp); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + } + + /* Enable the pipe */ + temp = REG_READ(pipeconf_reg); + if ((temp & PIPEACONF_ENABLE) == 0) + REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); + + /* Enable the plane */ + temp = REG_READ(dspcntr_reg); + if ((temp & DISPLAY_PLANE_ENABLE) == 0) { + REG_WRITE(dspcntr_reg, + temp | DISPLAY_PLANE_ENABLE); + /* Flush the plane changes */ + REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); + } + + intel_crtc_load_lut(crtc); + + /* Give the overlay scaler a chance to enable + * if it's on this pipe */ + /* intel_crtc_dpms_video(crtc, true); TODO */ + break; + case DRM_MODE_DPMS_OFF: + /* Give the overlay scaler a chance to disable + * if it's on this pipe */ + /* intel_crtc_dpms_video(crtc, FALSE); TODO */ + + /* Disable the VGA plane that we never use */ + REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); + + /* Disable display plane */ + temp = REG_READ(dspcntr_reg); + if ((temp & DISPLAY_PLANE_ENABLE) != 0) { + REG_WRITE(dspcntr_reg, + temp & ~DISPLAY_PLANE_ENABLE); + /* Flush the plane changes */ + REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); + REG_READ(dspbase_reg); + } + + if (!IS_I9XX(dev)) { + /* Wait for vblank for the disable to take effect */ + intel_wait_for_vblank(dev); + } + + /* Next, disable display pipes */ + temp = REG_READ(pipeconf_reg); + if ((temp & PIPEACONF_ENABLE) != 0) { + REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); + REG_READ(pipeconf_reg); + } + + /* Wait for vblank for the disable to take effect. */ + intel_wait_for_vblank(dev); + + temp = REG_READ(dpll_reg); + if ((temp & DPLL_VCO_ENABLE) != 0) { + REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); + REG_READ(dpll_reg); + } + + /* Wait for the clocks to turn off. */ + udelay(150); + break; + } + + enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; + +#if 0 /* JB: Add vblank support later */ + if (enabled) + dev_priv->vblank_pipe |= (1 << pipe); + else + dev_priv->vblank_pipe &= ~(1 << pipe); +#endif + + intel_crtc->dpms_mode = mode; + +#if 0 /* JB: Add sarea support later */ + if (!dev->primary->master) + return 0; + + master_priv = dev->primary->master->driver_priv; + if (!master_priv->sarea_priv) + return 0; + + switch (pipe) { + case 0: + master_priv->sarea_priv->planeA_w = + enabled ? crtc->mode.hdisplay : 0; + master_priv->sarea_priv->planeA_h = + enabled ? crtc->mode.vdisplay : 0; + break; + case 1: + master_priv->sarea_priv->planeB_w = + enabled ? crtc->mode.hdisplay : 0; + master_priv->sarea_priv->planeB_h = + enabled ? crtc->mode.vdisplay : 0; + break; + default: + DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); + break; + } +#endif +} + +static void intel_crtc_prepare(struct drm_crtc *crtc) +{ + struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; + crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); +} + +static void intel_crtc_commit(struct drm_crtc *crtc) +{ + struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; + crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); +} + +void intel_encoder_prepare(struct drm_encoder *encoder) +{ + struct drm_encoder_helper_funcs *encoder_funcs = + encoder->helper_private; + /* lvds has its own version of prepare see intel_lvds_prepare */ + encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); +} + +void intel_encoder_commit(struct drm_encoder *encoder) +{ + struct drm_encoder_helper_funcs *encoder_funcs = + encoder->helper_private; + /* lvds has its own version of commit see intel_lvds_commit */ + encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); +} + +static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + + +/** Returns the core display clock speed for i830 - i945 */ +static int intel_get_core_clock_speed(struct drm_device *dev) +{ +#if 0 /* JB: Look into this more */ + /* Core clock values taken from the published datasheets. + * The 830 may go up to 166 Mhz, which we should check. + */ + if (IS_I945G(dev)) + return 400000; + else if (IS_I915G(dev)) + return 333000; + else if (IS_I945GM(dev) || IS_845G(dev)) + return 200000; + else if (IS_I915GM(dev)) { + u16 gcfgc = 0; + + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); + + if (gcfgc & GC_LOW_FREQUENCY_ENABLE) + return 133000; + else { + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_333_MHZ: + return 333000; + default: + case GC_DISPLAY_CLOCK_190_200_MHZ: + return 190000; + } + } + } else if (IS_I865G(dev)) + return 266000; + else if (IS_I855(dev)) { +#if 0 + PCITAG bridge = pciTag(0, 0, 0); + /* This is always the host bridge */ + u16 hpllcc = pciReadWord(bridge, HPLLCC); + +#endif + u16 hpllcc = 0; + /* Assume that the hardware is in the high speed state. This + * should be the default. + */ + switch (hpllcc & GC_CLOCK_CONTROL_MASK) { + case GC_CLOCK_133_200: + case GC_CLOCK_100_200: + return 200000; + case GC_CLOCK_166_250: + return 250000; + case GC_CLOCK_100_133: + return 133000; + } + } else /* 852, 830 */ + return 133000; +#endif + return 0; /* Silence gcc warning */ +} + + +/** + * Return the pipe currently connected to the panel fitter, + * or -1 if the panel fitter is not present or not in use + */ +static int intel_panel_fitter_pipe(struct drm_device *dev) +{ + u32 pfit_control; + + /* i830 doesn't have a panel fitter */ + if (IS_I830(dev)) + return -1; + + pfit_control = REG_READ(PFIT_CONTROL); + + /* See if the panel fitter is in use */ + if ((pfit_control & PFIT_ENABLE) == 0) + return -1; + + /* 965 can place panel fitter on either pipe */ + if (IS_I965G(dev) || IS_MRST(dev)) + return (pfit_control >> 29) & 0x3; + + /* older chips can only use pipe 1 */ + return 1; +} + +static int intel_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + int x, int y, + struct drm_framebuffer *old_fb) +{ + struct drm_device *dev = crtc->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + int fp_reg = (pipe == 0) ? FPA0 : FPB0; + int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; + int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD; + int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; + int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; + int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; + int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; + int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; + int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; + int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; + int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; + int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; + int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS; + int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; + int refclk; + struct intel_clock_t clock; + u32 dpll = 0, fp = 0, dspcntr, pipeconf; + bool ok, is_sdvo = false, is_dvo = false; + bool is_crt = false, is_lvds = false, is_tv = false; + struct drm_mode_config *mode_config = &dev->mode_config; + struct drm_connector *connector; + + list_for_each_entry(connector, &mode_config->connector_list, head) { + struct intel_output *intel_output = + to_intel_output(connector); + + if (!connector->encoder + || connector->encoder->crtc != crtc) + continue; + + switch (intel_output->type) { + case INTEL_OUTPUT_LVDS: + is_lvds = true; + break; + case INTEL_OUTPUT_SDVO: + is_sdvo = true; + break; + case INTEL_OUTPUT_DVO: + is_dvo = true; + break; + case INTEL_OUTPUT_TVOUT: + is_tv = true; + break; + case INTEL_OUTPUT_ANALOG: + is_crt = true; + break; + } + } + + if (IS_I9XX(dev)) + refclk = 96000; + else + refclk = 48000; + + ok = intel_find_best_PLL(crtc, adjusted_mode->clock, refclk, + &clock); + if (!ok) { + DRM_ERROR("Couldn't find PLL settings for mode!\n"); + return 0; + } + + fp = clock.n << 16 | clock.m1 << 8 | clock.m2; + + dpll = DPLL_VGA_MODE_DIS; + if (IS_I9XX(dev)) { + if (is_lvds) { + dpll |= DPLLB_MODE_LVDS; + if (IS_POULSBO(dev)) + dpll |= DPLL_DVO_HIGH_SPEED; + } else + dpll |= DPLLB_MODE_DAC_SERIAL; + if (is_sdvo) { + dpll |= DPLL_DVO_HIGH_SPEED; + if (IS_I945G(dev) || IS_I945GM(dev)) { + int sdvo_pixel_multiply = + adjusted_mode->clock / mode->clock; + dpll |= + (sdvo_pixel_multiply - + 1) << SDVO_MULTIPLIER_SHIFT_HIRES; + } + } + + /* compute bitmask from p1 value */ + dpll |= (1 << (clock.p1 - 1)) << 16; + switch (clock.p2) { + case 5: + dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; + break; + case 7: + dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; + break; + case 10: + dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; + break; + case 14: + dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; + break; + } + if (IS_I965G(dev)) + dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); + } else { + if (is_lvds) { + dpll |= + (1 << (clock.p1 - 1)) << + DPLL_FPA01_P1_POST_DIV_SHIFT; + } else { + if (clock.p1 == 2) + dpll |= PLL_P1_DIVIDE_BY_TWO; + else + dpll |= + (clock.p1 - + 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; + if (clock.p2 == 4) + dpll |= PLL_P2_DIVIDE_BY_4; + } + } + + if (is_tv) { + /* XXX: just matching BIOS for now */ +/* dpll |= PLL_REF_INPUT_TVCLKINBC; */ + dpll |= 3; + } +#if 0 + else if (is_lvds) + dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; +#endif + else + dpll |= PLL_REF_INPUT_DREFCLK; + + /* setup pipeconf */ + pipeconf = REG_READ(pipeconf_reg); + + /* Set up the display plane register */ + dspcntr = DISPPLANE_GAMMA_ENABLE; + + if (pipe == 0) + dspcntr |= DISPPLANE_SEL_PIPE_A; + else + dspcntr |= DISPPLANE_SEL_PIPE_B; + + if (pipe == 0 && !IS_I965G(dev)) { + /* Enable pixel doubling when the dot clock is > 90% + * of the (display) core speed. + * + * XXX: No double-wide on 915GM pipe B. + * Is that the only reason for the + * pipe == 0 check? + */ + if (mode->clock > intel_get_core_clock_speed(dev) * 9 / 10) + pipeconf |= PIPEACONF_DOUBLE_WIDE; + else + pipeconf &= ~PIPEACONF_DOUBLE_WIDE; + } + + dspcntr |= DISPLAY_PLANE_ENABLE; + pipeconf |= PIPEACONF_ENABLE; + dpll |= DPLL_VCO_ENABLE; + + + /* Disable the panel fitter if it was on our pipe */ + if (intel_panel_fitter_pipe(dev) == pipe) + REG_WRITE(PFIT_CONTROL, 0); + + DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); + drm_mode_debug_printmodeline(mode); + +#if 0 + if (!xf86ModesEqual(mode, adjusted_mode)) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Adjusted mode for pipe %c:\n", + pipe == 0 ? 'A' : 'B'); + xf86PrintModeline(pScrn->scrnIndex, mode); + } + i830PrintPll("chosen", &clock); +#endif + + if (dpll & DPLL_VCO_ENABLE) { + REG_WRITE(fp_reg, fp); + REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); + REG_READ(dpll_reg); + udelay(150); + } + + /* The LVDS pin pair needs to be on before the DPLLs are enabled. + * This is an exception to the general rule that mode_set doesn't turn + * things on. + */ + if (is_lvds) { + u32 lvds = REG_READ(LVDS); + + lvds |= + LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | + LVDS_PIPEB_SELECT; + /* Set the B0-B3 data pairs corresponding to + * whether we're going to + * set the DPLLs for dual-channel mode or not. + */ + if (clock.p2 == 7) + lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; + else + lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); + + /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) + * appropriately here, but we need to look more + * thoroughly into how panels behave in the two modes. + */ + + REG_WRITE(LVDS, lvds); + REG_READ(LVDS); + } + + REG_WRITE(fp_reg, fp); + REG_WRITE(dpll_reg, dpll); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + + if (IS_I965G(dev)) { + int sdvo_pixel_multiply = + adjusted_mode->clock / mode->clock; + REG_WRITE(dpll_md_reg, + (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | + ((sdvo_pixel_multiply - + 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT)); + } else { + /* write it again -- the BIOS does, after all */ + REG_WRITE(dpll_reg, dpll); + } + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + + REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | + ((adjusted_mode->crtc_htotal - 1) << 16)); + REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | + ((adjusted_mode->crtc_hblank_end - 1) << 16)); + REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | + ((adjusted_mode->crtc_hsync_end - 1) << 16)); + REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | + ((adjusted_mode->crtc_vtotal - 1) << 16)); + REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | + ((adjusted_mode->crtc_vblank_end - 1) << 16)); + REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | + ((adjusted_mode->crtc_vsync_end - 1) << 16)); + /* pipesrc and dspsize control the size that is scaled from, + * which should always be the user's requested size. + */ + REG_WRITE(dspsize_reg, + ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); + REG_WRITE(dsppos_reg, 0); + REG_WRITE(pipesrc_reg, + ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); + REG_WRITE(pipeconf_reg, pipeconf); + REG_READ(pipeconf_reg); + + intel_wait_for_vblank(dev); + + REG_WRITE(dspcntr_reg, dspcntr); + + /* Flush the plane changes */ + { + struct drm_crtc_helper_funcs *crtc_funcs = + crtc->helper_private; + crtc_funcs->mode_set_base(crtc, x, y, old_fb); + } + + intel_wait_for_vblank(dev); + + return 0; +} + +/** Loads the palette/gamma unit for the CRTC with the prepared values */ +void intel_crtc_load_lut(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B; + int i; + + /* The clocks have to be on to load the palette. */ + if (!crtc->enabled) + return; + + for (i = 0; i < 256; i++) { + REG_WRITE(palreg + 4 * i, + (intel_crtc->lut_r[i] << 16) | + (intel_crtc->lut_g[i] << 8) | + intel_crtc->lut_b[i]); + } +} + +static int intel_crtc_cursor_set(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, uint32_t height) +{ + struct drm_device *dev = crtc->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_mode_device *mode_dev = intel_crtc->mode_dev; + int pipe = intel_crtc->pipe; + uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR; + uint32_t base = (pipe == 0) ? CURABASE : CURBBASE; + uint32_t temp; + size_t addr = 0; + size_t size; + void *bo; + int ret; + + DRM_DEBUG("\n"); + + /* if we want to turn of the cursor ignore width and height */ + if (!handle) { + DRM_DEBUG("cursor off\n"); + /* turn of the cursor */ + temp = 0; + temp |= CURSOR_MODE_DISABLE; + + REG_WRITE(control, temp); + REG_WRITE(base, 0); + + /* unpin the old bo */ + if (intel_crtc->cursor_bo) { + mode_dev->bo_unpin_for_scanout(dev, + intel_crtc-> + cursor_bo); + intel_crtc->cursor_bo = NULL; + } + + return 0; + } + + /* Currently we only support 64x64 cursors */ + if (width != 64 || height != 64) { + DRM_ERROR("we currently only support 64x64 cursors\n"); + return -EINVAL; + } + + bo = mode_dev->bo_from_handle(dev, file_priv, handle); + if (!bo) + return -ENOENT; + + ret = mode_dev->bo_pin_for_scanout(dev, bo); + if (ret) + return ret; + + size = mode_dev->bo_size(dev, bo); + if (size < width * height * 4) { + DRM_ERROR("buffer is to small\n"); + return -ENOMEM; + } + + addr = mode_dev->bo_size(dev, bo); + if (mode_dev->cursor_needs_physical) + addr = dev->agp->base + addr; + + intel_crtc->cursor_addr = addr; + temp = 0; + /* set the pipe for the cursor */ + temp |= (pipe << 28); + temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; + + REG_WRITE(control, temp); + REG_WRITE(base, addr); + + /* unpin the old bo */ + if (intel_crtc->cursor_bo && intel_crtc->cursor_bo != bo) { + mode_dev->bo_unpin_for_scanout(dev, intel_crtc->cursor_bo); + intel_crtc->cursor_bo = bo; + } + + return 0; +} + +static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) +{ + struct drm_device *dev = crtc->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + uint32_t temp = 0; + uint32_t adder; + + if (x < 0) { + temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT); + x = -x; + } + if (y < 0) { + temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT); + y = -y; + } + + temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT); + temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); + + adder = intel_crtc->cursor_addr; + REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp); + REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder); + + return 0; +} + +/** Sets the color ramps on behalf of RandR */ +void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, + u16 blue, int regno) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + + intel_crtc->lut_r[regno] = red >> 8; + intel_crtc->lut_g[regno] = green >> 8; + intel_crtc->lut_b[regno] = blue >> 8; +} + +static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, + u16 *green, u16 *blue, uint32_t size) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int i; + + if (size != 256) + return; + + for (i = 0; i < 256; i++) { + intel_crtc->lut_r[i] = red[i] >> 8; + intel_crtc->lut_g[i] = green[i] >> 8; + intel_crtc->lut_b[i] = blue[i] >> 8; + } + + intel_crtc_load_lut(crtc); +} + +/** + * Get a pipe with a simple mode set on it for doing load-based monitor + * detection. + * + * It will be up to the load-detect code to adjust the pipe as appropriate for + * its requirements. The pipe will be connected to no other outputs. + * + * Currently this code will only succeed if there is a pipe with no outputs + * configured for it. In the future, it could choose to temporarily disable + * some outputs to free up a pipe for its use. + * + * \return crtc, or NULL if no pipes are available. + */ + +/* VESA 640x480x72Hz mode to set on the pipe */ +static struct drm_display_mode load_detect_mode = { + DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, + 704, 832, 0, 480, 489, 491, 520, 0, + DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), +}; + +struct drm_crtc *intel_get_load_detect_pipe(struct intel_output + *intel_output, + struct drm_display_mode *mode, + int *dpms_mode) +{ + struct intel_crtc *intel_crtc; + struct drm_crtc *possible_crtc; + struct drm_crtc *supported_crtc = NULL; + struct drm_encoder *encoder = &intel_output->enc; + struct drm_crtc *crtc = NULL; + struct drm_device *dev = encoder->dev; + struct drm_encoder_helper_funcs *encoder_funcs = + encoder->helper_private; + struct drm_crtc_helper_funcs *crtc_funcs; + int i = -1; + + /* + * Algorithm gets a little messy: + * - if the connector already has an assigned crtc, use it (but make + * sure it's on first) + * - try to find the first unused crtc that can drive this connector, + * and use that if we find one + * - if there are no unused crtcs available, try to use the first + * one we found that supports the connector + */ + + /* See if we already have a CRTC for this connector */ + if (encoder->crtc) { + crtc = encoder->crtc; + /* Make sure the crtc and connector are running */ + intel_crtc = to_intel_crtc(crtc); + *dpms_mode = intel_crtc->dpms_mode; + if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { + crtc_funcs = crtc->helper_private; + crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); + encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); + } + return crtc; + } + + /* Find an unused one (if possible) */ + list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, + head) { + i++; + if (!(encoder->possible_crtcs & (1 << i))) + continue; + if (!possible_crtc->enabled) { + crtc = possible_crtc; + break; + } + if (!supported_crtc) + supported_crtc = possible_crtc; + } + + /* + * If we didn't find an unused CRTC, don't use any. + */ + if (!crtc) + return NULL; + + encoder->crtc = crtc; + intel_output->load_detect_temp = true; + + intel_crtc = to_intel_crtc(crtc); + *dpms_mode = intel_crtc->dpms_mode; + + if (!crtc->enabled) { + if (!mode) + mode = &load_detect_mode; + drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb); + } else { + if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { + crtc_funcs = crtc->helper_private; + crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); + } + + /* Add this connector to the crtc */ + encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode); + encoder_funcs->commit(encoder); + } + /* let the connector get through one full cycle before testing */ + intel_wait_for_vblank(dev); + + return crtc; +} + +void intel_release_load_detect_pipe(struct intel_output *intel_output, + int dpms_mode) +{ + struct drm_encoder *encoder = &intel_output->enc; + struct drm_device *dev = encoder->dev; + struct drm_crtc *crtc = encoder->crtc; + struct drm_encoder_helper_funcs *encoder_funcs = + encoder->helper_private; + struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; + + if (intel_output->load_detect_temp) { + encoder->crtc = NULL; + intel_output->load_detect_temp = false; + crtc->enabled = drm_helper_crtc_in_use(crtc); + drm_helper_disable_unused_functions(dev); + } + + /* Switch crtc and output back off if necessary */ + if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) { + if (encoder->crtc == crtc) + encoder_funcs->dpms(encoder, dpms_mode); + crtc_funcs->dpms(crtc, dpms_mode); + } +} + +/* Returns the clock of the currently programmed mode of the given pipe. */ +static int intel_crtc_clock_get(struct drm_device *dev, + struct drm_crtc *crtc) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + u32 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B); + u32 fp; + struct intel_clock_t clock; + + if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) + fp = REG_READ((pipe == 0) ? FPA0 : FPB0); + else + fp = REG_READ((pipe == 0) ? FPA1 : FPB1); + + clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; + clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; + clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; + if (IS_I9XX(dev)) { + clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> + DPLL_FPA01_P1_POST_DIV_SHIFT); + + switch (dpll & DPLL_MODE_MASK) { + case DPLLB_MODE_DAC_SERIAL: + clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? + 5 : 10; + break; + case DPLLB_MODE_LVDS: + clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? + 7 : 14; + break; + default: + DRM_DEBUG("Unknown DPLL mode %08x in programmed " + "mode\n", (int) (dpll & DPLL_MODE_MASK)); + return 0; + } + + /* XXX: Handle the 100Mhz refclk */ + i9xx_clock(96000, &clock); + } else { + bool is_lvds = (pipe == 1) + && (REG_READ(LVDS) & LVDS_PORT_EN); + + if (is_lvds) { + clock.p1 = + ffs((dpll & + DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> + DPLL_FPA01_P1_POST_DIV_SHIFT); + clock.p2 = 14; + + if ((dpll & PLL_REF_INPUT_MASK) == + PLLB_REF_INPUT_SPREADSPECTRUMIN) { + /* XXX: might not be 66MHz */ + i8xx_clock(66000, &clock); + } else + i8xx_clock(48000, &clock); + } else { + if (dpll & PLL_P1_DIVIDE_BY_TWO) + clock.p1 = 2; + else { + clock.p1 = + ((dpll & + DPLL_FPA01_P1_POST_DIV_MASK_I830) >> + DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; + } + if (dpll & PLL_P2_DIVIDE_BY_4) + clock.p2 = 4; + else + clock.p2 = 2; + + i8xx_clock(48000, &clock); + } + } + + /* XXX: It would be nice to validate the clocks, but we can't reuse + * i830PllIsValid() because it relies on the xf86_config connector + * configuration being accurate, which it isn't necessarily. + */ + + return clock.dot; +} + +/** Returns the currently programmed mode of the given pipe. */ +struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, + struct drm_crtc *crtc) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + struct drm_display_mode *mode; + int htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B); + int hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B); + int vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B); + int vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B); + + mode = kzalloc(sizeof(*mode), GFP_KERNEL); + if (!mode) + return NULL; + + mode->clock = intel_crtc_clock_get(dev, crtc); + mode->hdisplay = (htot & 0xffff) + 1; + mode->htotal = ((htot & 0xffff0000) >> 16) + 1; + mode->hsync_start = (hsync & 0xffff) + 1; + mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; + mode->vdisplay = (vtot & 0xffff) + 1; + mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; + mode->vsync_start = (vsync & 0xffff) + 1; + mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; + + drm_mode_set_name(mode); + drm_mode_set_crtcinfo(mode, 0); + + return mode; +} + +static void intel_crtc_destroy(struct drm_crtc *crtc) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + + drm_crtc_cleanup(crtc); + kfree(intel_crtc); +} + +static const struct drm_crtc_helper_funcs intel_helper_funcs = { + .dpms = intel_crtc_dpms, + .mode_fixup = intel_crtc_mode_fixup, + .mode_set = intel_crtc_mode_set, + .mode_set_base = intel_pipe_set_base, + .prepare = intel_crtc_prepare, + .commit = intel_crtc_commit, +}; + +static const struct drm_crtc_helper_funcs mrst_helper_funcs; + +const struct drm_crtc_funcs intel_crtc_funcs = { + .cursor_set = intel_crtc_cursor_set, + .cursor_move = intel_crtc_cursor_move, + .gamma_set = intel_crtc_gamma_set, + .set_config = drm_crtc_helper_set_config, + .destroy = intel_crtc_destroy, +}; + + +void intel_crtc_init(struct drm_device *dev, int pipe, + struct intel_mode_device *mode_dev) +{ + struct intel_crtc *intel_crtc; + int i; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter intel_crtc_init \n"); +#endif /* PRINT_JLIU7 */ + + /* We allocate a extra array of drm_connector pointers + * for fbdev after the crtc */ + intel_crtc = + kzalloc(sizeof(struct intel_crtc) + + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), + GFP_KERNEL); + if (intel_crtc == NULL) + return; + + drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); + + drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); + intel_crtc->pipe = pipe; + for (i = 0; i < 256; i++) { + intel_crtc->lut_r[i] = i; + intel_crtc->lut_g[i] = i; + intel_crtc->lut_b[i] = i; + } + + intel_crtc->mode_dev = mode_dev; + intel_crtc->cursor_addr = 0; + intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; + + if (IS_MRST(dev)) { + drm_crtc_helper_add(&intel_crtc->base, &mrst_helper_funcs); + } else { + drm_crtc_helper_add(&intel_crtc->base, + &intel_helper_funcs); + } + + /* Setup the array of drm_connector pointer array */ + intel_crtc->mode_set.crtc = &intel_crtc->base; + intel_crtc->mode_set.connectors = + (struct drm_connector **) (intel_crtc + 1); + intel_crtc->mode_set.num_connectors = 0; + +#if 0 /* JB: not drop, What should go in here? */ + if (i915_fbpercrtc) +#endif +} + +struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe) +{ + struct drm_crtc *crtc = NULL; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + if (intel_crtc->pipe == pipe) + break; + } + return crtc; +} + +int intel_connector_clones(struct drm_device *dev, int type_mask) +{ + int index_mask = 0; + struct drm_connector *connector; + int entry = 0; + + list_for_each_entry(connector, &dev->mode_config.connector_list, + head) { + struct intel_output *intel_output = + to_intel_output(connector); + if (type_mask & (1 << intel_output->type)) + index_mask |= (1 << entry); + entry++; + } + return index_mask; +} + +#if 0 /* JB: Should be per device */ +static void intel_setup_outputs(struct drm_device *dev) +{ + struct drm_connector *connector; + + intel_crt_init(dev); + + /* Set up integrated LVDS */ + if (IS_MOBILE(dev) && !IS_I830(dev)) + intel_lvds_init(dev); + + if (IS_I9XX(dev)) { + intel_sdvo_init(dev, SDVOB); + intel_sdvo_init(dev, SDVOC); + } else + intel_dvo_init(dev); + + if (IS_I9XX(dev) && !IS_I915G(dev)) + intel_tv_init(dev); + + list_for_each_entry(connector, &dev->mode_config.connector_list, + head) { + struct intel_output *intel_output = + to_intel_output(connector); + struct drm_encoder *encoder = &intel_output->enc; + int crtc_mask = 0, clone_mask = 0; + + /* valid crtcs */ + switch (intel_output->type) { + case INTEL_OUTPUT_DVO: + case INTEL_OUTPUT_SDVO: + crtc_mask = ((1 << 0) | (1 << 1)); + clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | + (1 << INTEL_OUTPUT_DVO) | + (1 << INTEL_OUTPUT_SDVO)); + break; + case INTEL_OUTPUT_ANALOG: + crtc_mask = ((1 << 0) | (1 << 1)); + clone_mask = ((1 << INTEL_OUTPUT_ANALOG) | + (1 << INTEL_OUTPUT_DVO) | + (1 << INTEL_OUTPUT_SDVO)); + break; + case INTEL_OUTPUT_LVDS: + crtc_mask = (1 << 1); + clone_mask = (1 << INTEL_OUTPUT_LVDS); + break; + case INTEL_OUTPUT_TVOUT: + crtc_mask = ((1 << 0) | (1 << 1)); + clone_mask = (1 << INTEL_OUTPUT_TVOUT); + break; + } + encoder->possible_crtcs = crtc_mask; + encoder->possible_clones = + intel_connector_clones(dev, clone_mask); + } +} +#endif + +#if 0 /* JB: Rework framebuffer code into something none device specific */ +static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) +{ + struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); + struct drm_device *dev = fb->dev; + + if (fb->fbdev) + intelfb_remove(dev, fb); + + drm_framebuffer_cleanup(fb); + drm_gem_object_unreference(fb->mm_private); + + kfree(intel_fb); +} + +static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, + struct drm_file *file_priv, + unsigned int *handle) +{ + struct drm_gem_object *object = fb->mm_private; + + return drm_gem_handle_create(file_priv, object, handle); +} + +static const struct drm_framebuffer_funcs intel_fb_funcs = { + .destroy = intel_user_framebuffer_destroy, + .create_handle = intel_user_framebuffer_create_handle, +}; + +struct drm_framebuffer *intel_framebuffer_create(struct drm_device *dev, + struct drm_mode_fb_cmd + *mode_cmd, + void *mm_private) +{ + struct intel_framebuffer *intel_fb; + + intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); + if (!intel_fb) + return NULL; + + if (!drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs)) + return NULL; + + drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); + + return &intel_fb->base; +} + + +static struct drm_framebuffer *intel_user_framebuffer_create(struct + drm_device + *dev, + struct + drm_file + *filp, + struct + drm_mode_fb_cmd + *mode_cmd) +{ + struct drm_gem_object *obj; + + obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle); + if (!obj) + return NULL; + + return intel_framebuffer_create(dev, mode_cmd, obj); +} + +static int intel_insert_new_fb(struct drm_device *dev, + struct drm_file *file_priv, + struct drm_framebuffer *fb, + struct drm_mode_fb_cmd *mode_cmd) +{ + struct intel_framebuffer *intel_fb; + struct drm_gem_object *obj; + struct drm_crtc *crtc; + + intel_fb = to_intel_framebuffer(fb); + + mutex_lock(&dev->struct_mutex); + obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); + + if (!obj) { + mutex_unlock(&dev->struct_mutex); + return -EINVAL; + } + drm_gem_object_unreference(intel_fb->base.mm_private); + drm_helper_mode_fill_fb_struct(fb, mode_cmd, obj); + mutex_unlock(&dev->struct_mutex); + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + if (crtc->fb == fb) { + struct drm_crtc_helper_funcs *crtc_funcs = + crtc->helper_private; + crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y); + } + } + return 0; +} + +static const struct drm_mode_config_funcs intel_mode_funcs = { + .resize_fb = intel_insert_new_fb, + .fb_create = intel_user_framebuffer_create, + .fb_changed = intelfb_probe, +}; +#endif + +#if 0 /* Should be per device */ +void intel_modeset_init(struct drm_device *dev) +{ + int num_pipe; + int i; + + drm_mode_config_init(dev); + + dev->mode_config.min_width = 0; + dev->mode_config.min_height = 0; + + dev->mode_config.funcs = (void *) &intel_mode_funcs; + + if (IS_I965G(dev)) { + dev->mode_config.max_width = 8192; + dev->mode_config.max_height = 8192; + } else { + dev->mode_config.max_width = 2048; + dev->mode_config.max_height = 2048; + } + + /* set memory base */ + if (IS_I9XX(dev)) + dev->mode_config.fb_base = + pci_resource_start(dev->pdev, 2); + else + dev->mode_config.fb_base = + pci_resource_start(dev->pdev, 0); + + if (IS_MOBILE(dev) || IS_I9XX(dev)) + num_pipe = 2; + else + num_pipe = 1; + DRM_DEBUG("%d display pipe%s available.\n", + num_pipe, num_pipe > 1 ? "s" : ""); + + for (i = 0; i < num_pipe; i++) + intel_crtc_init(dev, i); + + intel_setup_outputs(dev); + + /* setup fbs */ + /* drm_initial_config(dev, false); */ +} +#endif + +void intel_modeset_cleanup(struct drm_device *dev) +{ + drm_mode_config_cleanup(dev); +} + + +/* current intel driver doesn't take advantage of encoders + always give back the encoder for the connector +*/ +struct drm_encoder *intel_best_encoder(struct drm_connector *connector) +{ + struct intel_output *intel_output = to_intel_output(connector); + + return &intel_output->enc; +} + +/* MRST_PLATFORM start */ + +#if DUMP_REGISTER +void dump_dc_registers(struct drm_device *dev) +{ + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + unsigned int i = 0; + + DRM_INFO("jliu7 dump_dc_registers\n"); + + + if (0x80000000 & REG_READ(0x70008)) { + for (i = 0x20a0; i < 0x20af; i += 4) { + DRM_INFO("jliu7 interrupt register=0x%x, value=%x\n", i, (unsigned int) REG_READ(i)); + } + + for (i = 0xf014; i < 0xf047; i += 4) { + DRM_INFO + ("jliu7 pipe A dpll register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } + + for (i = 0x60000; i < 0x6005f; i += 4) { + DRM_INFO + ("jliu7 pipe A timing register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } + + for (i = 0x61140; i < 0x61143; i += 4) { + DRM_INFO("jliu7 SDBOB register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } + + for (i = 0x61180; i < 0x6123F; i += 4) { + DRM_INFO + ("jliu7 LVDS PORT register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } + + for (i = 0x61254; i < 0x612AB; i += 4) { + DRM_INFO("jliu7 BLC register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } + + for (i = 0x70000; i < 0x70047; i += 4) { + DRM_INFO + ("jliu7 PIPE A control register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } + + for (i = 0x70180; i < 0x7020b; i += 4) { + DRM_INFO("jliu7 display A control register=0x%x," + "value=%x\n", i, + (unsigned int) REG_READ(i)); + } + + for (i = 0x71400; i < 0x71403; i += 4) { + DRM_INFO + ("jliu7 VGA Display Plane Control register=0x%x," + "value=%x\n", i, (unsigned int) REG_READ(i)); + } + } + + if (0x80000000 & REG_READ(0x71008)) { + for (i = 0x61000; i < 0x6105f; i += 4) { + DRM_INFO + ("jliu7 pipe B timing register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } + + for (i = 0x71000; i < 0x71047; i += 4) { + DRM_INFO + ("jliu7 PIPE B control register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } + + for (i = 0x71180; i < 0x7120b; i += 4) { + DRM_INFO("jliu7 display B control register=0x%x," + "value=%x\n", i, + (unsigned int) REG_READ(i)); + } + } +#if 0 + for (i = 0x70080; i < 0x700df; i += 4) { + DRM_INFO("jliu7 cursor A & B register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); + } +#endif + +} + +void dump_dsi_registers(struct drm_device *dev) +{ + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + unsigned int i = 0; + + DRM_INFO("jliu7 dump_dsi_registers\n"); + + for (i = 0xb000; i < 0xb064; i += 4) { + DRM_INFO("jliu7 MIPI IP register=0x%x, value=%x\n", i, + (unsigned int) REG_READ(i)); + } + + i = 0xb104; + DRM_INFO("jliu7 MIPI control register=0x%x, value=%x\n", + i, (unsigned int) REG_READ(i)); +} +#endif /* DUMP_REGISTER */ + + +struct mrst_limit_t { + struct intel_range_t dot, m, p1; +}; + +struct mrst_clock_t { + /* derived values */ + int dot; + int m; + int p1; +}; + +#define MRST_LIMIT_LVDS_100L 0 +#define MRST_LIMIT_LVDS_83 1 +#define MRST_LIMIT_LVDS_100 2 + +#define MRST_DOT_MIN 19750 +#define MRST_DOT_MAX 120000 +#define MRST_M_MIN_100L 20 +#define MRST_M_MIN_100 10 +#define MRST_M_MIN_83 12 +#define MRST_M_MAX_100L 34 +#define MRST_M_MAX_100 17 +#define MRST_M_MAX_83 20 +#define MRST_P1_MIN 2 +#define MRST_P1_MAX_0 7 +#define MRST_P1_MAX_1 8 + +static const struct mrst_limit_t mrst_limits[] = { + { /* MRST_LIMIT_LVDS_100L */ + .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, + .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L}, + .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1}, + }, + { /* MRST_LIMIT_LVDS_83L */ + .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, + .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83}, + .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0}, + }, + { /* MRST_LIMIT_LVDS_100 */ + .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX}, + .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100}, + .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1}, + }, +}; + +#define MRST_M_MIN 10 +static const u32 mrst_m_converts[] = { + 0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C, + 0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25, + 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c, +}; + +#define COUNT_MAX 0x10000000 +void mrstWaitForPipeDisable(struct drm_device *dev) +{ + int count, temp; + + /* FIXME JLIU7_PO */ + intel_wait_for_vblank(dev); + return; + + /* Wait for for the pipe disable to take effect. */ + for (count = 0; count < COUNT_MAX; count++) { + temp = REG_READ(PIPEACONF); + if ((temp & PIPEACONF_PIPE_STATE) == 0) + break; + } + + if (count == COUNT_MAX) { +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrstWaitForPipeDisable time out. \n"); +#endif /* PRINT_JLIU7 */ + } else { +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrstWaitForPipeDisable cout = %d. \n", + count); +#endif /* PRINT_JLIU7 */ + } +} + +void mrstWaitForPipeEnable(struct drm_device *dev) +{ + int count, temp; + + /* FIXME JLIU7_PO */ + intel_wait_for_vblank(dev); + return; + + /* Wait for for the pipe disable to take effect. */ + for (count = 0; count < COUNT_MAX; count++) { + temp = REG_READ(PIPEACONF); + if ((temp & PIPEACONF_PIPE_STATE) == 1) + break; + } + + if (count == COUNT_MAX) { +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrstWaitForPipeEnable time out. \n"); +#endif /* PRINT_JLIU7 */ + } else { +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrstWaitForPipeEnable cout = %d. \n", + count); +#endif /* PRINT_JLIU7 */ + } +} + +static const struct mrst_limit_t *mrst_limit(struct drm_crtc *crtc) +{ + const struct mrst_limit_t *limit; + struct drm_device *dev = crtc->dev; + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) + || intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) { + if (dev_priv->sku_100L) + limit = &mrst_limits[MRST_LIMIT_LVDS_100L]; + if (dev_priv->sku_83) + limit = &mrst_limits[MRST_LIMIT_LVDS_83]; + if (dev_priv->sku_100) + limit = &mrst_limits[MRST_LIMIT_LVDS_100]; + } else { + limit = NULL; +#if PRINT_JLIU7 + DRM_INFO("JLIU7 jliu7 mrst_limit Wrong display type. \n"); +#endif /* PRINT_JLIU7 */ + } + + return limit; +} + +/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */ +static void mrst_clock(int refclk, struct mrst_clock_t *clock) +{ + clock->dot = (refclk * clock->m) / (14 * clock->p1); +} + +void mrstPrintPll(char *prefix, struct mrst_clock_t *clock) +{ +#if PRINT_JLIU7 + DRM_INFO + ("JLIU7 mrstPrintPll %s: dotclock = %d, m = %d, p1 = %d. \n", + prefix, clock->dot, clock->m, clock->p1); +#endif /* PRINT_JLIU7 */ +} + +/** + * Returns a set of divisors for the desired target clock with the given refclk, + * or FALSE. Divisor values are the actual divisors for + */ +static bool +mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk, + struct mrst_clock_t *best_clock) +{ + struct mrst_clock_t clock; + const struct mrst_limit_t *limit = mrst_limit(crtc); + int err = target; + + memset(best_clock, 0, sizeof(*best_clock)); + + for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) { + for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max; + clock.p1++) { + int this_err; + + mrst_clock(refclk, &clock); + + this_err = abs(clock.dot - target); + if (this_err < err) { + *best_clock = clock; + err = this_err; + } + } + } + DRM_DEBUG("mrstFindBestPLL err = %d.\n", err); + + return err != target; +} + +/** + * Sets the power management mode of the pipe and plane. + * + * This code should probably grow support for turning the cursor off and back + * on appropriately at the same time as we're turning the pipe off/on. + */ +static void mrst_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct drm_device *dev = crtc->dev; + /* struct drm_i915_master_private *master_priv; */ + /* struct drm_i915_private *dev_priv = dev->dev_private; */ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + int pipe = intel_crtc->pipe; + int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B; + int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; + int dspbase_reg = (pipe == 0) ? MRST_DSPABASE : DSPBBASE; + int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; + u32 temp; + bool enabled; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_crtc_dpms, mode = %d, pipe = %d \n", + mode, pipe); +#endif /* PRINT_JLIU7 */ + + /* XXX: When our outputs are all unaware of DPMS modes other than off + * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. + */ + switch (mode) { + case DRM_MODE_DPMS_ON: + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + /* Enable the DPLL */ + temp = REG_READ(dpll_reg); + if ((temp & DPLL_VCO_ENABLE) == 0) { + REG_WRITE(dpll_reg, temp); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + } + + /* Enable the pipe */ + temp = REG_READ(pipeconf_reg); + if ((temp & PIPEACONF_ENABLE) == 0) + REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE); + + /* Enable the plane */ + temp = REG_READ(dspcntr_reg); + if ((temp & DISPLAY_PLANE_ENABLE) == 0) { + REG_WRITE(dspcntr_reg, + temp | DISPLAY_PLANE_ENABLE); + /* Flush the plane changes */ + REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); + } + + intel_crtc_load_lut(crtc); + + /* Give the overlay scaler a chance to enable + if it's on this pipe */ + /* intel_crtc_dpms_video(crtc, true); TODO */ + break; + case DRM_MODE_DPMS_OFF: + /* Give the overlay scaler a chance to disable + * if it's on this pipe */ + /* intel_crtc_dpms_video(crtc, FALSE); TODO */ + + /* Disable the VGA plane that we never use */ + REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); + + /* Disable display plane */ + temp = REG_READ(dspcntr_reg); + if ((temp & DISPLAY_PLANE_ENABLE) != 0) { + REG_WRITE(dspcntr_reg, + temp & ~DISPLAY_PLANE_ENABLE); + /* Flush the plane changes */ + REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); + REG_READ(dspbase_reg); + } + + if (!IS_I9XX(dev)) { + /* Wait for vblank for the disable to take effect */ + intel_wait_for_vblank(dev); + } + + /* Next, disable display pipes */ + temp = REG_READ(pipeconf_reg); + if ((temp & PIPEACONF_ENABLE) != 0) { + REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE); + REG_READ(pipeconf_reg); + } + + /* Wait for for the pipe disable to take effect. */ + mrstWaitForPipeDisable(dev); + + temp = REG_READ(dpll_reg); + if ((temp & DPLL_VCO_ENABLE) != 0) { + REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE); + REG_READ(dpll_reg); + } + + /* Wait for the clocks to turn off. */ + udelay(150); + break; + } + +#if DUMP_REGISTER + dump_dc_registers(dev); +#endif /* DUMP_REGISTER */ + + enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; + +#if 0 /* JB: Add vblank support later */ + if (enabled) + dev_priv->vblank_pipe |= (1 << pipe); + else + dev_priv->vblank_pipe &= ~(1 << pipe); +#endif + + intel_crtc->dpms_mode = mode; + +#if 0 /* JB: Add sarea support later */ + if (!dev->primary->master) + return; + + master_priv = dev->primary->master->driver_priv; + if (!master_priv->sarea_priv) + return; + + switch (pipe) { + case 0: + master_priv->sarea_priv->planeA_w = + enabled ? crtc->mode.hdisplay : 0; + master_priv->sarea_priv->planeA_h = + enabled ? crtc->mode.vdisplay : 0; + break; + case 1: + master_priv->sarea_priv->planeB_w = + enabled ? crtc->mode.hdisplay : 0; + master_priv->sarea_priv->planeB_h = + enabled ? crtc->mode.vdisplay : 0; + break; + default: + DRM_ERROR("Can't update pipe %d in SAREA\n", pipe); + break; + } +#endif +} + +static int mrst_crtc_mode_set(struct drm_crtc *crtc, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode, + int x, int y, + struct drm_framebuffer *old_fb) +{ + struct drm_device *dev = crtc->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + int pipe = intel_crtc->pipe; + int fp_reg = (pipe == 0) ? MRST_FPA0 : FPB0; + int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B; + int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR; + int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; + int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B; + int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B; + int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B; + int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B; + int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B; + int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B; + int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE; + int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC; + int refclk = 0; + struct mrst_clock_t clock; + u32 dpll = 0, fp = 0, dspcntr, pipeconf, lvdsport; + bool ok, is_sdvo = false; + bool is_crt = false, is_lvds = false, is_tv = false; + bool is_mipi = false; + struct drm_mode_config *mode_config = &dev->mode_config; + struct drm_connector *connector; + struct intel_output *intel_output; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_crtc_mode_set \n"); +#endif /* PRINT_JLIU7 */ + + list_for_each_entry(connector, &mode_config->connector_list, head) { + intel_output = to_intel_output(connector); + + if (!connector->encoder + || connector->encoder->crtc != crtc) + continue; + + switch (intel_output->type) { + case INTEL_OUTPUT_LVDS: + is_lvds = true; + break; + case INTEL_OUTPUT_SDVO: + is_sdvo = true; + break; + case INTEL_OUTPUT_TVOUT: + is_tv = true; + break; + case INTEL_OUTPUT_ANALOG: + is_crt = true; + break; + case INTEL_OUTPUT_MIPI: + is_mipi = true; + break; + } + } + + if (is_lvds | is_mipi) { + /*FIXME JLIU7 Get panel power delay parameters from + config data */ + REG_WRITE(0x61208, 0x25807d0); + REG_WRITE(0x6120c, 0x1f407d0); + REG_WRITE(0x61210, 0x270f04); + } + + /* Disable the VGA plane that we never use */ + REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); + + /* Disable the panel fitter if it was on our pipe */ + if (intel_panel_fitter_pipe(dev) == pipe) + REG_WRITE(PFIT_CONTROL, 0); + + DRM_DEBUG("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); + drm_mode_debug_printmodeline(mode); + + REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) | + ((adjusted_mode->crtc_htotal - 1) << 16)); + REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | + ((adjusted_mode->crtc_hblank_end - 1) << 16)); + REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | + ((adjusted_mode->crtc_hsync_end - 1) << 16)); + REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | + ((adjusted_mode->crtc_vtotal - 1) << 16)); + REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | + ((adjusted_mode->crtc_vblank_end - 1) << 16)); + REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | + ((adjusted_mode->crtc_vsync_end - 1) << 16)); + /* pipesrc and dspsize control the size that is scaled from, + * which should always be the user's requested size. + */ + REG_WRITE(dspsize_reg, + ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); + REG_WRITE(pipesrc_reg, + ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); + + /* Flush the plane changes */ + { + struct drm_crtc_helper_funcs *crtc_funcs = + crtc->helper_private; + crtc_funcs->mode_set_base(crtc, x, y, old_fb); + } + + /* setup pipeconf */ + pipeconf = REG_READ(pipeconf_reg); + + /* Set up the display plane register */ + dspcntr = REG_READ(dspcntr_reg); + dspcntr |= DISPPLANE_GAMMA_ENABLE; + + if (pipe == 0) + dspcntr |= DISPPLANE_SEL_PIPE_A; + else + dspcntr |= DISPPLANE_SEL_PIPE_B; + + dev_priv->dspcntr = dspcntr |= DISPLAY_PLANE_ENABLE; + dev_priv->pipeconf = pipeconf |= PIPEACONF_ENABLE; + + if (is_mipi) + return 0; + + if (dev_priv->sku_100L) + refclk = 100000; + else if (dev_priv->sku_83) + refclk = 166000; + else if (dev_priv->sku_100) + refclk = 200000; + + dpll = 0; /*BIT16 = 0 for 100MHz reference */ + + ok = mrstFindBestPLL(crtc, adjusted_mode->clock, refclk, &clock); + + if (!ok) { +#if 0 /* FIXME JLIU7 */ + DRM_ERROR("Couldn't find PLL settings for mode!\n"); + return; +#endif /* FIXME JLIU7 */ +#if PRINT_JLIU7 + DRM_INFO + ("JLIU7 mrstFindBestPLL fail in mrst_crtc_mode_set. \n"); +#endif /* PRINT_JLIU7 */ + } else { +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrst_crtc_mode_set pixel clock = %d," + "m = %x, p1 = %x. \n", clock.dot, clock.m, + clock.p1); +#endif /* PRINT_JLIU7 */ + } + + fp = mrst_m_converts[(clock.m - MRST_M_MIN)] << 8; + + dpll |= DPLL_VGA_MODE_DIS; + + + dpll |= DPLL_VCO_ENABLE; + + if (is_lvds) + dpll |= DPLLA_MODE_LVDS; + else + dpll |= DPLLB_MODE_DAC_SERIAL; + + if (is_sdvo) { + int sdvo_pixel_multiply = + adjusted_mode->clock / mode->clock; + + dpll |= DPLL_DVO_HIGH_SPEED; + dpll |= + (sdvo_pixel_multiply - + 1) << SDVO_MULTIPLIER_SHIFT_HIRES; + } + + + /* compute bitmask from p1 value */ + dpll |= (1 << (clock.p1 - 2)) << 17; + + dpll |= DPLL_VCO_ENABLE; + +#if PRINT_JLIU7 + mrstPrintPll("chosen", &clock); +#endif /* PRINT_JLIU7 */ + +#if 0 + if (!xf86ModesEqual(mode, adjusted_mode)) { + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Adjusted mode for pipe %c:\n", + pipe == 0 ? 'A' : 'B'); + xf86PrintModeline(pScrn->scrnIndex, mode); + } + i830PrintPll("chosen", &clock); +#endif + + if (dpll & DPLL_VCO_ENABLE) { + REG_WRITE(fp_reg, fp); + REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE); + REG_READ(dpll_reg); +/* FIXME jliu7 check the DPLLA lock bit PIPEACONF[29] */ + udelay(150); + } + + /* The LVDS pin pair needs to be on before the DPLLs are enabled. + * This is an exception to the general rule that mode_set doesn't turn + * things on. + */ + if (is_lvds) { + + /* FIXME JLIU7 need to support 24bit panel */ +#if MRST_24BIT_LVDS + lvdsport = + (REG_READ(LVDS) & (~LVDS_PIPEB_SELECT)) | LVDS_PORT_EN + | LVDS_A3_POWER_UP | LVDS_A0A2_CLKA_POWER_UP; + +#if MRST_24BIT_DOT_1 + lvdsport |= MRST_PANEL_24_DOT_1_FORMAT; +#endif /* MRST_24BIT_DOT_1 */ + +#else /* MRST_24BIT_LVDS */ + lvdsport = + (REG_READ(LVDS) & (~LVDS_PIPEB_SELECT)) | LVDS_PORT_EN; +#endif /* MRST_24BIT_LVDS */ + +#if MRST_24BIT_WA + lvdsport = 0x80300340; +#else /* MRST_24BIT_DOT_WA */ + lvdsport = 0x82300300; +#endif /* MRST_24BIT_DOT_WA */ + + REG_WRITE(LVDS, lvdsport); + REG_READ(LVDS); + } + + REG_WRITE(fp_reg, fp); + REG_WRITE(dpll_reg, dpll); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + + /* write it again -- the BIOS does, after all */ + REG_WRITE(dpll_reg, dpll); + REG_READ(dpll_reg); + /* Wait for the clocks to stabilize. */ + udelay(150); + + REG_WRITE(pipeconf_reg, pipeconf); + REG_READ(pipeconf_reg); + + /* Wait for for the pipe enable to take effect. */ + mrstWaitForPipeEnable(dev); + + REG_WRITE(dspcntr_reg, dspcntr); + intel_wait_for_vblank(dev); + + return 0; +} + + +static const struct drm_crtc_helper_funcs mrst_helper_funcs = { + .dpms = mrst_crtc_dpms, + .mode_fixup = intel_crtc_mode_fixup, + .mode_set = mrst_crtc_mode_set, + .mode_set_base = intel_pipe_set_base, + .prepare = intel_crtc_prepare, + .commit = intel_crtc_commit, +}; + +/* MRST_PLATFORM end */ --- /dev/null +++ b/drivers/staging/psb/intel_display.h @@ -0,0 +1,31 @@ + +/* copyright (c) 2008, Intel Corporation + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + */ + +#ifndef _INTEL_DISPLAY_H_ +#define _INTEL_DISPLAY_H_ + +bool intel_pipe_has_type(struct drm_crtc *crtc, int type); + +#endif --- /dev/null +++ b/drivers/staging/psb/intel_drv.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2006 Dave Airlie + * Copyright (c) 2007 Intel Corporation + * Jesse Barnes + */ +#ifndef __INTEL_DRV_H__ +#define __INTEL_DRV_H__ + +#include +#include +#include +#include + +#include + +/* + * MOORESTOWN defines + */ +#define MRST_I2C 0 + +#define DUMP_REGISTER 0 +#define MRST_24BIT_LVDS 1 +#define MRST_24BIT_DOT_1 0 +#define MRST_24BIT_WA 0 + +#define PRINT_JLIU7 0 +#define DELAY_TIME1 80 /* 1000 = 1ms */ + +/* + * Display related stuff + */ + +/* store information about an Ixxx DVO */ +/* The i830->i865 use multiple DVOs with multiple i2cs */ +/* the i915, i945 have a single sDVO i2c bus - which is different */ +#define MAX_OUTPUTS 6 +/* maximum connectors per crtcs in the mode set */ +#define INTELFB_CONN_LIMIT 4 + +#define INTEL_I2C_BUS_DVO 1 +#define INTEL_I2C_BUS_SDVO 2 + +/* these are outputs from the chip - integrated only + * external chips are via DVO or SDVO output */ +#define INTEL_OUTPUT_UNUSED 0 +#define INTEL_OUTPUT_ANALOG 1 +#define INTEL_OUTPUT_DVO 2 +#define INTEL_OUTPUT_SDVO 3 +#define INTEL_OUTPUT_LVDS 4 +#define INTEL_OUTPUT_TVOUT 5 +#define INTEL_OUTPUT_MIPI 6 + +#define INTEL_DVO_CHIP_NONE 0 +#define INTEL_DVO_CHIP_LVDS 1 +#define INTEL_DVO_CHIP_TMDS 2 +#define INTEL_DVO_CHIP_TVOUT 4 + +/** + * Hold information useally put on the device driver privates here, + * since it needs to be shared across multiple of devices drivers privates. + */ +struct intel_mode_device { + + /* + * Abstracted memory manager operations + */ + void *(*bo_from_handle) (struct drm_device *dev, + struct drm_file *file_priv, + unsigned int handle); + size_t(*bo_size) (struct drm_device *dev, void *bo); + size_t(*bo_offset) (struct drm_device *dev, void *bo); + int (*bo_pin_for_scanout) (struct drm_device *dev, void *bo); + int (*bo_unpin_for_scanout) (struct drm_device *dev, void *bo); + + /* + * Cursor + */ + int cursor_needs_physical; + + /* + * LVDS info + */ + int backlight_duty_cycle; /* restore backlight to this value */ + bool panel_wants_dither; + struct drm_display_mode *panel_fixed_mode; + struct drm_display_mode *vbt_mode; /* if any */ + + uint32_t saveBLC_PWM_CTL; +}; + +struct intel_i2c_chan { + /* for getting at dev. private (mmio etc.) */ + struct drm_device *drm_dev; + u32 reg; /* GPIO reg */ + struct i2c_adapter adapter; + struct i2c_algo_bit_data algo; + u8 slave_addr; +}; + +struct intel_output { + struct drm_connector base; + + struct drm_encoder enc; + int type; + struct intel_i2c_chan *i2c_bus; /* for control functions */ + struct intel_i2c_chan *ddc_bus; /* for DDC only stuff */ + bool load_detect_temp; + void *dev_priv; + + struct intel_mode_device *mode_dev; + +}; + +struct intel_crtc { + struct drm_crtc base; + int pipe; + int plane; + uint32_t cursor_addr; + u8 lut_r[256], lut_g[256], lut_b[256]; + int dpms_mode; + struct intel_framebuffer *fbdev_fb; + /* a mode_set for fbdev users on this crtc */ + struct drm_mode_set mode_set; + + /* current bo we scanout from */ + void *scanout_bo; + + /* current bo we cursor from */ + void *cursor_bo; + + struct intel_mode_device *mode_dev; +}; + +#define to_intel_crtc(x) container_of(x, struct intel_crtc, base) +#define to_intel_output(x) container_of(x, struct intel_output, base) +#define enc_to_intel_output(x) container_of(x, struct intel_output, enc) +#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) + +struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev, + const u32 reg, const char *name); +void intel_i2c_destroy(struct intel_i2c_chan *chan); +int intel_ddc_get_modes(struct intel_output *intel_output); +extern bool intel_ddc_probe(struct intel_output *intel_output); + +extern void intel_crtc_init(struct drm_device *dev, int pipe, + struct intel_mode_device *mode_dev); +extern void intel_crt_init(struct drm_device *dev); +extern void intel_sdvo_init(struct drm_device *dev, int output_device); +extern void intel_dvo_init(struct drm_device *dev); +extern void intel_tv_init(struct drm_device *dev); +extern void intel_lvds_init(struct drm_device *dev, + struct intel_mode_device *mode_dev); +extern void mrst_lvds_init(struct drm_device *dev, + struct intel_mode_device *mode_dev); +extern void mrst_dsi_init(struct drm_device *dev, + struct intel_mode_device *mode_dev); + +extern void intel_crtc_load_lut(struct drm_crtc *crtc); +extern void intel_encoder_prepare(struct drm_encoder *encoder); +extern void intel_encoder_commit(struct drm_encoder *encoder); + +extern struct drm_encoder *intel_best_encoder(struct drm_connector + *connector); + +extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, + struct drm_crtc *crtc); +extern void intel_wait_for_vblank(struct drm_device *dev); +extern struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, + int pipe); +extern struct drm_crtc *intel_get_load_detect_pipe + (struct intel_output *intel_output, + struct drm_display_mode *mode, int *dpms_mode); +extern void intel_release_load_detect_pipe(struct intel_output + *intel_output, int dpms_mode); + +extern struct drm_connector *intel_sdvo_find(struct drm_device *dev, + int sdvoB); +extern int intel_sdvo_supports_hotplug(struct drm_connector *connector); +extern void intel_sdvo_set_hotplug(struct drm_connector *connector, + int enable); +extern int intelfb_probe(struct drm_device *dev); +extern int intelfb_remove(struct drm_device *dev, + struct drm_framebuffer *fb); +extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, + u16 green, u16 blue, int regno); + +extern struct drm_framebuffer *intel_framebuffer_create(struct drm_device + *dev, struct + drm_mode_fb_cmd + *mode_cmd, + void *mm_private); +#endif /* __INTEL_DRV_H__ */ --- /dev/null +++ b/drivers/staging/psb/intel_dsi.c @@ -0,0 +1,1644 @@ +/* + * Copyright © 2006-2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * jim liu + */ + +#include +#include +#include + +#define DRM_MODE_ENCODER_MIPI 5 +#define DRM_MODE_CONNECTOR_MIPI 13 + +#if DUMP_REGISTER +extern void dump_dsi_registers(struct drm_device *dev); +#endif /* DUMP_REGISTER */ + +int dsi_backlight; /* restore backlight to this value */ + +/** + * Returns the maximum level of the backlight duty cycle field. + */ +static u32 mrst_dsi_get_max_backlight(struct drm_device *dev) +{ +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_get_max_backlight \n"); +#endif /* PRINT_JLIU7 */ + + return BRIGHTNESS_MAX_LEVEL; + +/* FIXME jliu7 need to revisit */ +} + +/** + * Sets the backlight level. + * + * \param level backlight level, from 0 to intel_dsi_get_max_backlight(). + */ +static void mrst_dsi_set_backlight(struct drm_device *dev, int level) +{ + u32 blc_pwm_ctl; + u32 max_pwm_blc; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_set_backlight \n"); +#endif /* PRINT_JLIU7 */ + +#if 1 /* FIXME JLIU7 */ + return; +#endif /* FIXME JLIU7 */ + + /* Provent LVDS going to total black */ + if (level < 20) + level = 20; + + max_pwm_blc = mrst_lvds_get_PWM_ctrl_freq(dev); + + if (max_pwm_blc ==0) + { + return; + } + + blc_pwm_ctl = level * max_pwm_blc / BRIGHTNESS_MAX_LEVEL; + + if (blc_pol == BLC_POLARITY_INVERSE) { + blc_pwm_ctl = max_pwm_blc - blc_pwm_ctl; + } + + REG_WRITE(BLC_PWM_CTL, + (max_pwm_blc << MRST_BACKLIGHT_MODULATION_FREQ_SHIFT) | + blc_pwm_ctl); +} + +/** + * Sets the power state for the panel. + */ +static void mrst_dsi_set_power(struct drm_device *dev, + struct intel_output *output, bool on) +{ + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + u32 pp_status; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_set_power \n"); +#endif /* PRINT_JLIU7 */ + /* + * The DIS device must be ready before we can change power state. + */ + if (!dev_priv->dsi_device_ready) + { + return; + } + + /* + * We don't support dual DSI yet. May be in POR in the future. + */ + if (dev_priv->dual_display) + { + return; + } + + if (on) { + if (dev_priv->dpi & (!dev_priv->dpi_panel_on)) + { + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrst_dsi_set_power dpi = on \n"); +#endif /* PRINT_JLIU7 */ + REG_WRITE(DPI_CONTROL_REG, DPI_TURN_ON); +#if 0 /*FIXME JLIU7 */ + REG_WRITE(DPI_DATA_REG, DPI_BACK_LIGHT_ON_DATA); + REG_WRITE(DPI_CONTROL_REG, DPI_BACK_LIGHT_ON); +#endif /*FIXME JLIU7 */ + + dev_priv->dpi_panel_on = true; + + REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | + POWER_TARGET_ON); + do { + pp_status = REG_READ(PP_STATUS); + } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); + } + else if ((!dev_priv->dpi) & (!dev_priv->dbi_panel_on)) + { +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrst_dsi_set_power dbi = on \n"); +#endif /* PRINT_JLIU7 */ + + dev_priv->DBI_CB_pointer = 0; + /* exit sleep mode */ + *(dev_priv->p_DBI_commandBuffer + dev_priv->DBI_CB_pointer++) = exit_sleep_mode; + +#if 0 /*FIXME JLIU7 */ + /* Check MIPI Adatper command registers */ + while (REG_READ(MIPI_COMMAND_ADDRESS_REG) & BIT0); +#endif /*FIXME JLIU7 */ + + /* FIXME_jliu7 mapVitualToPhysical(dev_priv->p_DBI_commandBuffer);*/ + REG_WRITE(MIPI_COMMAND_LENGTH_REG, 1); + REG_WRITE(MIPI_COMMAND_ADDRESS_REG, (u32)dev_priv->p_DBI_commandBuffer | BIT0); + + /* The host processor must wait five milliseconds after sending exit_sleep_mode command before sending another + command. This delay allows the supply voltages and clock circuits to stabilize */ + udelay(5000); + + dev_priv->DBI_CB_pointer = 0; + + /* set display on */ + *(dev_priv->p_DBI_commandBuffer + dev_priv->DBI_CB_pointer++) = set_display_on ; + +#if 0 /*FIXME JLIU7 */ + /* Check MIPI Adatper command registers */ + while (REG_READ(MIPI_COMMAND_ADDRESS_REG) & BIT0); +#endif /*FIXME JLIU7 */ + + /* FIXME_jliu7 mapVitualToPhysical(dev_priv->p_DBI_commandBuffer);*/ + REG_WRITE(MIPI_COMMAND_LENGTH_REG, 1); + REG_WRITE(MIPI_COMMAND_ADDRESS_REG, (u32)dev_priv->p_DBI_commandBuffer | BIT0); + + dev_priv->dbi_panel_on = true; + } +/*FIXME JLIU7 */ +/* Need to figure out how to control the MIPI panel power on sequence*/ + + mrst_dsi_set_backlight(dev, dsi_backlight); + } + else + { + mrst_dsi_set_backlight(dev, 0); +/*FIXME JLIU7 */ +/* Need to figure out how to control the MIPI panel power down sequence*/ + /* + * Only save the current backlight value if we're going from + * on to off. + */ + if (dev_priv->dpi & dev_priv->dpi_panel_on) + { +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrst_dsi_set_power dpi = off \n"); +#endif /* PRINT_JLIU7 */ + + REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & + ~POWER_TARGET_ON); + do { + pp_status = REG_READ(PP_STATUS); + } while (pp_status & PP_ON); + +#if 0 /*FIXME JLIU7 */ + REG_WRITE(DPI_DATA_REG, DPI_BACK_LIGHT_OFF_DATA); + REG_WRITE(DPI_CONTROL_REG, DPI_BACK_LIGHT_OFF); +#endif /*FIXME JLIU7 */ + REG_WRITE(DPI_CONTROL_REG, DPI_SHUT_DOWN); + dev_priv->dpi_panel_on = false; + } + else if ((!dev_priv->dpi) & dev_priv->dbi_panel_on) + { +#if PRINT_JLIU7 + DRM_INFO("JLIU7 mrst_dsi_set_power dbi = off \n"); +#endif /* PRINT_JLIU7 */ + dev_priv->DBI_CB_pointer = 0; + /* enter sleep mode */ + *(dev_priv->p_DBI_commandBuffer + dev_priv->DBI_CB_pointer++) = enter_sleep_mode; + + /* Check MIPI Adatper command registers */ + while (REG_READ(MIPI_COMMAND_ADDRESS_REG) & BIT0); + + /* FIXME_jliu7 mapVitualToPhysical(dev_priv->p_DBI_commandBuffer);*/ + REG_WRITE(MIPI_COMMAND_LENGTH_REG, 1); + REG_WRITE(MIPI_COMMAND_ADDRESS_REG, (u32)dev_priv->p_DBI_commandBuffer | BIT0); + dev_priv->dbi_panel_on = false; + } + } +} + +static void mrst_dsi_dpms(struct drm_encoder *encoder, int mode) +{ + struct drm_device *dev = encoder->dev; + struct intel_output *output = enc_to_intel_output(encoder); + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_dpms \n"); +#endif /* PRINT_JLIU7 */ + + if (mode == DRM_MODE_DPMS_ON) + mrst_dsi_set_power(dev, output, true); + else + mrst_dsi_set_power(dev, output, false); + + /* XXX: We never power down the DSI pairs. */ +} + +static void mrst_dsi_save(struct drm_connector *connector) +{ +#if 0 /* JB: Disable for drop */ + struct drm_device *dev = connector->dev; + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_save \n"); +#endif /* PRINT_JLIU7 */ + + dev_priv->savePP_ON = REG_READ(LVDSPP_ON); + dev_priv->savePP_OFF = REG_READ(LVDSPP_OFF); + dev_priv->savePP_CONTROL = REG_READ(PP_CONTROL); + dev_priv->savePP_CYCLE = REG_READ(PP_CYCLE); + dev_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); + dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & + BACKLIGHT_DUTY_CYCLE_MASK); + + /* + * make backlight to full brightness + */ + dsi_backlight = mrst_dsi_get_max_backlight(dev); +#endif +} + +static void mrst_dsi_restore(struct drm_connector *connector) +{ +#if 0 /* JB: Disable for drop */ + struct drm_device *dev = connector->dev; + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_restore \n"); +#endif /* PRINT_JLIU7 */ + + REG_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); + REG_WRITE(LVDSPP_ON, dev_priv->savePP_ON); + REG_WRITE(LVDSPP_OFF, dev_priv->savePP_OFF); + REG_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE); + REG_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); + if (dev_priv->savePP_CONTROL & POWER_TARGET_ON) + mrst_dsi_set_power(dev, true); + else + mrst_dsi_set_power(dev, false); +#endif +} + +static void mrst_dsi_prepare(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct intel_output *output = enc_to_intel_output(encoder); + struct intel_mode_device *mode_dev = output->mode_dev; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_prepare \n"); +#endif /* PRINT_JLIU7 */ + + mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); + mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL & + BACKLIGHT_DUTY_CYCLE_MASK); + + mrst_dsi_set_power(dev, output, false); +} + +static void mrst_dsi_commit( struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct intel_output *output = enc_to_intel_output(encoder); + struct intel_mode_device *mode_dev = output->mode_dev; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_commit \n"); +#endif /* PRINT_JLIU7 */ + + if (mode_dev->backlight_duty_cycle == 0) + mode_dev->backlight_duty_cycle = + mrst_dsi_get_max_backlight(dev); + + mrst_dsi_set_power(dev, output, true); + +#if DUMP_REGISTER + dump_dsi_registers(dev); +#endif /* DUMP_REGISTER */ +} + +/* ************************************************************************* *\ +FUNCTION: GetHS_TX_timeoutCount + ` +DESCRIPTION: In burst mode, value greater than one DPI line Time in byte clock + (txbyteclkhs). To timeout this timer 1+ of the above said value is recommended. + + In non-burst mode, Value greater than one DPI frame time in byte clock(txbyteclkhs). + To timeout this timer 1+ of the above said value is recommended. + +\* ************************************************************************* */ +static u32 GetHS_TX_timeoutCount(DRM_DRIVER_PRIVATE_T *dev_priv) +{ + + u32 timeoutCount = 0, HTOT_count = 0, VTOT_count = 0, HTotalPixel = 0; + + /* Total pixels need to be transfer per line*/ + HTotalPixel = (dev_priv->HsyncWidth + dev_priv->HbackPorch + dev_priv->HfrontPorch) * dev_priv->laneCount + dev_priv->HactiveArea; + + /* byte count = (pixel count * bits per pixel) / 8 */ + HTOT_count = (HTotalPixel * dev_priv->bpp) / 8; + + if (dev_priv->videoModeFormat == BURST_MODE) + { + timeoutCount = HTOT_count + 1; +#if 1 /*FIXME remove it after power-on */ + VTOT_count = dev_priv->VactiveArea + dev_priv->VbackPorch + dev_priv->VfrontPorch + + dev_priv->VsyncWidth; + /* timeoutCount = (HTOT_count * VTOT_count) + 1; */ + timeoutCount = (HTOT_count * VTOT_count) + 1; +#endif + } + else + { + VTOT_count = dev_priv->VactiveArea + dev_priv->VbackPorch + dev_priv->VfrontPorch + + dev_priv->VsyncWidth; + /* timeoutCount = (HTOT_count * VTOT_count) + 1; */ + timeoutCount = (HTOT_count * VTOT_count) + 1; + } + + return timeoutCount & 0xFFFF; +} + +/* ************************************************************************* *\ +FUNCTION: GetLP_RX_timeoutCount + +DESCRIPTION: The timeout value is protocol specific. Time out value is calculated + from txclkesc(50ns). + + Minimum value = + Time to send one Trigger message = 4 X txclkesc [Escape mode entry sequence) + + 8-bit trigger message (2x8xtxclkesc) + +1 txclksesc [stop_state] + = 21 X txclkesc [ 15h] + + Maximum Value = + Time to send a long packet with maximum payload data + = 4 X txclkesc [Escape mode entry sequence) + + 8-bit Low power data transmission Command (2x8xtxclkesc) + + packet header [ 4X8X2X txclkesc] + +payload [ nX8X2Xtxclkesc] + +CRC[2X8X2txclkesc] + +1 txclksesc [stop_state] + = 117 txclkesc +n[payload in terms of bytes]X16txclkesc. + +\* ************************************************************************* */ +static u32 GetLP_RX_timeoutCount(DRM_DRIVER_PRIVATE_T *dev_priv) +{ + + u32 timeoutCount = 0; + + if (dev_priv->config_phase) + { + /* Assuming 256 byte DDB data.*/ + timeoutCount = 117 + 256 * 16; + } + else + { + /* For DPI video only mode use the minimum value.*/ + timeoutCount = 0x15; +#if 1 /*FIXME remove it after power-on */ + /* Assuming 256 byte DDB data.*/ + timeoutCount = 117 + 256 * 16; +#endif + } + + return timeoutCount; +} + +/* ************************************************************************* *\ +FUNCTION: GetHSA_Count + +DESCRIPTION: Shows the horizontal sync value in terms of byte clock + (txbyteclkhs) + Minimum HSA period should be sufficient to transmit a hsync start short + packet(4 bytes) + i) For Non-burst Mode with sync pulse, Min value – 4 in decimal [plus + an optional 6 bytes for a zero payload blanking packet]. But if + the value is less than 10 but more than 4, then this count will + be added to the HBP’s count for one lane. + ii) For Non-Burst Sync Event & Burst Mode, there is no HSA, so you + can program this to zero. If you program this register, these + byte values will be added to HBP. + iii) For Burst mode of operation, normally the values programmed in + terms of byte clock are based on the principle - time for transfering + HSA in Burst mode is the same as in non-bust mode. +\* ************************************************************************* */ +static u32 GetHSA_Count(DRM_DRIVER_PRIVATE_T *dev_priv) +{ + u32 HSA_count; + u32 HSA_countX8; + + /* byte clock count = (pixel clock count * bits per pixel) /8 */ + HSA_countX8 = dev_priv->HsyncWidth * dev_priv->bpp; + + if (dev_priv->videoModeFormat == BURST_MODE) + { + HSA_countX8 *= dev_priv->DDR_Clock / dev_priv->DDR_Clock_Calculated; + } + + HSA_count = HSA_countX8 / 8; + + return HSA_count; +} + +/* ************************************************************************* *\ +FUNCTION: GetHBP_Count + +DESCRIPTION: Shows the horizontal back porch value in terms of txbyteclkhs. + Minimum HBP period should be sufficient to transmit a “hsync end short + packet(4 bytes) + Blanking packet overhead(6 bytes) + RGB packet header(4 bytes)” + For Burst mode of operation, normally the values programmed in terms of + byte clock are based on the principle - time for transfering HBP + in Burst mode is the same as in non-bust mode. + + Min value – 14 in decimal [ accounted with zero payload for blanking packet] for one lane. + Max value – any value greater than 14 based on DPI resolution +\* ************************************************************************* */ +static u32 GetHBP_Count(DRM_DRIVER_PRIVATE_T *dev_priv) +{ + u32 HBP_count; + u32 HBP_countX8; + + /* byte clock count = (pixel clock count * bits per pixel) /8 */ + HBP_countX8 = dev_priv->HbackPorch * dev_priv->bpp; + + if (dev_priv->videoModeFormat == BURST_MODE) + { + HBP_countX8 *= dev_priv->DDR_Clock / dev_priv->DDR_Clock_Calculated; + } + + HBP_count = HBP_countX8 / 8; + + return HBP_count; +} + +/* ************************************************************************* *\ +FUNCTION: GetHFP_Count + +DESCRIPTION: Shows the horizontal front porch value in terms of txbyteclkhs. + Minimum HFP period should be sufficient to transmit “RGB Data packet + footer(2 bytes) + Blanking packet overhead(6 bytes)” for non burst mode. + + For burst mode, Minimum HFP period should be sufficient to transmit + Blanking packet overhead(6 bytes)” + + For Burst mode of operation, normally the values programmed in terms of + byte clock are based on the principle - time for transfering HFP + in Burst mode is the same as in non-bust mode. + + Min value – 8 in decimal for non-burst mode [accounted with zero payload + for blanking packet] for one lane. + Min value – 6 in decimal for burst mode for one lane. + + Max value – any value greater than the minimum vaue based on DPI resolution +\* ************************************************************************* */ +static u32 GetHFP_Count(DRM_DRIVER_PRIVATE_T *dev_priv) +{ + u32 HFP_count; + u32 HFP_countX8; + + /* byte clock count = (pixel clock count * bits per pixel) /8 */ + HFP_countX8 = dev_priv->HfrontPorch * dev_priv->bpp; + + if (dev_priv->videoModeFormat == BURST_MODE) + { + HFP_countX8 *= dev_priv->DDR_Clock / dev_priv->DDR_Clock_Calculated; + } + + HFP_count = HFP_countX8 / 8; + + return HFP_count; +} + +/* ************************************************************************* *\ +FUNCTION: GetHAdr_Count + +DESCRIPTION: Shows the horizontal active area value in terms of txbyteclkhs. + In Non Burst Mode, Count equal to RGB word count value + + In Burst Mode, RGB pixel packets are time-compressed, leaving more time + during a scan line for LP mode (saving power) or for multiplexing + other transmissions onto the DSI link. Hence, the count equals the + time in txbyteclkhs for sending time compressed RGB pixels plus + the time needed for moving to power save mode or the time needed + for secondary channel to use the DSI link. + + But if the left out time for moving to low power mode is less than + 8 txbyteclkhs [2txbyteclkhs for RGB data packet footer and + 6txbyteclkhs for a blanking packet with zero payload], then + this count will be added to the HFP's count for one lane. + + Min value – 8 in decimal for non-burst mode [accounted with zero payload + for blanking packet] for one lane. + Min value – 6 in decimal for burst mode for one lane. + + Max value – any value greater than the minimum vaue based on DPI resolution +\* ************************************************************************* */ +static u32 GetHAdr_Count(DRM_DRIVER_PRIVATE_T *dev_priv) +{ + u32 HAdr_count; + u32 HAdr_countX8; + + /* byte clock count = (pixel clock count * bits per pixel) /8 */ + HAdr_countX8 = dev_priv->HactiveArea * dev_priv->bpp; + + if (dev_priv->videoModeFormat == BURST_MODE) + { + HAdr_countX8 *= dev_priv->DDR_Clock / dev_priv->DDR_Clock_Calculated; + } + + HAdr_count = HAdr_countX8 / 8; + + return HAdr_count; +} + +/* ************************************************************************* *\ +FUNCTION: GetHighLowSwitchCount + +DESCRIPTION: High speed to low power or Low power to high speed switching time + in terms byte clock (txbyteclkhs). This value is based on the + byte clock (txbyteclkhs) and low power clock frequency (txclkesc) + + Typical value - Number of byte clocks required to switch from low power mode + to high speed mode after "txrequesths" is asserted. + + The worst count value among the low to high or high to low switching time + in terms of txbyteclkhs has to be programmed in this register. + + Usefull Formulae: + DDR clock period = 2 times UI + txbyteclkhs clock = 8 times UI + Tlpx = 1 / txclkesc + CALCULATION OF LOW POWER TO HIGH SPEED SWITCH COUNT VALUE (from Standard D-PHY spec) + LP01 + LP00 + HS0 = 1Tlpx + 1Tlpx + 3Tlpx [Approx] + 1DDR clock [2UI] + 1txbyteclkhs clock [8UI] + CALCULATION OF HIGH SPEED TO LOW POWER SWITCH COUNT VALUE (from Standard D-PHY spec) + Ths-trail = 1txbyteclkhs clock [8UI] + 5DDR clock [10UI] + 4 Tlpx [Approx] +\* ************************************************************************* */ +static u32 GetHighLowSwitchCount(DRM_DRIVER_PRIVATE_T *dev_priv) +{ + u32 HighLowSwitchCount, HighToLowSwitchCount, LowToHighSwitchCount; + +/* ************************************************************************* *\ + CALCULATION OF HIGH SPEED TO LOW POWER SWITCH COUNT VALUE (from Standard D-PHY spec) + Ths-trail = 1txbyteclkhs clock [8UI] + 5DDR clock [10UI] + 4 Tlpx [Approx] + + Tlpx = 50 ns, Using max txclkesc (20MHz) + + txbyteclkhs_period = 4000 / dev_priv->DDR_Clock; in ns + UI_period = 500 / dev_priv->DDR_Clock; in ns + + HS_to_LP = Ths-trail = 18 * UI_period + 4 * Tlpx + = 9000 / dev_priv->DDR_Clock + 200; + + HighToLowSwitchCount = HS_to_LP / txbyteclkhs_period + = (9000 / dev_priv->DDR_Clock + 200) / (4000 / dev_priv->DDR_Clock) + = (9000 + (200 * dev_priv->DDR_Clock)) / 4000 + +\* ************************************************************************* */ + HighToLowSwitchCount = (9000 + (200 * dev_priv->DDR_Clock)) / 4000 + 1; + +/* ************************************************************************* *\ + CALCULATION OF LOW POWER TO HIGH SPEED SWITCH COUNT VALUE (from Standard D-PHY spec) + LP01 + LP00 + HS0 = 1Tlpx + 1Tlpx + 3Tlpx [Approx] + 1DDR clock [2UI] + 1txbyteclkhs clock [8UI] + + LP_to_HS = 10 * UI_period + 5 * Tlpx = + = 5000 / dev_priv->DDR_Clock + 250; + + LowToHighSwitchCount = LP_to_HS / txbyteclkhs_period + = (5000 / dev_priv->DDR_Clock + 250) / (4000 / dev_priv->DDR_Clock) + = (5000 + (250 * dev_priv->DDR_Clock)) / 4000 + +\* ************************************************************************* */ + LowToHighSwitchCount = (5000 + (250 * dev_priv->DDR_Clock)) / 4000 + 1; + + if (HighToLowSwitchCount > LowToHighSwitchCount) + { + HighLowSwitchCount = HighToLowSwitchCount; + } + else + { + HighLowSwitchCount = LowToHighSwitchCount; + } + + + /* FIXME jliu need to fine tune the above formulae and remove the following after power on */ + if (HighLowSwitchCount < 0x1f) + HighLowSwitchCount = 0x1f; + + return HighLowSwitchCount; +} + +/* ************************************************************************* *\ +FUNCTION: mrst_gen_long_write + ` +DESCRIPTION: + +\* ************************************************************************* */ +static void mrst_gen_long_write(struct drm_device *dev, u32 *data, u16 wc,u8 vc) +{ + u32 gen_data_reg = HS_GEN_DATA_REG; + u32 gen_ctrl_reg = HS_GEN_CTRL_REG; + u32 date_full_bit = HS_DATA_FIFO_FULL; + u32 control_full_bit = HS_CTRL_FIFO_FULL; + u16 wc_saved = wc; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_gen_long_write \n"); +#endif /* PRINT_JLIU7 */ + + /* sanity check */ + if (vc > 4) + { + DRM_ERROR(KERN_ERR "MIPI Virtual channel Can't greater than 4. \n"); + return; + } + + + if (0) /* FIXME JLIU7 check if it is in LP*/ + { + gen_data_reg = LP_GEN_DATA_REG; + gen_ctrl_reg = LP_GEN_CTRL_REG; + date_full_bit = LP_DATA_FIFO_FULL; + control_full_bit = LP_CTRL_FIFO_FULL; + } + + while (wc >= 4) + { + /* Check if MIPI IP generic data fifo is not full */ + while ((REG_READ(GEN_FIFO_STAT_REG) & date_full_bit) == date_full_bit); + + /* write to data buffer */ + REG_WRITE(gen_data_reg, *data); + + wc -= 4; + data ++; + } + + switch (wc) + { + case 1: + REG_WRITE8(gen_data_reg, *((u8 *)data)); + break; + case 2: + REG_WRITE16(gen_data_reg, *((u16 *)data)); + break; + case 3: + REG_WRITE16(gen_data_reg, *((u16 *)data)); + data = (u32*)((u8*) data + 2); + REG_WRITE8(gen_data_reg, *((u8 *)data)); + break; + } + + /* Check if MIPI IP generic control fifo is not full */ + while ((REG_READ(GEN_FIFO_STAT_REG) & control_full_bit) == control_full_bit); + /* write to control buffer */ + REG_WRITE(gen_ctrl_reg, 0x29 | (wc_saved << 8) | (vc << 6)); +} + +/* ************************************************************************* *\ +FUNCTION: mrst_init_HIMAX_MIPI_bridge + ` +DESCRIPTION: + +\* ************************************************************************* */ +static void mrst_init_HIMAX_MIPI_bridge(struct drm_device *dev) +{ + u32 gen_data[2]; + u16 wc = 0; + u8 vc =0; + u32 gen_data_intel = 0x200105; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_init_HIMAX_MIPI_bridge \n"); +#endif /* PRINT_JLIU7 */ + + /* exit sleep mode */ + wc = 0x5; + gen_data[0] = gen_data_intel | (0x11 << 24); + gen_data[1] = 0; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_pixel_format */ + gen_data[0] = gen_data_intel | (0x3A << 24); + gen_data[1] = 0x77; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* Set resolution for (800X480) */ + wc = 0x8; + gen_data[0] = gen_data_intel | (0x2A << 24); + gen_data[1] = 0x1F030000; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[0] = gen_data_intel | (0x2B << 24); + gen_data[1] = 0xDF010000; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* System control */ + wc = 0x6; + gen_data[0] = gen_data_intel | (0xEE << 24); + gen_data[1] = 0x10FA; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* INPUT TIMING FOR TEST PATTERN(800X480) */ + /* H-size */ + gen_data[1] = 0x2000; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0301; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* V-size */ + gen_data[1] = 0xE002; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0103; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* H-total */ + gen_data[1] = 0x2004; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0405; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* V-total */ + gen_data[1] = 0x0d06; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0207; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* H-blank */ + gen_data[1] = 0x0308; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0009; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* H-blank */ + gen_data[1] = 0x030A; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x000B; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* H-start */ + gen_data[1] = 0xD80C; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x000D; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* V-start */ + gen_data[1] = 0x230E; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x000F; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* RGB domain */ + gen_data[1] = 0x0027; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* INP_FORM Setting */ + /* set_1 */ + gen_data[1] = 0x1C10; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_2 */ + gen_data[1] = 0x0711; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_3 */ + gen_data[1] = 0x0012; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_4 */ + gen_data[1] = 0x0013; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_5 */ + gen_data[1] = 0x2314; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_6 */ + gen_data[1] = 0x0015; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_7 */ + gen_data[1] = 0x2316; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_8 */ + gen_data[1] = 0x0017; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_1 */ + gen_data[1] = 0x0330; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* FRC Setting */ + /* FRC_set_2 */ + gen_data[1] = 0x237A; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* FRC_set_3 */ + gen_data[1] = 0x4C7B; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* FRC_set_4 */ + gen_data[1] = 0x037C; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* FRC_set_5 */ + gen_data[1] = 0x3482; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* FRC_set_7 */ + gen_data[1] = 0x1785; + mrst_gen_long_write(dev, gen_data, wc, vc); + +#if 0 + /* FRC_set_8 */ + gen_data[1] = 0xD08F; + mrst_gen_long_write(dev, gen_data, wc, vc); +#endif + + /* OUTPUT TIMING FOR TEST PATTERN (800X480) */ + /* out_htotal */ + gen_data[1] = 0x2090; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0491; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* out_hsync */ + gen_data[1] = 0x0392; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0093; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* out_hstart */ + gen_data[1] = 0xD894; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0095; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* out_hsize */ + gen_data[1] = 0x2096; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0397; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* out_vtotal */ + gen_data[1] = 0x0D98; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x0299; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* out_vsync */ + gen_data[1] = 0x039A; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x009B; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* out_vstart */ + gen_data[1] = 0x239C; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x009D; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* out_vsize */ + gen_data[1] = 0xE09E; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x019F; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* FRC_set_6 */ + gen_data[1] = 0x9084; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* Other setting */ + gen_data[1] = 0x0526; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* RBG domain */ + gen_data[1] = 0x1177; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* rgbw */ + /* set_1 */ + gen_data[1] = 0xD28F; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_2 */ + gen_data[1] = 0x02D0; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_3 */ + gen_data[1] = 0x08D1; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_4 */ + gen_data[1] = 0x05D2; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_5 */ + gen_data[1] = 0x24D4; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* set_6 */ + gen_data[1] = 0x00D5; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x02D7; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x00D8; + mrst_gen_long_write(dev, gen_data, wc, vc); + + gen_data[1] = 0x48F3; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0xD4F2; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x3D8E; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x60FD; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x00B5; + mrst_gen_long_write(dev, gen_data, wc, vc); + gen_data[1] = 0x48F4; + mrst_gen_long_write(dev, gen_data, wc, vc); + + /* inside patten */ + gen_data[1] = 0x0060; + mrst_gen_long_write(dev, gen_data, wc, vc); +} + +/* ************************************************************************* *\ +FUNCTION: mrst_init_NSC_MIPI_bridge + ` +DESCRIPTION: + +\* ************************************************************************* */ +static void mrst_init_NSC_MIPI_bridge(struct drm_device *dev) +{ + + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_init_NSC_MIPI_bridge.\n"); +#endif /* PRINT_JLIU7 */ + /* Program MIPI IP to 50MHz DSI, Non-Burst mode with sync event, + 1 or 2 Data Lanes */ + + udelay(DELAY_TIME1); + /* enable RGB24*/ + REG_WRITE(LP_GEN_CTRL_REG, 0x003205e3); + + udelay(DELAY_TIME1); + /* enable all error reporting*/ + REG_WRITE(LP_GEN_CTRL_REG, 0x000040e3); + udelay(DELAY_TIME1); + REG_WRITE(LP_GEN_CTRL_REG, 0x000041e3); + + udelay(DELAY_TIME1); + /* enable 2 data lane; video shaping & error reporting */ + REG_WRITE(LP_GEN_CTRL_REG, 0x00a842e3); /* 0x006842e3 for 1 data lane */ + + udelay(DELAY_TIME1); + /* HS timeout */ + REG_WRITE(LP_GEN_CTRL_REG, 0x009243e3); + + udelay(DELAY_TIME1); + /* setle = 6h; low power timeout = ((2^21)-1)*4TX_esc_clks. */ + REG_WRITE(LP_GEN_CTRL_REG, 0x00e645e3); + + /* enable all virtual channels */ + REG_WRITE(LP_GEN_CTRL_REG, 0x000f46e3); + + /* set output strength to low-drive */ + REG_WRITE(LP_GEN_CTRL_REG, 0x00007de3); + + if (dev_priv->sku_83) + { + /* set escape clock to divede by 8 */ + REG_WRITE(LP_GEN_CTRL_REG, 0x000044e3); + } + else if(dev_priv->sku_100L) + { + /* set escape clock to divede by 16 */ + REG_WRITE(LP_GEN_CTRL_REG, 0x001044e3); + } + else if(dev_priv->sku_100) + { + /* set escape clock to divede by 32*/ + REG_WRITE(LP_GEN_CTRL_REG, 0x003044e3); + + /* setle = 6h; low power timeout = ((2^21)-1)*4TX_esc_clks. */ + REG_WRITE(LP_GEN_CTRL_REG, 0x00ec45e3); + } + + /* CFG_VALID=1; RGB_CLK_EN=1. */ + REG_WRITE(LP_GEN_CTRL_REG, 0x00057fe3); + +} + +static void mrst_dsi_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = encoder->dev; + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + u32 pfit_control; + u32 dsiFuncPrgValue = 0; + u32 SupportedFormat = 0; + u32 channelNumber = 0; + u32 DBI_dataWidth = 0; + u32 resolution = 0; + u32 mipiport = 0; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_mode_set \n"); +#endif /* PRINT_JLIU7 */ + + switch (dev_priv->bpp) + { + case 16: + SupportedFormat = RGB_565_FMT; + break; + case 18: + SupportedFormat = RGB_666_FMT; + break; + case 24: + SupportedFormat = RGB_888_FMT; + break; + default: + DRM_INFO("mrst_dsi_mode_set, invalid bpp \n"); + break; + } + + resolution = dev_priv->HactiveArea | (dev_priv->VactiveArea << RES_V_POS); + + if (dev_priv->dpi) + { + /* Enable automatic panel scaling for non-native modes so that they fill + * the screen. Should be enabled before the pipe is enabled, according to + * register description and PRM. + */ + /*FIXME JLIU7, enable Auto-scale only */ + /* + * Enable automatic panel scaling so that non-native modes fill the + * screen. Should be enabled before the pipe is enabled, according to + * register description and PRM. + */ +#if 0 /*JLIU7_PO */ + if (mode->hdisplay != adjusted_mode->hdisplay || + mode->vdisplay != adjusted_mode->vdisplay) + { + pfit_control = PFIT_ENABLE; + } + else +#endif /*JLIU7_PO */ + { + pfit_control = 0; + } + REG_WRITE(PFIT_CONTROL, pfit_control); + + /* Enable MIPI Port */ + mipiport = MIPI_PORT_EN; + REG_WRITE(MIPI, mipiport); + + /* JLIU7_FIXME set MIPI clock ratio to 1:1 for NSC init */ + REG_WRITE(MIPI_CONTROL_REG, 0x00000018); + + /* Enable all the error interrupt */ + REG_WRITE(INTR_EN_REG, 0xffffffff); + REG_WRITE(TURN_AROUND_TIMEOUT_REG, 0x0000000F); + REG_WRITE(DEVICE_RESET_REG, 0x000000ff); /* old value = 0x00000015 may depends on the DSI RX device*/ + REG_WRITE(INIT_COUNT_REG, 0x00000fff); /* Minimum value = 0x000007d0 */ + + SupportedFormat <<= FMT_DPI_POS; + dsiFuncPrgValue = dev_priv->laneCount | SupportedFormat; + REG_WRITE(DSI_FUNC_PRG_REG, dsiFuncPrgValue); + + REG_WRITE(DPI_RESOLUTION_REG, resolution); + REG_WRITE(DBI_RESOLUTION_REG, 0x00000000); + + REG_WRITE(VERT_SYNC_PAD_COUNT_REG, dev_priv->VsyncWidth); + REG_WRITE(VERT_BACK_PORCH_COUNT_REG, dev_priv->VbackPorch); + REG_WRITE(VERT_FRONT_PORCH_COUNT_REG, dev_priv->VfrontPorch); + +#if 1 /*JLIU7_PO hard coded for NSC PO */ + REG_WRITE(HORIZ_SYNC_PAD_COUNT_REG, 0x1e); + REG_WRITE(HORIZ_BACK_PORCH_COUNT_REG, 0x18); + REG_WRITE(HORIZ_FRONT_PORCH_COUNT_REG, 0x8); + REG_WRITE(HORIZ_ACTIVE_AREA_COUNT_REG, 0x4b0); +#else /*JLIU7_PO hard coded for NSC PO */ + REG_WRITE(HORIZ_SYNC_PAD_COUNT_REG, GetHSA_Count(dev_priv)); + REG_WRITE(HORIZ_BACK_PORCH_COUNT_REG, GetHBP_Count(dev_priv)); + REG_WRITE(HORIZ_FRONT_PORCH_COUNT_REG, GetHFP_Count(dev_priv)); + REG_WRITE(HORIZ_ACTIVE_AREA_COUNT_REG, GetHAdr_Count(dev_priv)); +#endif /*JLIU7_PO hard coded for NSC PO */ + REG_WRITE(VIDEO_FMT_REG, dev_priv->videoModeFormat); + } + else + { + /* JLIU7 FIXME VIRTUAL_CHANNEL_NUMBER_1 or VIRTUAL_CHANNEL_NUMBER_0*/ + channelNumber = VIRTUAL_CHANNEL_NUMBER_1 << DBI_CHANNEL_NUMBER_POS; + DBI_dataWidth = DBI_DATA_WIDTH_16BIT << DBI_DATA_WIDTH_POS; + dsiFuncPrgValue = dev_priv->laneCount | channelNumber | DBI_dataWidth; + /* JLIU7 FIXME */ + SupportedFormat <<= FMT_DBI_POS; + dsiFuncPrgValue |= SupportedFormat; + REG_WRITE(DSI_FUNC_PRG_REG, dsiFuncPrgValue); + + REG_WRITE(DPI_RESOLUTION_REG, 0x00000000); + REG_WRITE(DBI_RESOLUTION_REG, resolution); + } + +#if 1 /*JLIU7_PO hard code for NSC PO */ + REG_WRITE(HS_TX_TIMEOUT_REG, 0xffff); + REG_WRITE(LP_RX_TIMEOUT_REG, 0xffff); + + REG_WRITE(HIGH_LOW_SWITCH_COUNT_REG, 0x46); +#else /*JLIU7_PO hard code for NSC PO */ + REG_WRITE(HS_TX_TIMEOUT_REG, GetHS_TX_timeoutCount(dev_priv)); + REG_WRITE(LP_RX_TIMEOUT_REG, GetLP_RX_timeoutCount(dev_priv)); + + REG_WRITE(HIGH_LOW_SWITCH_COUNT_REG, GetHighLowSwitchCount(dev_priv)); +#endif /*JLIU7_PO hard code for NSC PO */ + + + REG_WRITE(EOT_DISABLE_REG, 0x00000000); + + /* FIXME JLIU7 for NSC PO */ + REG_WRITE(LP_BYTECLK_REG, 0x00000004); + + REG_WRITE(DEVICE_READY_REG, 0x00000001); + REG_WRITE(DPI_CONTROL_REG, 0x00000002); /* Turn On */ + + dev_priv->dsi_device_ready = true; + +#if 0 /*JLIU7_PO */ + mrst_init_HIMAX_MIPI_bridge(dev); +#endif /*JLIU7_PO */ + mrst_init_NSC_MIPI_bridge(dev); + + if (dev_priv->sku_100L) + /* Set DSI link to 100MHz; 2:1 clock ratio */ + REG_WRITE(MIPI_CONTROL_REG, 0x00000009); + + REG_WRITE(PIPEACONF, dev_priv->pipeconf); + REG_READ(PIPEACONF); + + /* Wait for 20ms for the pipe enable to take effect. */ + udelay(20000); + + /* JLIU7_PO hard code for NSC PO Program the display FIFO watermarks */ + REG_WRITE(DSPARB, 0x00001d9c); + REG_WRITE(DSPFW1, 0xfc0f0f18); + REG_WRITE(DSPFW5, 0x04140404); + REG_WRITE(DSPFW6, 0x000001f0); + + REG_WRITE(DSPACNTR, dev_priv->dspcntr); + + /* Wait for 20ms for the plane enable to take effect. */ + udelay(20000); +} + +/** + * Detect the MIPI connection. + * + * This always returns CONNECTOR_STATUS_CONNECTED. + * This connector should only have + * been set up if the MIPI was actually connected anyway. + */ +static enum drm_connector_status mrst_dsi_detect(struct drm_connector + *connector) +{ +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_detect \n"); +#endif /* PRINT_JLIU7 */ + + return connector_status_connected; +} + +/** + * Return the list of MIPI DDB modes if available. + */ +static int mrst_dsi_get_modes(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct intel_output *intel_output = to_intel_output(connector); + struct intel_mode_device *mode_dev = intel_output->mode_dev; + +/* FIXME get the MIPI DDB modes */ + + /* Didn't get an DDB, so + * Set wide sync ranges so we get all modes + * handed to valid_mode for checking + */ + connector->display_info.min_vfreq = 0; + connector->display_info.max_vfreq = 200; + connector->display_info.min_hfreq = 0; + connector->display_info.max_hfreq = 200; + + if (mode_dev->panel_fixed_mode != NULL) { + struct drm_display_mode *mode = + drm_mode_duplicate(dev, mode_dev->panel_fixed_mode); + drm_mode_probed_add(connector, mode); + return 1; + } + + return 0; +} + +static const struct drm_encoder_helper_funcs mrst_dsi_helper_funcs = { + .dpms = mrst_dsi_dpms, + .mode_fixup = intel_lvds_mode_fixup, + .prepare = mrst_dsi_prepare, + .mode_set = mrst_dsi_mode_set, + .commit = mrst_dsi_commit, +}; + +static const struct drm_connector_helper_funcs + mrst_dsi_connector_helper_funcs = { + .get_modes = mrst_dsi_get_modes, + .mode_valid = intel_lvds_mode_valid, + .best_encoder = intel_best_encoder, +}; + +static const struct drm_connector_funcs mrst_dsi_connector_funcs = { + .save = mrst_dsi_save, + .restore = mrst_dsi_restore, + .detect = mrst_dsi_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = intel_lvds_destroy, +}; + +/** Returns the panel fixed mode from configuration. */ +/** FIXME JLIU7 need to revist it. */ +struct drm_display_mode *mrst_dsi_get_configuration_mode(struct drm_device *dev) +{ + struct drm_display_mode *mode; + + mode = kzalloc(sizeof(*mode), GFP_KERNEL); + if (!mode) + return NULL; + +#if 1 /*FIXME jliu7 remove it later */ + /* copy from SV - hard coded fixed mode for DSI TPO TD043MTEA2 LCD panel */ + mode->hdisplay = 800; + mode->vdisplay = 480; + mode->hsync_start = 808; + mode->hsync_end = 848; + mode->htotal = 880; + mode->vsync_start = 482; + mode->vsync_end = 483; + mode->vtotal = 486; + mode->clock = 33264; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for DSI TPO TD043MTEA2 LCD panel */ + mode->hdisplay = 800; + mode->vdisplay = 480; + mode->hsync_start = 836; + mode->hsync_end = 846; + mode->htotal = 1056; + mode->vsync_start = 489; + mode->vsync_end = 491; + mode->vtotal = 525; + mode->clock = 33264; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for LVDS 800x480 */ + mode->hdisplay = 800; + mode->vdisplay = 480; + mode->hsync_start = 801; + mode->hsync_end = 802; + mode->htotal = 1024; + mode->vsync_start = 481; + mode->vsync_end = 482; + mode->vtotal = 525; + mode->clock = 30994; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later, jliu7 modify it according to the spec */ + /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */ + mode->hdisplay = 1024; + mode->vdisplay = 600; + mode->hsync_start = 1072; + mode->hsync_end = 1104; + mode->htotal = 1184; + mode->vsync_start = 603; + mode->vsync_end = 604; + mode->vtotal = 608; + mode->clock = 53990; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it, it is copied from SBIOS */ + /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */ + mode->hdisplay = 1024; + mode->vdisplay = 600; + mode->hsync_start = 1104; + mode->hsync_end = 1136; + mode->htotal = 1184; + mode->vsync_start = 603; + mode->vsync_end = 604; + mode->vtotal = 608; + mode->clock = 53990; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for Sharp wsvga LVDS 1024x600 */ + mode->hdisplay = 1024; + mode->vdisplay = 600; + mode->hsync_start = 1124; + mode->hsync_end = 1204; + mode->htotal = 1312; + mode->vsync_start = 607; + mode->vsync_end = 610; + mode->vtotal = 621; + mode->clock = 48885; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for LVDS 1024x768 */ + mode->hdisplay = 1024; + mode->vdisplay = 768; + mode->hsync_start = 1048; + mode->hsync_end = 1184; + mode->htotal = 1344; + mode->vsync_start = 771; + mode->vsync_end = 777; + mode->vtotal = 806; + mode->clock = 65000; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for LVDS 1366x768 */ + mode->hdisplay = 1366; + mode->vdisplay = 768; + mode->hsync_start = 1430; + mode->hsync_end = 1558; + mode->htotal = 1664; + mode->vsync_start = 769; + mode->vsync_end = 770; + mode->vtotal = 776; + mode->clock = 77500; +#endif /*FIXME jliu7 remove it later */ + + drm_mode_set_name(mode); + drm_mode_set_crtcinfo(mode, 0); + + return mode; +} + +/* ************************************************************************* *\ +FUNCTION: mrstDSI_clockInit + ` +DESCRIPTION: + +\* ************************************************************************* */ +static u32 sku_83_mipi_2xclk[4] = {166667, 333333, 444444, 666667}; +static u32 sku_100_mipi_2xclk[4] = {200000, 400000, 533333, 800000}; +static u32 sku_100L_mipi_2xclk[4] = {100000, 200000, 266667, 400000}; +#define MIPI_2XCLK_COUNT 0x04 + +static bool mrstDSI_clockInit(DRM_DRIVER_PRIVATE_T *dev_priv) +{ + u32 Htotal = 0, Vtotal = 0, RRate = 0, mipi_2xclk = 0; + u32 i = 0; + u32 *p_mipi_2xclk = NULL; + + (void)GetHS_TX_timeoutCount; + (void)GetLP_RX_timeoutCount; + (void)GetHSA_Count; + (void)GetHBP_Count; + (void)GetHFP_Count; + (void)GetHAdr_Count; + (void)GetHighLowSwitchCount; + (void)mrst_init_HIMAX_MIPI_bridge; + +#if 0 /* JLIU7_PO old values */ + /* FIXME jliu7 DPI hard coded for TPO TD043MTEA2 LCD panel */ + dev_priv->pixelClock = 33264; /*KHz*/ + dev_priv->HsyncWidth = 10; + dev_priv->HbackPorch = 210; + dev_priv->HfrontPorch = 36; + dev_priv->HactiveArea = 800; + dev_priv->VsyncWidth = 2; + dev_priv->VbackPorch = 34; + dev_priv->VfrontPorch = 9; + dev_priv->VactiveArea = 480; + dev_priv->bpp = 24; + + /* FIXME jliu7 DBI hard coded for TPO TD043MTEA2 LCD panel */ + dev_priv->dbi_pixelClock = 33264; /*KHz*/ + dev_priv->dbi_HsyncWidth = 10; + dev_priv->dbi_HbackPorch = 210; + dev_priv->dbi_HfrontPorch = 36; + dev_priv->dbi_HactiveArea = 800; + dev_priv->dbi_VsyncWidth = 2; + dev_priv->dbi_VbackPorch = 34; + dev_priv->dbi_VfrontPorch = 9; + dev_priv->dbi_VactiveArea = 480; + dev_priv->dbi_bpp = 24; +#else /* JLIU7_PO old values */ + /* FIXME jliu7 DPI hard coded for TPO TD043MTEA2 LCD panel */ + /* FIXME Pre-Si value, 1 or 2 lanes; 50MHz; Non-Burst w/ sync event */ + dev_priv->pixelClock = 33264; /*KHz*/ + dev_priv->HsyncWidth = 10; + dev_priv->HbackPorch = 8; + dev_priv->HfrontPorch = 3; + dev_priv->HactiveArea = 800; + dev_priv->VsyncWidth = 2; + dev_priv->VbackPorch = 3; + dev_priv->VfrontPorch = 2; + dev_priv->VactiveArea = 480; + dev_priv->bpp = 24; + + /* FIXME jliu7 DBI hard coded for TPO TD043MTEA2 LCD panel */ + dev_priv->dbi_pixelClock = 33264; /*KHz*/ + dev_priv->dbi_HsyncWidth = 10; + dev_priv->dbi_HbackPorch = 8; + dev_priv->dbi_HfrontPorch = 3; + dev_priv->dbi_HactiveArea = 800; + dev_priv->dbi_VsyncWidth = 2; + dev_priv->dbi_VbackPorch = 3; + dev_priv->dbi_VfrontPorch = 2; + dev_priv->dbi_VactiveArea = 480; + dev_priv->dbi_bpp = 24; +#endif /* JLIU7_PO old values */ + + Htotal = dev_priv->HsyncWidth + dev_priv->HbackPorch + dev_priv->HfrontPorch + dev_priv->HactiveArea; + Vtotal = dev_priv->VsyncWidth + dev_priv->VbackPorch + dev_priv->VfrontPorch + dev_priv->VactiveArea; + + RRate = ((dev_priv->pixelClock * 1000) / (Htotal * Vtotal)) + 1; + + dev_priv->RRate = RRate; + + /* ddr clock frequence = (pixel clock frequence * bits per pixel)/2*/ + mipi_2xclk = (dev_priv->pixelClock * dev_priv->bpp) / dev_priv->laneCount; /* KHz */ + dev_priv->DDR_Clock_Calculated = mipi_2xclk / 2; /* KHz */ + + DRM_DEBUG("mrstDSI_clockInit RRate = %d, mipi_2xclk = %d. \n", RRate, mipi_2xclk); + + if (dev_priv->sku_100) + { + p_mipi_2xclk = sku_100_mipi_2xclk; + } + else if (dev_priv->sku_100L) + { + p_mipi_2xclk = sku_100L_mipi_2xclk; + } + else + { + p_mipi_2xclk = sku_83_mipi_2xclk; + } + + for (; i < MIPI_2XCLK_COUNT; i++) + { + if ((dev_priv->DDR_Clock_Calculated * 2) < p_mipi_2xclk[i]) + break; + } + + if (i == MIPI_2XCLK_COUNT) + { + DRM_DEBUG("mrstDSI_clockInit the DDR clock is too big, DDR_Clock_Calculated is = %d\n", dev_priv->DDR_Clock_Calculated); + return false; + } + + dev_priv->DDR_Clock = p_mipi_2xclk[i] / 2; + dev_priv->ClockBits = i; + +#if 0 /*JLIU7_PO */ +#if 0 /* FIXME remove it after power on*/ + mipiControlReg = REG_READ(MIPI_CONTROL_REG) & (~MIPI_2X_CLOCK_BITS); + mipiControlReg |= i; + REG_WRITE(MIPI_CONTROL_REG, mipiControlReg); +#else /* FIXME remove it after power on*/ + mipiControlReg |= i; + REG_WRITE(MIPI_CONTROL_REG, mipiControlReg); +#endif /* FIXME remove it after power on*/ +#endif /*JLIU7_PO */ + +#if 1 /* FIXME remove it after power on*/ + DRM_DEBUG("mrstDSI_clockInit, mipi_2x_clock_divider = 0x%x, DDR_Clock_Calculated is = %d\n", i, dev_priv->DDR_Clock_Calculated); +#endif /* FIXME remove it after power on*/ + + return true; +} + +/** + * mrst_dsi_init - setup MIPI connectors on this device + * @dev: drm device + * + * Create the connector, try to figure out what + * modes we can display on the MIPI panel (if present). + */ +void mrst_dsi_init(struct drm_device *dev, + struct intel_mode_device *mode_dev) +{ + DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private; + struct intel_output *intel_output; + struct drm_connector *connector; + struct drm_encoder *encoder; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_dsi_init \n"); +#endif /* PRINT_JLIU7 */ + + intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); + if (!intel_output) + return; + + intel_output->mode_dev = mode_dev; + connector = &intel_output->base; + encoder = &intel_output->enc; + drm_connector_init(dev, &intel_output->base, + &mrst_dsi_connector_funcs, + DRM_MODE_CONNECTOR_MIPI); + + drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs, + DRM_MODE_ENCODER_MIPI); + + drm_mode_connector_attach_encoder(&intel_output->base, + &intel_output->enc); + intel_output->type = INTEL_OUTPUT_MIPI; + + drm_encoder_helper_add(encoder, &mrst_dsi_helper_funcs); + drm_connector_helper_add(connector, + &mrst_dsi_connector_helper_funcs); + connector->display_info.subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = false; + connector->doublescan_allowed = false; + + dsi_backlight = BRIGHTNESS_MAX_LEVEL; + blc_pol = BLC_POLARITY_INVERSE; + blc_freq = 0xc8; + + /* + * MIPI discovery: + * 1) check for DDB data + * 2) check for VBT data + * 4) make sure lid is open + * if closed, act like it's not there for now + */ + + /* FIXME jliu7 we only support DPI */ + dev_priv->dpi = true; + + /* FIXME hard coded 4 lanes for Himax HX8858-A, 2 lanes for NSC LM2550 */ + dev_priv->laneCount = 2; + + /* FIXME hard coded for NSC PO. */ + /* We only support BUST_MODE */ + dev_priv->videoModeFormat = NON_BURST_MODE_SYNC_EVENTS; /* BURST_MODE */ + /* FIXME change it to true if GET_DDB works */ + dev_priv->config_phase = false; + + if (!mrstDSI_clockInit(dev_priv)) + { + DRM_DEBUG("Can't iniitialize MRST DSI clock.\n"); +#if 0 /* FIXME JLIU7 */ + goto failed_find; +#endif /* FIXME JLIU7 */ + } + + /* + * If we didn't get DDB data, try geting panel timing + * from configuration data + */ + mode_dev->panel_fixed_mode = mrst_dsi_get_configuration_mode(dev); + + if (mode_dev->panel_fixed_mode) { + mode_dev->panel_fixed_mode->type |= + DRM_MODE_TYPE_PREFERRED; + goto out; /* FIXME: check for quirks */ + } + + /* If we still don't have a mode after all that, give up. */ + if (!mode_dev->panel_fixed_mode) { + DRM_DEBUG + ("Found no modes on the lvds, ignoring the LVDS\n"); + goto failed_find; + } + +out: + drm_sysfs_connector_add(connector); + return; + +failed_find: + DRM_DEBUG("No MIIP modes found, disabling.\n"); + drm_encoder_cleanup(encoder); + drm_connector_cleanup(connector); + kfree(connector); +} --- /dev/null +++ b/drivers/staging/psb/intel_i2c.c @@ -0,0 +1,179 @@ +/* + * Copyright © 2006-2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + */ +/* + * Copyright (c) 2006 Dave Airlie + * Jesse Barnes + */ + +#include +#include +#include + +/* + * Intel GPIO access functions + */ + +#define I2C_RISEFALL_TIME 20 + +static int get_clock(void *data) +{ + struct intel_i2c_chan *chan = data; + struct drm_device *dev = chan->drm_dev; + u32 val; + + val = REG_READ(chan->reg); + return (val & GPIO_CLOCK_VAL_IN) != 0; +} + +static int get_data(void *data) +{ + struct intel_i2c_chan *chan = data; + struct drm_device *dev = chan->drm_dev; + u32 val; + + val = REG_READ(chan->reg); + return (val & GPIO_DATA_VAL_IN) != 0; +} + +static void set_clock(void *data, int state_high) +{ + struct intel_i2c_chan *chan = data; + struct drm_device *dev = chan->drm_dev; + u32 reserved = 0, clock_bits; + + /* On most chips, these bits must be preserved in software. */ + if (!IS_I830(dev) && !IS_845G(dev)) + reserved = + REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | + GPIO_CLOCK_PULLUP_DISABLE); + + if (state_high) + clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; + else + clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | + GPIO_CLOCK_VAL_MASK; + REG_WRITE(chan->reg, reserved | clock_bits); + udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */ +} + +static void set_data(void *data, int state_high) +{ + struct intel_i2c_chan *chan = data; + struct drm_device *dev = chan->drm_dev; + u32 reserved = 0, data_bits; + + /* On most chips, these bits must be preserved in software. */ + if (!IS_I830(dev) && !IS_845G(dev)) + reserved = + REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | + GPIO_CLOCK_PULLUP_DISABLE); + + if (state_high) + data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; + else + data_bits = + GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | + GPIO_DATA_VAL_MASK; + + REG_WRITE(chan->reg, reserved | data_bits); + udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */ +} + +/** + * intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg + * @dev: DRM device + * @output: driver specific output device + * @reg: GPIO reg to use + * @name: name for this bus + * + * Creates and registers a new i2c bus with the Linux i2c layer, for use + * in output probing and control (e.g. DDC or SDVO control functions). + * + * Possible values for @reg include: + * %GPIOA + * %GPIOB + * %GPIOC + * %GPIOD + * %GPIOE + * %GPIOF + * %GPIOG + * %GPIOH + * see PRM for details on how these different busses are used. + */ +struct intel_i2c_chan *intel_i2c_create(struct drm_device *dev, + const u32 reg, const char *name) +{ + struct intel_i2c_chan *chan; + + chan = kzalloc(sizeof(struct intel_i2c_chan), GFP_KERNEL); + if (!chan) + goto out_free; + + chan->drm_dev = dev; + chan->reg = reg; + snprintf(chan->adapter.name, I2C_NAME_SIZE, "intel drm %s", name); + chan->adapter.owner = THIS_MODULE; + chan->adapter.algo_data = &chan->algo; + chan->adapter.dev.parent = &dev->pdev->dev; + chan->algo.setsda = set_data; + chan->algo.setscl = set_clock; + chan->algo.getsda = get_data; + chan->algo.getscl = get_clock; + chan->algo.udelay = 20; + chan->algo.timeout = usecs_to_jiffies(2200); + chan->algo.data = chan; + + i2c_set_adapdata(&chan->adapter, chan); + + if (i2c_bit_add_bus(&chan->adapter)) + goto out_free; + + /* JJJ: raise SCL and SDA? */ + set_data(chan, 1); + set_clock(chan, 1); + udelay(20); + + return chan; + +out_free: + kfree(chan); + return NULL; +} + +/** + * intel_i2c_destroy - unregister and free i2c bus resources + * @output: channel to free + * + * Unregister the adapter from the i2c layer, then free the structure. + */ +void intel_i2c_destroy(struct intel_i2c_chan *chan) +{ + if (!chan) + return; + + i2c_del_adapter(&chan->adapter); + kfree(chan); +} --- /dev/null +++ b/drivers/staging/psb/intel_lvds.c @@ -0,0 +1,1023 @@ +/* + * Copyright © 2006-2007 Intel Corporation + * Copyright (c) 2006 Dave Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * Dave Airlie + * Jesse Barnes + */ + +#include +#include +#include +/* MRST defines start */ +uint8_t blc_type; +uint8_t blc_pol; +uint8_t blc_freq; +uint8_t blc_minbrightness; +uint8_t blc_i2caddr; +uint8_t blc_brightnesscmd; +int lvds_backlight; /* restore backlight to this value */ + +u32 CoreClock; +u32 PWMControlRegFreq; +/* MRST defines end */ + +/** + * Sets the backlight level. + * + * \param level backlight level, from 0 to intel_lvds_get_max_backlight(). + */ +static void intel_lvds_set_backlight(struct drm_device *dev, int level) +{ + u32 blc_pwm_ctl; + + blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; + REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | + (level << BACKLIGHT_DUTY_CYCLE_SHIFT))); +} + +/** + * Returns the maximum level of the backlight duty cycle field. + */ +static u32 intel_lvds_get_max_backlight(struct drm_device *dev) +{ + return ((REG_READ(BLC_PWM_CTL) & BACKLIGHT_MODULATION_FREQ_MASK) >> + BACKLIGHT_MODULATION_FREQ_SHIFT) * 2; +} + +/** + * Sets the power state for the panel. + */ +static void intel_lvds_set_power(struct drm_device *dev, + struct intel_output *output, bool on) +{ + u32 pp_status; + + if (on) { + REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | + POWER_TARGET_ON); + do { + pp_status = REG_READ(PP_STATUS); + } while ((pp_status & PP_ON) == 0); + + intel_lvds_set_backlight(dev, + output-> + mode_dev->backlight_duty_cycle); + } else { + intel_lvds_set_backlight(dev, 0); + + REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & + ~POWER_TARGET_ON); + do { + pp_status = REG_READ(PP_STATUS); + } while (pp_status & PP_ON); + } +} + +static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) +{ + struct drm_device *dev = encoder->dev; + struct intel_output *output = enc_to_intel_output(encoder); + + if (mode == DRM_MODE_DPMS_ON) + intel_lvds_set_power(dev, output, true); + else + intel_lvds_set_power(dev, output, false); + + /* XXX: We never power down the LVDS pairs. */ +} + +static void intel_lvds_save(struct drm_connector *connector) +{ +#if 0 /* JB: Disable for drop */ + struct drm_device *dev = connector->dev; + + dev_priv->savePP_ON = REG_READ(PP_ON_DELAYS); + dev_priv->savePP_OFF = REG_READ(PP_OFF_DELAYS); + dev_priv->savePP_CONTROL = REG_READ(PP_CONTROL); + dev_priv->savePP_DIVISOR = REG_READ(PP_DIVISOR); + dev_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); + dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL & + BACKLIGHT_DUTY_CYCLE_MASK); + + /* + * If the light is off at server startup, just make it full brightness + */ + if (dev_priv->backlight_duty_cycle == 0) + dev_priv->backlight_duty_cycle = + intel_lvds_get_max_backlight(dev); +#endif +} + +static void intel_lvds_restore(struct drm_connector *connector) +{ +#if 0 /* JB: Disable for drop */ + struct drm_device *dev = connector->dev; + + REG_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); + REG_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON); + REG_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF); + REG_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); + REG_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); + if (dev_priv->savePP_CONTROL & POWER_TARGET_ON) + intel_lvds_set_power(dev, true); + else + intel_lvds_set_power(dev, false); +#endif +} + +static int intel_lvds_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct intel_output *intel_output = to_intel_output(connector); + struct drm_display_mode *fixed_mode = + intel_output->mode_dev->panel_fixed_mode; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter intel_lvds_mode_valid \n"); +#endif /* PRINT_JLIU7 */ + + if (fixed_mode) { + if (mode->hdisplay > fixed_mode->hdisplay) + return MODE_PANEL; + if (mode->vdisplay > fixed_mode->vdisplay) + return MODE_PANEL; + } + return MODE_OK; +} + +static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct intel_mode_device *mode_dev = + enc_to_intel_output(encoder)->mode_dev; + struct drm_device *dev = encoder->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + struct drm_encoder *tmp_encoder; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter intel_lvds_mode_fixup \n"); +#endif /* PRINT_JLIU7 */ + + /* Should never happen!! */ + if (IS_MRST(dev) && intel_crtc->pipe != 0) { + printk(KERN_ERR + "Can't support LVDS/MIPI on pipe B on MRST\n"); + return false; + } else if (!IS_MRST(dev) && !IS_I965G(dev) + && intel_crtc->pipe == 0) { + printk(KERN_ERR "Can't support LVDS on pipe A\n"); + return false; + } + /* Should never happen!! */ + list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, + head) { + if (tmp_encoder != encoder + && tmp_encoder->crtc == encoder->crtc) { + printk(KERN_ERR "Can't enable LVDS and another " + "encoder on the same pipe\n"); + return false; + } + } + + /* + * If we have timings from the BIOS for the panel, put them in + * to the adjusted mode. The CRTC will be set up for this mode, + * with the panel scaling set up to source from the H/VDisplay + * of the original mode. + */ + if (mode_dev->panel_fixed_mode != NULL) { + adjusted_mode->hdisplay = + mode_dev->panel_fixed_mode->hdisplay; + adjusted_mode->hsync_start = + mode_dev->panel_fixed_mode->hsync_start; + adjusted_mode->hsync_end = + mode_dev->panel_fixed_mode->hsync_end; + adjusted_mode->htotal = mode_dev->panel_fixed_mode->htotal; + adjusted_mode->vdisplay = + mode_dev->panel_fixed_mode->vdisplay; + adjusted_mode->vsync_start = + mode_dev->panel_fixed_mode->vsync_start; + adjusted_mode->vsync_end = + mode_dev->panel_fixed_mode->vsync_end; + adjusted_mode->vtotal = mode_dev->panel_fixed_mode->vtotal; + adjusted_mode->clock = mode_dev->panel_fixed_mode->clock; + drm_mode_set_crtcinfo(adjusted_mode, + CRTC_INTERLACE_HALVE_V); + } + + /* + * XXX: It would be nice to support lower refresh rates on the + * panels to reduce power consumption, and perhaps match the + * user's requested refresh rate. + */ + + return true; +} + +static void intel_lvds_prepare(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct intel_output *output = enc_to_intel_output(encoder); + struct intel_mode_device *mode_dev = output->mode_dev; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter intel_lvds_prepare \n"); +#endif /* PRINT_JLIU7 */ + + mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); + mode_dev->backlight_duty_cycle = (mode_dev->saveBLC_PWM_CTL & + BACKLIGHT_DUTY_CYCLE_MASK); + + intel_lvds_set_power(dev, output, false); +} + +static void intel_lvds_commit(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct intel_output *output = enc_to_intel_output(encoder); + struct intel_mode_device *mode_dev = output->mode_dev; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter intel_lvds_commit \n"); +#endif /* PRINT_JLIU7 */ + + if (mode_dev->backlight_duty_cycle == 0) + mode_dev->backlight_duty_cycle = + intel_lvds_get_max_backlight(dev); + + intel_lvds_set_power(dev, output, true); +} + +static void intel_lvds_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct intel_mode_device *mode_dev = + enc_to_intel_output(encoder)->mode_dev; + struct drm_device *dev = encoder->dev; + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); + u32 pfit_control; + + /* + * The LVDS pin pair will already have been turned on in the + * intel_crtc_mode_set since it has a large impact on the DPLL + * settings. + */ + + /* + * Enable automatic panel scaling so that non-native modes fill the + * screen. Should be enabled before the pipe is enabled, according to + * register description and PRM. + */ + if (mode->hdisplay != adjusted_mode->hdisplay || + mode->vdisplay != adjusted_mode->vdisplay) + pfit_control = (PFIT_ENABLE | VERT_AUTO_SCALE | + HORIZ_AUTO_SCALE | VERT_INTERP_BILINEAR | + HORIZ_INTERP_BILINEAR); + else + pfit_control = 0; + + if (!IS_I965G(dev)) { + if (mode_dev->panel_wants_dither) + pfit_control |= PANEL_8TO6_DITHER_ENABLE; + } else + pfit_control |= intel_crtc->pipe << PFIT_PIPE_SHIFT; + + REG_WRITE(PFIT_CONTROL, pfit_control); +} + +/** + * Detect the LVDS connection. + * + * This always returns CONNECTOR_STATUS_CONNECTED. + * This connector should only have + * been set up if the LVDS was actually connected anyway. + */ +static enum drm_connector_status intel_lvds_detect(struct drm_connector + *connector) +{ + return connector_status_connected; +} + +/** + * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. + */ +static int intel_lvds_get_modes(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct intel_output *intel_output = to_intel_output(connector); + struct intel_mode_device *mode_dev = intel_output->mode_dev; + int ret = 0; + + if (!IS_MRST(dev)) + ret = intel_ddc_get_modes(intel_output); + + if (ret) + return ret; + + /* Didn't get an EDID, so + * Set wide sync ranges so we get all modes + * handed to valid_mode for checking + */ + connector->display_info.min_vfreq = 0; + connector->display_info.max_vfreq = 200; + connector->display_info.min_hfreq = 0; + connector->display_info.max_hfreq = 200; + + if (mode_dev->panel_fixed_mode != NULL) { + struct drm_display_mode *mode = + drm_mode_duplicate(dev, mode_dev->panel_fixed_mode); + drm_mode_probed_add(connector, mode); + return 1; + } + + return 0; +} + +/** + * intel_lvds_destroy - unregister and free LVDS structures + * @connector: connector to free + * + * Unregister the DDC bus for this connector then free the driver private + * structure. + */ +static void intel_lvds_destroy(struct drm_connector *connector) +{ + struct intel_output *intel_output = to_intel_output(connector); + + if (intel_output->ddc_bus) + intel_i2c_destroy(intel_output->ddc_bus); + drm_sysfs_connector_remove(connector); + drm_connector_cleanup(connector); + kfree(connector); +} + +static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { + .dpms = intel_lvds_dpms, + .mode_fixup = intel_lvds_mode_fixup, + .prepare = intel_lvds_prepare, + .mode_set = intel_lvds_mode_set, + .commit = intel_lvds_commit, +}; + +static const struct drm_connector_helper_funcs + intel_lvds_connector_helper_funcs = { + .get_modes = intel_lvds_get_modes, + .mode_valid = intel_lvds_mode_valid, + .best_encoder = intel_best_encoder, +}; + +static const struct drm_connector_funcs intel_lvds_connector_funcs = { + .save = intel_lvds_save, + .restore = intel_lvds_restore, + .detect = intel_lvds_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = intel_lvds_destroy, +}; + + +static void intel_lvds_enc_destroy(struct drm_encoder *encoder) +{ + drm_encoder_cleanup(encoder); +} + +static const struct drm_encoder_funcs intel_lvds_enc_funcs = { + .destroy = intel_lvds_enc_destroy, +}; + + + +/** + * intel_lvds_init - setup LVDS connectors on this device + * @dev: drm device + * + * Create the connector, register the LVDS DDC bus, and try to figure out what + * modes we can display on the LVDS panel (if present). + */ +void intel_lvds_init(struct drm_device *dev, + struct intel_mode_device *mode_dev) +{ + struct intel_output *intel_output; + struct drm_connector *connector; + struct drm_encoder *encoder; + struct drm_display_mode *scan; /* *modes, *bios_mode; */ + struct drm_crtc *crtc; + u32 lvds; + int pipe; + + intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); + if (!intel_output) + return; + + intel_output->mode_dev = mode_dev; + connector = &intel_output->base; + encoder = &intel_output->enc; + drm_connector_init(dev, &intel_output->base, + &intel_lvds_connector_funcs, + DRM_MODE_CONNECTOR_LVDS); + + drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs, + DRM_MODE_ENCODER_LVDS); + + drm_mode_connector_attach_encoder(&intel_output->base, + &intel_output->enc); + intel_output->type = INTEL_OUTPUT_LVDS; + + drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); + drm_connector_helper_add(connector, + &intel_lvds_connector_helper_funcs); + connector->display_info.subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = false; + connector->doublescan_allowed = false; + + + /* + * LVDS discovery: + * 1) check for EDID on DDC + * 2) check for VBT data + * 3) check to see if LVDS is already on + * if none of the above, no panel + * 4) make sure lid is open + * if closed, act like it's not there for now + */ + + /* Set up the DDC bus. */ + intel_output->ddc_bus = intel_i2c_create(dev, GPIOC, "LVDSDDC_C"); + if (!intel_output->ddc_bus) { + dev_printk(KERN_ERR, &dev->pdev->dev, + "DDC bus registration " "failed.\n"); + goto failed_ddc; + } + + /* + * Attempt to get the fixed panel mode from DDC. Assume that the + * preferred mode is the right one. + */ + intel_ddc_get_modes(intel_output); + list_for_each_entry(scan, &connector->probed_modes, head) { + if (scan->type & DRM_MODE_TYPE_PREFERRED) { + mode_dev->panel_fixed_mode = + drm_mode_duplicate(dev, scan); + goto out; /* FIXME: check for quirks */ + } + } + + /* Failed to get EDID, what about VBT? */ + if (mode_dev->vbt_mode) + mode_dev->panel_fixed_mode = + drm_mode_duplicate(dev, mode_dev->vbt_mode); + + /* + * If we didn't get EDID, try checking if the panel is already turned + * on. If so, assume that whatever is currently programmed is the + * correct mode. + */ + lvds = REG_READ(LVDS); + pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; + crtc = intel_get_crtc_from_pipe(dev, pipe); + + if (crtc && (lvds & LVDS_PORT_EN)) { + mode_dev->panel_fixed_mode = + intel_crtc_mode_get(dev, crtc); + if (mode_dev->panel_fixed_mode) { + mode_dev->panel_fixed_mode->type |= + DRM_MODE_TYPE_PREFERRED; + goto out; /* FIXME: check for quirks */ + } + } + + /* If we still don't have a mode after all that, give up. */ + if (!mode_dev->panel_fixed_mode) { + DRM_DEBUG + ("Found no modes on the lvds, ignoring the LVDS\n"); + goto failed_find; + } + + /* FIXME: detect aopen & mac mini type stuff automatically? */ + /* + * Blacklist machines with BIOSes that list an LVDS panel without + * actually having one. + */ + if (IS_I945GM(dev)) { + /* aopen mini pc */ + if (dev->pdev->subsystem_vendor == 0xa0a0) { + DRM_DEBUG + ("Suspected AOpen Mini PC, ignoring the LVDS\n"); + goto failed_find; + } + + if ((dev->pdev->subsystem_vendor == 0x8086) && + (dev->pdev->subsystem_device == 0x7270)) { + /* It's a Mac Mini or Macbook Pro. + * + * Apple hardware is out to get us. The macbook pro + * has a real LVDS panel, but the mac mini does not, + * and they have the same device IDs. We'll + * distinguish by panel size, on the assumption + * that Apple isn't about to make any machines with an + * 800x600 display. + */ + + if (mode_dev->panel_fixed_mode != NULL && + mode_dev->panel_fixed_mode->hdisplay == 800 && + mode_dev->panel_fixed_mode->vdisplay == 600) { + DRM_DEBUG + ("Suspected Mac Mini, ignoring the LVDS\n"); + goto failed_find; + } + } + } + +out: + drm_sysfs_connector_add(connector); + +#if PRINT_JLIU7 + DRM_INFO("PRINT_JLIU7 hdisplay = %d\n", + mode_dev->panel_fixed_mode->hdisplay); + DRM_INFO("PRINT_JLIU7 vdisplay = %d\n", + mode_dev->panel_fixed_mode->vdisplay); + DRM_INFO("PRINT_JLIU7 hsync_start = %d\n", + mode_dev->panel_fixed_mode->hsync_start); + DRM_INFO("PRINT_JLIU7 hsync_end = %d\n", + mode_dev->panel_fixed_mode->hsync_end); + DRM_INFO("PRINT_JLIU7 htotal = %d\n", + mode_dev->panel_fixed_mode->htotal); + DRM_INFO("PRINT_JLIU7 vsync_start = %d\n", + mode_dev->panel_fixed_mode->vsync_start); + DRM_INFO("PRINT_JLIU7 vsync_end = %d\n", + mode_dev->panel_fixed_mode->vsync_end); + DRM_INFO("PRINT_JLIU7 vtotal = %d\n", + mode_dev->panel_fixed_mode->vtotal); + DRM_INFO("PRINT_JLIU7 clock = %d\n", + mode_dev->panel_fixed_mode->clock); +#endif /* PRINT_JLIU7 */ + return; + +failed_find: + if (intel_output->ddc_bus) + intel_i2c_destroy(intel_output->ddc_bus); +failed_ddc: + drm_encoder_cleanup(encoder); + drm_connector_cleanup(connector); + kfree(connector); +} + +/* MRST platform start */ + +/* + * FIXME need to move to register define head file + */ +#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16) +#define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16) + +/* The max/min PWM frequency in BPCR[31:17] - */ +/* The smallest number is 1 (not 0) that can fit in the + * 15-bit field of the and then*/ +/* shifts to the left by one bit to get the actual 16-bit + * value that the 15-bits correspond to.*/ +#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF + +#define BRIGHTNESS_MAX_LEVEL 100 +#define BLC_PWM_PRECISION_FACTOR 10 /* 10000000 */ +#define BLC_PWM_FREQ_CALC_CONSTANT 32 +#define MHz 1000000 +#define BLC_POLARITY_NORMAL 0 +#define BLC_POLARITY_INVERSE 1 + +/** + * Calculate PWM control register value. + */ +static bool mrstLVDSCalculatePWMCtrlRegFreq(struct drm_device *dev) +{ + unsigned long value = 0; + if (blc_freq == 0) { + /* DRM_ERROR(KERN_ERR "mrstLVDSCalculatePWMCtrlRegFreq: + * Frequency Requested is 0.\n"); */ + return false; + } + + value = (CoreClock * MHz); + value = (value / BLC_PWM_FREQ_CALC_CONSTANT); + value = (value * BLC_PWM_PRECISION_FACTOR); + value = (value / blc_freq); + value = (value / BLC_PWM_PRECISION_FACTOR); + + if (value > (unsigned long) MRST_BLC_MAX_PWM_REG_FREQ) { + return 0; + } else { + PWMControlRegFreq = (u32) value; + return 1; + } +} + +/** + * Returns the maximum level of the backlight duty cycle field. + */ +static u32 mrst_lvds_get_PWM_ctrl_freq(struct drm_device *dev) +{ + u32 max_pwm_blc = 0; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_lvds_get_PWM_ctrl_freq \n"); +#endif /* PRINT_JLIU7 */ + +/*FIXME JLIU7 get the PWM frequency from configuration */ + + max_pwm_blc = + (REG_READ(BLC_PWM_CTL) & MRST_BACKLIGHT_MODULATION_FREQ_MASK) + >> MRST_BACKLIGHT_MODULATION_FREQ_SHIFT; + + + if (!max_pwm_blc) { + if (mrstLVDSCalculatePWMCtrlRegFreq(dev)) + max_pwm_blc = PWMControlRegFreq; + } + + return max_pwm_blc; +} + +/** + * Sets the backlight level. + * + * \param level backlight level, from 0 to intel_lvds_get_max_backlight(). + */ +static void mrst_lvds_set_backlight(struct drm_device *dev, int level) +{ + u32 blc_pwm_ctl; + u32 max_pwm_blc; +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_lvds_set_backlight \n"); +#endif /* PRINT_JLIU7 */ + +#if 1 /* FIXME JLIU7 */ + return; +#endif /* FIXME JLIU7 */ + + /* Provent LVDS going to total black */ + if (level < 20) + level = 20; + + max_pwm_blc = mrst_lvds_get_PWM_ctrl_freq(dev); + + if (max_pwm_blc == 0) + return; + + blc_pwm_ctl = level * max_pwm_blc / BRIGHTNESS_MAX_LEVEL; + + if (blc_pol == BLC_POLARITY_INVERSE) + blc_pwm_ctl = max_pwm_blc - blc_pwm_ctl; + + REG_WRITE(BLC_PWM_CTL, + (max_pwm_blc << MRST_BACKLIGHT_MODULATION_FREQ_SHIFT) | + blc_pwm_ctl); +} + +/** + * Sets the power state for the panel. + */ +static void mrst_lvds_set_power(struct drm_device *dev, + struct intel_output *output, bool on) +{ + u32 pp_status; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_lvds_set_power \n"); +#endif /* PRINT_JLIU7 */ + + if (on) { + REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | + POWER_TARGET_ON); + do { + pp_status = REG_READ(PP_STATUS); + } while ((pp_status & (PP_ON | PP_READY)) == PP_READY); + + mrst_lvds_set_backlight(dev, lvds_backlight); + } else { + mrst_lvds_set_backlight(dev, 0); + + REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & + ~POWER_TARGET_ON); + do { + pp_status = REG_READ(PP_STATUS); + } while (pp_status & PP_ON); + } +} + +static void mrst_lvds_dpms(struct drm_encoder *encoder, int mode) +{ + struct drm_device *dev = encoder->dev; + struct intel_output *output = enc_to_intel_output(encoder); + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_lvds_dpms \n"); +#endif /* PRINT_JLIU7 */ + + if (mode == DRM_MODE_DPMS_ON) + mrst_lvds_set_power(dev, output, true); + else + mrst_lvds_set_power(dev, output, false); + + /* XXX: We never power down the LVDS pairs. */ +} + +static void mrst_lvds_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct intel_mode_device *mode_dev = + enc_to_intel_output(encoder)->mode_dev; + struct drm_device *dev = encoder->dev; + u32 pfit_control; + u32 lvds_port; + +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_lvds_mode_set \n"); +#endif /* PRINT_JLIU7 */ + + /* + * The LVDS pin pair will already have been turned on in the + * intel_crtc_mode_set since it has a large impact on the DPLL + * settings. + */ + /*FIXME JLIU7 Get panel power delay parameters from config data */ + REG_WRITE(0x61208, 0x25807d0); + REG_WRITE(0x6120c, 0x1f407d0); + REG_WRITE(0x61210, 0x270f04); + + lvds_port = (REG_READ(LVDS) & (~LVDS_PIPEB_SELECT)) | LVDS_PORT_EN; + + if (mode_dev->panel_wants_dither) + lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE; + + REG_WRITE(LVDS, lvds_port); + + /* + * Enable automatic panel scaling so that non-native modes fill the + * screen. Should be enabled before the pipe is enabled, according to + * register description and PRM. + */ + if (mode->hdisplay != adjusted_mode->hdisplay || + mode->vdisplay != adjusted_mode->vdisplay) + pfit_control = PFIT_ENABLE; + else + pfit_control = 0; + + REG_WRITE(PFIT_CONTROL, pfit_control); +} + + +static const struct drm_encoder_helper_funcs mrst_lvds_helper_funcs = { + .dpms = mrst_lvds_dpms, + .mode_fixup = intel_lvds_mode_fixup, + .prepare = intel_lvds_prepare, + .mode_set = mrst_lvds_mode_set, + .commit = intel_lvds_commit, +}; + +/** Returns the panel fixed mode from configuration. */ +/** FIXME JLIU7 need to revist it. */ +struct drm_display_mode *mrst_lvds_get_configuration_mode(struct drm_device + *dev) +{ + struct drm_display_mode *mode; + + mode = kzalloc(sizeof(*mode), GFP_KERNEL); + if (!mode) + return NULL; + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for TPO LTPS LPJ040K001A */ + mode->hdisplay = 800; + mode->vdisplay = 480; + mode->hsync_start = 836; + mode->hsync_end = 846; + mode->htotal = 1056; + mode->vsync_start = 489; + mode->vsync_end = 491; + mode->vtotal = 525; + mode->clock = 33264; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for LVDS 800x480 */ + mode->hdisplay = 800; + mode->vdisplay = 480; + mode->hsync_start = 801; + mode->hsync_end = 802; + mode->htotal = 1024; + mode->vsync_start = 481; + mode->vsync_end = 482; + mode->vtotal = 525; + mode->clock = 30994; +#endif /*FIXME jliu7 remove it later */ + +#if 1 /*FIXME jliu7 remove it later, jliu7 modify it according to the spec */ + /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */ + mode->hdisplay = 1024; + mode->vdisplay = 600; + mode->hsync_start = 1072; + mode->hsync_end = 1104; + mode->htotal = 1184; + mode->vsync_start = 603; + mode->vsync_end = 604; + mode->vtotal = 608; + mode->clock = 53990; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it, it is copied from SBIOS */ + /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */ + mode->hdisplay = 1024; + mode->vdisplay = 600; + mode->hsync_start = 1104; + mode->hsync_end = 1136; + mode->htotal = 1184; + mode->vsync_start = 603; + mode->vsync_end = 604; + mode->vtotal = 608; + mode->clock = 53990; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for Sharp wsvga LVDS 1024x600 */ + mode->hdisplay = 1024; + mode->vdisplay = 600; + mode->hsync_start = 1124; + mode->hsync_end = 1204; + mode->htotal = 1312; + mode->vsync_start = 607; + mode->vsync_end = 610; + mode->vtotal = 621; + mode->clock = 48885; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for LVDS 1024x768 */ + mode->hdisplay = 1024; + mode->vdisplay = 768; + mode->hsync_start = 1048; + mode->hsync_end = 1184; + mode->htotal = 1344; + mode->vsync_start = 771; + mode->vsync_end = 777; + mode->vtotal = 806; + mode->clock = 65000; +#endif /*FIXME jliu7 remove it later */ + +#if 0 /*FIXME jliu7 remove it later */ + /* hard coded fixed mode for LVDS 1366x768 */ + mode->hdisplay = 1366; + mode->vdisplay = 768; + mode->hsync_start = 1430; + mode->hsync_end = 1558; + mode->htotal = 1664; + mode->vsync_start = 769; + mode->vsync_end = 770; + mode->vtotal = 776; + mode->clock = 77500; +#endif /*FIXME jliu7 remove it later */ + + drm_mode_set_name(mode); + drm_mode_set_crtcinfo(mode, 0); + + return mode; +} + +/** + * mrst_lvds_init - setup LVDS connectors on this device + * @dev: drm device + * + * Create the connector, register the LVDS DDC bus, and try to figure out what + * modes we can display on the LVDS panel (if present). + */ +void mrst_lvds_init(struct drm_device *dev, + struct intel_mode_device *mode_dev) +{ + struct intel_output *intel_output; + struct drm_connector *connector; + struct drm_encoder *encoder; +#if MRST_I2C + struct drm_display_mode *scan; /* *modes, *bios_mode; */ +#endif +#if PRINT_JLIU7 + DRM_INFO("JLIU7 enter mrst_lvds_init \n"); +#endif /* PRINT_JLIU7 */ + + intel_output = kzalloc(sizeof(struct intel_output), GFP_KERNEL); + if (!intel_output) + return; + + intel_output->mode_dev = mode_dev; + connector = &intel_output->base; + encoder = &intel_output->enc; + drm_connector_init(dev, &intel_output->base, + &intel_lvds_connector_funcs, + DRM_MODE_CONNECTOR_LVDS); + + drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs, + DRM_MODE_ENCODER_LVDS); + + drm_mode_connector_attach_encoder(&intel_output->base, + &intel_output->enc); + intel_output->type = INTEL_OUTPUT_LVDS; + + drm_encoder_helper_add(encoder, &mrst_lvds_helper_funcs); + drm_connector_helper_add(connector, + &intel_lvds_connector_helper_funcs); + connector->display_info.subpixel_order = SubPixelHorizontalRGB; + connector->interlace_allowed = false; + connector->doublescan_allowed = false; + + lvds_backlight = BRIGHTNESS_MAX_LEVEL; + + /* + * LVDS discovery: + * 1) check for EDID on DDC + * 2) check for VBT data + * 3) check to see if LVDS is already on + * if none of the above, no panel + * 4) make sure lid is open + * if closed, act like it's not there for now + */ + +#if MRST_I2C + /* Set up the DDC bus. */ + intel_output->ddc_bus = intel_i2c_create(dev, GPIOC, "LVDSDDC_C"); + if (!intel_output->ddc_bus) { + dev_printk(KERN_ERR, &dev->pdev->dev, + "DDC bus registration " "failed.\n"); + goto failed_ddc; + } + + /* + * Attempt to get the fixed panel mode from DDC. Assume that the + * preferred mode is the right one. + */ + intel_ddc_get_modes(intel_output); + list_for_each_entry(scan, &connector->probed_modes, head) { + if (scan->type & DRM_MODE_TYPE_PREFERRED) { + mode_dev->panel_fixed_mode = + drm_mode_duplicate(dev, scan); + goto out; /* FIXME: check for quirks */ + } + } +#endif /* MRST_I2C */ + + /* + * If we didn't get EDID, try geting panel timing + * from configuration data + */ + mode_dev->panel_fixed_mode = mrst_lvds_get_configuration_mode(dev); + + if (mode_dev->panel_fixed_mode) { + mode_dev->panel_fixed_mode->type |= + DRM_MODE_TYPE_PREFERRED; + goto out; /* FIXME: check for quirks */ + } + + /* If we still don't have a mode after all that, give up. */ + if (!mode_dev->panel_fixed_mode) { + DRM_DEBUG + ("Found no modes on the lvds, ignoring the LVDS\n"); + goto failed_find; + } + +out: + drm_sysfs_connector_add(connector); + return; + +failed_find: + DRM_DEBUG("No LVDS modes found, disabling.\n"); + if (intel_output->ddc_bus) + intel_i2c_destroy(intel_output->ddc_bus); +#if MRST_I2C +failed_ddc: +#endif + drm_encoder_cleanup(encoder); + drm_connector_cleanup(connector); + kfree(connector); +} + +/* MRST platform end */ --- /dev/null +++ b/drivers/staging/psb/intel_modes.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2007 Intel Corporation + * Jesse Barnes + */ + +#include +#include +#include +#include "intel_drv.h" + +/** + * intel_ddc_probe + * + */ +bool intel_ddc_probe(struct intel_output *intel_output) +{ + u8 out_buf[] = { 0x0, 0x0 }; + u8 buf[2]; + int ret; + struct i2c_msg msgs[] = { + { + .addr = 0x50, + .flags = 0, + .len = 1, + .buf = out_buf, + }, + { + .addr = 0x50, + .flags = I2C_M_RD, + .len = 1, + .buf = buf, + } + }; + + ret = i2c_transfer(&intel_output->ddc_bus->adapter, msgs, 2); + if (ret == 2) + return true; + + return false; +} + +/** + * intel_ddc_get_modes - get modelist from monitor + * @connector: DRM connector device to use + * + * Fetch the EDID information from @connector using the DDC bus. + */ +int intel_ddc_get_modes(struct intel_output *intel_output) +{ + struct edid *edid; + int ret = 0; + + edid = + drm_get_edid(&intel_output->base, + &intel_output->ddc_bus->adapter); + if (edid) { + drm_mode_connector_update_edid_property(&intel_output-> + base, edid); + ret = drm_add_edid_modes(&intel_output->base, edid); + kfree(edid); + } + return ret; +} --- /dev/null +++ b/drivers/staging/psb/intel_reg.h @@ -0,0 +1,972 @@ +#define BLC_PWM_CTL 0x61254 +#define BLC_PWM_CTL2 0x61250 +#define BACKLIGHT_MODULATION_FREQ_SHIFT (17) +/** + * This is the most significant 15 bits of the number of backlight cycles in a + * complete cycle of the modulated backlight control. + * + * The actual value is this field multiplied by two. + */ +#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) +#define BLM_LEGACY_MODE (1 << 16) +/** + * This is the number of cycles out of the backlight modulation cycle for which + * the backlight is on. + * + * This field must be no greater than the number of cycles in the complete + * backlight modulation cycle. + */ +#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) +#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) + +#define I915_GCFGC 0xf0 +#define I915_LOW_FREQUENCY_ENABLE (1 << 7) +#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4) +#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define I915_DISPLAY_CLOCK_MASK (7 << 4) + +#define I855_HPLLCC 0xc0 +#define I855_CLOCK_CONTROL_MASK (3 << 0) +#define I855_CLOCK_133_200 (0 << 0) +#define I855_CLOCK_100_200 (1 << 0) +#define I855_CLOCK_100_133 (2 << 0) +#define I855_CLOCK_166_250 (3 << 0) + +/* I830 CRTC registers */ +#define HTOTAL_A 0x60000 +#define HBLANK_A 0x60004 +#define HSYNC_A 0x60008 +#define VTOTAL_A 0x6000c +#define VBLANK_A 0x60010 +#define VSYNC_A 0x60014 +#define PIPEASRC 0x6001c +#define BCLRPAT_A 0x60020 +#define VSYNCSHIFT_A 0x60028 + +#define HTOTAL_B 0x61000 +#define HBLANK_B 0x61004 +#define HSYNC_B 0x61008 +#define VTOTAL_B 0x6100c +#define VBLANK_B 0x61010 +#define VSYNC_B 0x61014 +#define PIPEBSRC 0x6101c +#define BCLRPAT_B 0x61020 +#define VSYNCSHIFT_B 0x61028 + +#define PP_STATUS 0x61200 +# define PP_ON (1 << 31) +/** + * Indicates that all dependencies of the panel are on: + * + * - PLL enabled + * - pipe enabled + * - LVDS/DVOB/DVOC on + */ +# define PP_READY (1 << 30) +# define PP_SEQUENCE_NONE (0 << 28) +# define PP_SEQUENCE_ON (1 << 28) +# define PP_SEQUENCE_OFF (2 << 28) +# define PP_SEQUENCE_MASK 0x30000000 +#define PP_CONTROL 0x61204 +# define POWER_TARGET_ON (1 << 0) + +#define LVDSPP_ON 0x61208 +#define LVDSPP_OFF 0x6120c +#define PP_CYCLE 0x61210 + +#define PFIT_CONTROL 0x61230 +# define PFIT_ENABLE (1 << 31) +# define PFIT_PIPE_MASK (3 << 29) +# define PFIT_PIPE_SHIFT 29 +# define VERT_INTERP_DISABLE (0 << 10) +# define VERT_INTERP_BILINEAR (1 << 10) +# define VERT_INTERP_MASK (3 << 10) +# define VERT_AUTO_SCALE (1 << 9) +# define HORIZ_INTERP_DISABLE (0 << 6) +# define HORIZ_INTERP_BILINEAR (1 << 6) +# define HORIZ_INTERP_MASK (3 << 6) +# define HORIZ_AUTO_SCALE (1 << 5) +# define PANEL_8TO6_DITHER_ENABLE (1 << 3) + +#define PFIT_PGM_RATIOS 0x61234 +# define PFIT_VERT_SCALE_MASK 0xfff00000 +# define PFIT_HORIZ_SCALE_MASK 0x0000fff0 + +#define PFIT_AUTO_RATIOS 0x61238 + + +#define DPLL_A 0x06014 +#define DPLL_B 0x06018 +# define DPLL_VCO_ENABLE (1 << 31) +# define DPLL_DVO_HIGH_SPEED (1 << 30) +# define DPLL_SYNCLOCK_ENABLE (1 << 29) +# define DPLL_VGA_MODE_DIS (1 << 28) +# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ +# define DPLLB_MODE_LVDS (2 << 26) /* i915 */ +# define DPLL_MODE_MASK (3 << 26) +# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ +# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ +# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ +# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ +# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ +# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ +/** + * The i830 generation, in DAC/serial mode, defines p1 as two plus this + * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. + */ +# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 +/** + * The i830 generation, in LVDS mode, defines P1 as the bit number set within + * this field (only one bit may be set). + */ +# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 +# define DPLL_FPA01_P1_POST_DIV_SHIFT 16 +# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required + * in DVO non-gang */ +# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ +# define PLL_REF_INPUT_DREFCLK (0 << 13) +# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ +# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO + * TVCLKIN */ +# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) +# define PLL_REF_INPUT_MASK (3 << 13) +# define PLL_LOAD_PULSE_PHASE_SHIFT 9 +/* + * Parallel to Serial Load Pulse phase selection. + * Selects the phase for the 10X DPLL clock for the PCIe + * digital display port. The range is 4 to 13; 10 or more + * is just a flip delay. The default is 6 + */ +# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) +# define DISPLAY_RATE_SELECT_FPA1 (1 << 8) + +/** + * SDVO multiplier for 945G/GM. Not used on 965. + * + * \sa DPLL_MD_UDI_MULTIPLIER_MASK + */ +# define SDVO_MULTIPLIER_MASK 0x000000ff +# define SDVO_MULTIPLIER_SHIFT_HIRES 4 +# define SDVO_MULTIPLIER_SHIFT_VGA 0 + +/** @defgroup DPLL_MD + * @{ + */ +/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ +#define DPLL_A_MD 0x0601c +/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ +#define DPLL_B_MD 0x06020 +/** + * UDI pixel divider, controlling how many pixels are stuffed into a packet. + * + * Value is pixels minus 1. Must be set to 1 pixel for SDVO. + */ +# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 +# define DPLL_MD_UDI_DIVIDER_SHIFT 24 +/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ +# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 +# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 +/** + * SDVO/UDI pixel multiplier. + * + * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus + * clock rate is 10 times the DPLL clock. At low resolution/refresh rate + * modes, the bus rate would be below the limits, so SDVO allows for stuffing + * dummy bytes in the datastream at an increased clock rate, with both sides of + * the link knowing how many bytes are fill. + * + * So, for a mode with a dotclock of 65Mhz, we would want to double the clock + * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be + * set to 130Mhz, and the SDVO multiplier set to 2x in this register and + * through an SDVO command. + * + * This register field has values of multiplication factor minus 1, with + * a maximum multiplier of 5 for SDVO. + */ +# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 +# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 +/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. + * This best be set to the default value (3) or the CRT won't work. No, + * I don't entirely understand what this does... + */ +# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f +# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 +/** @} */ + +#define DPLL_TEST 0x606c +# define DPLLB_TEST_SDVO_DIV_1 (0 << 22) +# define DPLLB_TEST_SDVO_DIV_2 (1 << 22) +# define DPLLB_TEST_SDVO_DIV_4 (2 << 22) +# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) +# define DPLLB_TEST_N_BYPASS (1 << 19) +# define DPLLB_TEST_M_BYPASS (1 << 18) +# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) +# define DPLLA_TEST_N_BYPASS (1 << 3) +# define DPLLA_TEST_M_BYPASS (1 << 2) +# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) + +#define ADPA 0x61100 +#define ADPA_DAC_ENABLE (1<<31) +#define ADPA_DAC_DISABLE 0 +#define ADPA_PIPE_SELECT_MASK (1<<30) +#define ADPA_PIPE_A_SELECT 0 +#define ADPA_PIPE_B_SELECT (1<<30) +#define ADPA_USE_VGA_HVPOLARITY (1<<15) +#define ADPA_SETS_HVPOLARITY 0 +#define ADPA_VSYNC_CNTL_DISABLE (1<<11) +#define ADPA_VSYNC_CNTL_ENABLE 0 +#define ADPA_HSYNC_CNTL_DISABLE (1<<10) +#define ADPA_HSYNC_CNTL_ENABLE 0 +#define ADPA_VSYNC_ACTIVE_HIGH (1<<4) +#define ADPA_VSYNC_ACTIVE_LOW 0 +#define ADPA_HSYNC_ACTIVE_HIGH (1<<3) +#define ADPA_HSYNC_ACTIVE_LOW 0 + +#define FPA0 0x06040 +#define FPA1 0x06044 +#define FPB0 0x06048 +#define FPB1 0x0604c +# define FP_N_DIV_MASK 0x003f0000 +# define FP_N_DIV_SHIFT 16 +# define FP_M1_DIV_MASK 0x00003f00 +# define FP_M1_DIV_SHIFT 8 +# define FP_M2_DIV_MASK 0x0000003f +# define FP_M2_DIV_SHIFT 0 + + +#define PORT_HOTPLUG_EN 0x61110 +# define SDVOB_HOTPLUG_INT_EN (1 << 26) +# define SDVOC_HOTPLUG_INT_EN (1 << 25) +# define TV_HOTPLUG_INT_EN (1 << 18) +# define CRT_HOTPLUG_INT_EN (1 << 9) +# define CRT_HOTPLUG_FORCE_DETECT (1 << 3) + +#define PORT_HOTPLUG_STAT 0x61114 +# define CRT_HOTPLUG_INT_STATUS (1 << 11) +# define TV_HOTPLUG_INT_STATUS (1 << 10) +# define CRT_HOTPLUG_MONITOR_MASK (3 << 8) +# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) +# define CRT_HOTPLUG_MONITOR_MONO (2 << 8) +# define CRT_HOTPLUG_MONITOR_NONE (0 << 8) +# define SDVOC_HOTPLUG_INT_STATUS (1 << 7) +# define SDVOB_HOTPLUG_INT_STATUS (1 << 6) + +#define SDVOB 0x61140 +#define SDVOC 0x61160 +#define SDVO_ENABLE (1 << 31) +#define SDVO_PIPE_B_SELECT (1 << 30) +#define SDVO_STALL_SELECT (1 << 29) +#define SDVO_INTERRUPT_ENABLE (1 << 26) +/** + * 915G/GM SDVO pixel multiplier. + * + * Programmed value is multiplier - 1, up to 5x. + * + * \sa DPLL_MD_UDI_MULTIPLIER_MASK + */ +#define SDVO_PORT_MULTIPLY_MASK (7 << 23) +#define SDVO_PORT_MULTIPLY_SHIFT 23 +#define SDVO_PHASE_SELECT_MASK (15 << 19) +#define SDVO_PHASE_SELECT_DEFAULT (6 << 19) +#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18) +#define SDVOC_GANG_MODE (1 << 16) +#define SDVO_BORDER_ENABLE (1 << 7) +#define SDVOB_PCIE_CONCURRENCY (1 << 3) +#define SDVO_DETECTED (1 << 2) +/* Bits to be preserved when writing */ +#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14)) +#define SDVOC_PRESERVE_MASK (1 << 17) + +/** @defgroup LVDS + * @{ + */ +/** + * This register controls the LVDS output enable, pipe selection, and data + * format selection. + * + * All of the clock/data pairs are force powered down by power sequencing. + */ +#define LVDS 0x61180 +/** + * Enables the LVDS port. This bit must be set before DPLLs are enabled, as + * the DPLL semantics change when the LVDS is assigned to that pipe. + */ +# define LVDS_PORT_EN (1 << 31) +/** Selects pipe B for LVDS data. Must be set on pre-965. */ +# define LVDS_PIPEB_SELECT (1 << 30) + +/** + * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per + * pixel. + */ +# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8) +# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8) +# define LVDS_A0A2_CLKA_POWER_UP (3 << 8) +/** + * Controls the A3 data pair, which contains the additional LSBs for 24 bit + * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be + * on. + */ +# define LVDS_A3_POWER_MASK (3 << 6) +# define LVDS_A3_POWER_DOWN (0 << 6) +# define LVDS_A3_POWER_UP (3 << 6) +/** + * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP + * is set. + */ +# define LVDS_CLKB_POWER_MASK (3 << 4) +# define LVDS_CLKB_POWER_DOWN (0 << 4) +# define LVDS_CLKB_POWER_UP (3 << 4) + +/** + * Controls the B0-B3 data pairs. This must be set to match the DPLL p2 + * setting for whether we are in dual-channel mode. The B3 pair will + * additionally only be powered up when LVDS_A3_POWER_UP is set. + */ +# define LVDS_B0B3_POWER_MASK (3 << 2) +# define LVDS_B0B3_POWER_DOWN (0 << 2) +# define LVDS_B0B3_POWER_UP (3 << 2) + +#define PIPEACONF 0x70008 +#define PIPEACONF_ENABLE (1<<31) +#define PIPEACONF_DISABLE 0 +#define PIPEACONF_DOUBLE_WIDE (1<<30) +#define I965_PIPECONF_ACTIVE (1<<30) +#define PIPEACONF_SINGLE_WIDE 0 +#define PIPEACONF_PIPE_UNLOCKED 0 +#define PIPEACONF_PIPE_LOCKED (1<<25) +#define PIPEACONF_PALETTE 0 +#define PIPEACONF_GAMMA (1<<24) +#define PIPECONF_FORCE_BORDER (1<<25) +#define PIPECONF_PROGRESSIVE (0 << 21) +#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) + +#define PIPEBCONF 0x71008 +#define PIPEBCONF_ENABLE (1<<31) +#define PIPEBCONF_DISABLE 0 +#define PIPEBCONF_DOUBLE_WIDE (1<<30) +#define PIPEBCONF_DISABLE 0 +#define PIPEBCONF_GAMMA (1<<24) +#define PIPEBCONF_PALETTE 0 + +#define PIPEBGCMAXRED 0x71010 +#define PIPEBGCMAXGREEN 0x71014 +#define PIPEBGCMAXBLUE 0x71018 +#define PIPEBSTAT 0x71024 +#define PIPEBFRAMEHIGH 0x71040 +#define PIPEBFRAMEPIXEL 0x71044 + +#define DSPARB 0x70030 +#define DSPFW1 0x70034 +#define DSPFW2 0x70038 +#define DSPFW3 0x7003c +#define DSPFW4 0x70050 +#define DSPFW5 0x70054 +#define DSPFW6 0x70058 + +#define DSPACNTR 0x70180 +#define DSPBCNTR 0x71180 +#define DISPLAY_PLANE_ENABLE (1<<31) +#define DISPLAY_PLANE_DISABLE 0 +#define DISPPLANE_GAMMA_ENABLE (1<<30) +#define DISPPLANE_GAMMA_DISABLE 0 +#define DISPPLANE_PIXFORMAT_MASK (0xf<<26) +#define DISPPLANE_8BPP (0x2<<26) +#define DISPPLANE_15_16BPP (0x4<<26) +#define DISPPLANE_16BPP (0x5<<26) +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) +#define DISPPLANE_32BPP (0x7<<26) +#define DISPPLANE_STEREO_ENABLE (1<<25) +#define DISPPLANE_STEREO_DISABLE 0 +#define DISPPLANE_SEL_PIPE_MASK (1<<24) +#define DISPPLANE_SEL_PIPE_A 0 +#define DISPPLANE_SEL_PIPE_B (1<<24) +#define DISPPLANE_SRC_KEY_ENABLE (1<<22) +#define DISPPLANE_SRC_KEY_DISABLE 0 +#define DISPPLANE_LINE_DOUBLE (1<<20) +#define DISPPLANE_NO_LINE_DOUBLE 0 +#define DISPPLANE_STEREO_POLARITY_FIRST 0 +#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) +/* plane B only */ +#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) +#define DISPPLANE_ALPHA_TRANS_DISABLE 0 +#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 +#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) + +#define DSPABASE 0x70184 +#define DSPASTRIDE 0x70188 + +#define DSPBBASE 0x71184 +#define DSPBADDR DSPBBASE +#define DSPBSTRIDE 0x71188 + +#define DSPAKEYVAL 0x70194 +#define DSPAKEYMASK 0x70198 + +#define DSPAPOS 0x7018C /* reserved */ +#define DSPASIZE 0x70190 +#define DSPBPOS 0x7118C +#define DSPBSIZE 0x71190 + +#define DSPASURF 0x7019C +#define DSPATILEOFF 0x701A4 + +#define DSPBSURF 0x7119C +#define DSPBTILEOFF 0x711A4 + +#define VGACNTRL 0x71400 +# define VGA_DISP_DISABLE (1 << 31) +# define VGA_2X_MODE (1 << 30) +# define VGA_PIPE_B_SELECT (1 << 29) + +/* + * Some BIOS scratch area registers. The 845 (and 830?) store the amount + * of video memory available to the BIOS in SWF1. + */ + +#define SWF0 0x71410 +#define SWF1 0x71414 +#define SWF2 0x71418 +#define SWF3 0x7141c +#define SWF4 0x71420 +#define SWF5 0x71424 +#define SWF6 0x71428 + +/* + * 855 scratch registers. + */ +#define SWF00 0x70410 +#define SWF01 0x70414 +#define SWF02 0x70418 +#define SWF03 0x7041c +#define SWF04 0x70420 +#define SWF05 0x70424 +#define SWF06 0x70428 + +#define SWF10 SWF0 +#define SWF11 SWF1 +#define SWF12 SWF2 +#define SWF13 SWF3 +#define SWF14 SWF4 +#define SWF15 SWF5 +#define SWF16 SWF6 + +#define SWF30 0x72414 +#define SWF31 0x72418 +#define SWF32 0x7241c + + +/* + * Palette registers + */ +#define PALETTE_A 0x0a000 +#define PALETTE_B 0x0a800 + +#define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC) +#define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG) +#define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) +#define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) +#define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG) + + +/* || dev->pci_device == PCI_DEVICE_ID_INTELPCI_CHIP_E7221_G) */ +#define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG) +#define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG) +#define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG) +#define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG) + +#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ + (dev)->pci_device == 0x2982 || \ + (dev)->pci_device == 0x2992 || \ + (dev)->pci_device == 0x29A2 || \ + (dev)->pci_device == 0x2A02 || \ + (dev)->pci_device == 0x2A12) + +#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) + +#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ + (dev)->pci_device == 0x29B2 || \ + (dev)->pci_device == 0x29D2) + +#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ + IS_I945GM(dev) || IS_I965G(dev) || IS_POULSBO(dev) || \ + IS_MRST(dev)) + +#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ + IS_I945GM(dev) || IS_I965GM(dev) || \ + IS_POULSBO(dev) || IS_MRST(dev)) + +/* Cursor A & B regs */ +#define CURACNTR 0x70080 +#define CURSOR_MODE_DISABLE 0x00 +#define CURSOR_MODE_64_32B_AX 0x07 +#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX) +#define MCURSOR_GAMMA_ENABLE (1 << 26) +#define CURABASE 0x70084 +#define CURAPOS 0x70088 +#define CURSOR_POS_MASK 0x007FF +#define CURSOR_POS_SIGN 0x8000 +#define CURSOR_X_SHIFT 0 +#define CURSOR_Y_SHIFT 16 +#define CURBCNTR 0x700c0 +#define CURBBASE 0x700c4 +#define CURBPOS 0x700c8 + +/* + * MOORESTOWN delta registers + */ +#define MRST_DPLL_A 0x0f014 +#define DPLLA_MODE_LVDS (2 << 26) /* mrst */ +#define MRST_FPA0 0x0f040 +#define MRST_FPA1 0x0f044 + +/* #define LVDS 0x61180 */ +# define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25) +# define MRST_PANEL_24_DOT_1_FORMAT (1 << 24) +# define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6) + +#define MIPI 0x61190 +# define MIPI_PORT_EN (1 << 31) + +/* #define PP_CONTROL 0x61204 */ +# define POWER_DOWN_ON_RESET (1 << 1) + +/* #define PFIT_CONTROL 0x61230 */ +# define PFIT_PIPE_SELECT (3 << 29) +# define PFIT_PIPE_SELECT_SHIFT (29) + +/* #define BLC_PWM_CTL 0x61254 */ +#define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16) +#define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16) + +/* #define PIPEACONF 0x70008 */ +#define PIPEACONF_PIPE_STATE (1<<30) +/* #define DSPACNTR 0x70180 */ +#if 0 /*FIXME JLIU7 need to define the following */ +1000 = 32 - bit RGBX(10 : 10 : 10 : 2) +pixel format.Ignore alpha.1010 = BGRX 10 : 10 : 10 : 2 1100 = 64 - bit RGBX +(16 : 16 : 16 : 16) 16 bit floating point pixel format. +Ignore alpha.1110 = 32 - bit RGBX(8 : 8 : 8 : 8) pixel format. + Ignore + alpha. +#endif /*FIXME JLIU7 need to define the following */ + +#define MRST_DSPABASE 0x7019c + +/* + * MOORESTOWN reserved registers + */ +#if 0 +#define DSPAPOS 0x7018C /* reserved */ +#define DSPASIZE 0x70190 +#endif +/* + * Moorestown registers. + */ +/*=========================================================================== +; General Constants +;--------------------------------------------------------------------------*/ +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +/*=========================================================================== +; MIPI IP registers +;--------------------------------------------------------------------------*/ +#define DEVICE_READY_REG 0xb000 +#define INTR_STAT_REG 0xb004 +#define RX_SOT_ERROR BIT0 +#define RX_SOT_SYNC_ERROR BIT1 +#define RX_ESCAPE_MODE_ENTRY_ERROR BIT3 +#define RX_LP_TX_SYNC_ERROR BIT4 +#define RX_HS_RECEIVE_TIMEOUT_ERROR BIT5 +#define RX_FALSE_CONTROL_ERROR BIT6 +#define RX_ECC_SINGLE_BIT_ERROR BIT7 +#define RX_ECC_MULTI_BIT_ERROR BIT8 +#define RX_CHECKSUM_ERROR BIT9 +#define RX_DSI_DATA_TYPE_NOT_RECOGNIZED BIT10 +#define RX_DSI_VC_ID_INVALID BIT11 +#define TX_FALSE_CONTROL_ERROR BIT12 +#define TX_ECC_SINGLE_BIT_ERROR BIT13 +#define TX_ECC_MULTI_BIT_ERROR BIT14 +#define TX_CHECKSUM_ERROR BIT15 +#define TX_DSI_DATA_TYPE_NOT_RECOGNIZED BIT16 +#define TX_DSI_VC_ID_INVALID BIT17 +#define HIGH_CONTENTION BIT18 +#define LOW_CONTENTION BIT19 +#define DPI_FIFO_UNDER_RUN BIT20 +#define HS_TX_TIMEOUT BIT21 +#define LP_RX_TIMEOUT BIT22 +#define TURN_AROUND_ACK_TIMEOUT BIT23 +#define ACK_WITH_NO_ERROR BIT24 +#define INTR_EN_REG 0xb008 +#define DSI_FUNC_PRG_REG 0xb00c +#define DPI_CHANNEL_NUMBER_POS 0x03 +#define DBI_CHANNEL_NUMBER_POS 0x05 +#define FMT_DPI_POS 0x07 +#define FMT_DBI_POS 0x0A +#define DBI_DATA_WIDTH_POS 0x0D +#define HS_TX_TIMEOUT_REG 0xb010 +#define LP_RX_TIMEOUT_REG 0xb014 +#define TURN_AROUND_TIMEOUT_REG 0xb018 +#define DEVICE_RESET_REG 0xb01C +#define DPI_RESOLUTION_REG 0xb020 +#define RES_V_POS 0x10 +#define DBI_RESOLUTION_REG 0xb024 +#define HORIZ_SYNC_PAD_COUNT_REG 0xb028 +#define HORIZ_BACK_PORCH_COUNT_REG 0xb02C +#define HORIZ_FRONT_PORCH_COUNT_REG 0xb030 +#define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034 +#define VERT_SYNC_PAD_COUNT_REG 0xb038 +#define VERT_BACK_PORCH_COUNT_REG 0xb03c +#define VERT_FRONT_PORCH_COUNT_REG 0xb040 +#define HIGH_LOW_SWITCH_COUNT_REG 0xb044 +#define DPI_CONTROL_REG 0xb048 +#define DPI_SHUT_DOWN BIT0 +#define DPI_TURN_ON BIT1 +#define DPI_COLOR_MODE_ON BIT2 +#define DPI_COLOR_MODE_OFF BIT3 +#define DPI_BACK_LIGHT_ON BIT4 +#define DPI_BACK_LIGHT_OFF BIT5 +#define DPI_LP BIT6 +#define DPI_DATA_REG 0xb04c +#define DPI_BACK_LIGHT_ON_DATA 0x07 +#define DPI_BACK_LIGHT_OFF_DATA 0x17 +#define INIT_COUNT_REG 0xb050 +#define MAX_RET_PAK_REG 0xb054 +#define VIDEO_FMT_REG 0xb058 +#define EOT_DISABLE_REG 0xb05c +#define LP_BYTECLK_REG 0xb060 +#define LP_GEN_DATA_REG 0xb064 +#define HS_GEN_DATA_REG 0xb068 +#define LP_GEN_CTRL_REG 0xb06C +#define HS_GEN_CTRL_REG 0xb070 +#define GEN_FIFO_STAT_REG 0xb074 +#define HS_DATA_FIFO_FULL BIT0 +#define HS_DATA_FIFO_HALF_EMPTY BIT1 +#define HS_DATA_FIFO_EMPTY BIT2 +#define LP_DATA_FIFO_FULL BIT8 +#define LP_DATA_FIFO_HALF_EMPTY BIT9 +#define LP_DATA_FIFO_EMPTY BIT10 +#define HS_CTRL_FIFO_FULL BIT16 +#define HS_CTRL_FIFO_HALF_EMPTY BIT17 +#define HS_CTRL_FIFO_EMPTY BIT18 +#define LP_CTRL_FIFO_FULL BIT24 +#define LP_CTRL_FIFO_HALF_EMPTY BIT25 +#define LP_CTRL_FIFO_EMPTY BIT26 +/*=========================================================================== +; MIPI Adapter registers +;--------------------------------------------------------------------------*/ +#define MIPI_CONTROL_REG 0xb104 +#define MIPI_2X_CLOCK_BITS (BIT0 | BIT1) +#define MIPI_DATA_ADDRESS_REG 0xb108 +#define MIPI_DATA_LENGTH_REG 0xb10C +#define MIPI_COMMAND_ADDRESS_REG 0xb110 +#define MIPI_COMMAND_LENGTH_REG 0xb114 +#define MIPI_READ_DATA_RETURN_REG0 0xb118 +#define MIPI_READ_DATA_RETURN_REG1 0xb11C +#define MIPI_READ_DATA_RETURN_REG2 0xb120 +#define MIPI_READ_DATA_RETURN_REG3 0xb124 +#define MIPI_READ_DATA_RETURN_REG4 0xb128 +#define MIPI_READ_DATA_RETURN_REG5 0xb12C +#define MIPI_READ_DATA_RETURN_REG6 0xb130 +#define MIPI_READ_DATA_RETURN_REG7 0xb134 +#define MIPI_READ_DATA_VALID_REG 0xb138 +/* DBI COMMANDS */ +#define soft_reset 0x01 +/* ************************************************************************* *\ +The display module performs a software reset. +Registers are written with their SW Reset default values. +\* ************************************************************************* */ +#define get_power_mode 0x0a +/* ************************************************************************* *\ +The display module returns the current power mode +\* ************************************************************************* */ +#define get_address_mode 0x0b +/* ************************************************************************* *\ +The display module returns the current status. +\* ************************************************************************* */ +#define get_pixel_format 0x0c +/* ************************************************************************* *\ +This command gets the pixel format for the RGB image data +used by the interface. +\* ************************************************************************* */ +#define get_display_mode 0x0d +/* ************************************************************************* *\ +The display module returns the Display Image Mode status. +\* ************************************************************************* */ +#define get_signal_mode 0x0e +/* ************************************************************************* *\ +The display module returns the Display Signal Mode. +\* ************************************************************************* */ +#define get_diagnostic_result 0x0f +/* ************************************************************************* *\ +The display module returns the self-diagnostic results following +a Sleep Out command. +\* ************************************************************************* */ +#define enter_sleep_mode 0x10 +/* ************************************************************************* *\ +This command causes the display module to enter the Sleep mode. +In this mode, all unnecessary blocks inside the display module are disabled +except interface communication. This is the lowest power mode +the display module supports. +\* ************************************************************************* */ +#define exit_sleep_mode 0x11 +/* ************************************************************************* *\ +This command causes the display module to exit Sleep mode. +All blocks inside the display module are enabled. +\* ************************************************************************* */ +#define enter_partial_mode 0x12 +/* ************************************************************************* *\ +This command causes the display module to enter the Partial Display Mode. +The Partial Display Mode window is described by the set_partial_area command. +\* ************************************************************************* */ +#define enter_normal_mode 0x13 +/* ************************************************************************* *\ +This command causes the display module to enter the Normal mode. +Normal Mode is defined as Partial Display mode and Scroll mode are off +\* ************************************************************************* */ +#define exit_invert_mode 0x20 +/* ************************************************************************* *\ +This command causes the display module to stop inverting the image data on +the display device. The frame memory contents remain unchanged. +No status bits are changed. +\* ************************************************************************* */ +#define enter_invert_mode 0x21 +/* ************************************************************************* *\ +This command causes the display module to invert the image data only on +the display device. The frame memory contents remain unchanged. +No status bits are changed. +\* ************************************************************************* */ +#define set_gamma_curve 0x26 +/* ************************************************************************* *\ +This command selects the desired gamma curve for the display device. +Four fixed gamma curves are defined in section DCS spec. +\* ************************************************************************* */ +#define set_display_off 0x28 +/* ************************************************************************* *\ +This command causes the display module to stop displaying the image data +on the display device. The frame memory contents remain unchanged. +No status bits are changed. +\* ************************************************************************* */ +#define set_display_on 0x29 +/* ************************************************************************* *\ +This command causes the display module to start displaying the image data +on the display device. The frame memory contents remain unchanged. +No status bits are changed. +\* ************************************************************************* */ +#define set_column_address 0x2a +/* ************************************************************************* *\ +This command defines the column extent of the frame memory accessed by the +hostprocessor with the read_memory_continue and write_memory_continue commands. +No status bits are changed. +\* ************************************************************************* */ +#define set_page_address 0x2b +/* ************************************************************************* *\ +This command defines the page extent of the frame memory accessed by the host +processor with the write_memory_continue and read_memory_continue command. +No status bits are changed. +\* ************************************************************************* */ +#define write_mem_start 0x2c +/* ************************************************************************* *\ +This command transfers image data from the host processor to the display +module s frame memory starting at the pixel location specified by +preceding set_column_address and set_page_address commands. +\* ************************************************************************* */ +#define set_partial_area 0x30 +/* ************************************************************************* *\ +This command defines the Partial Display mode s display area. +There are two parameters associated with +this command, the first defines the Start Row (SR) and the second the End Row +(ER). SR and ER refer to the Frame Memory Line Pointer. +\* ************************************************************************* */ +#define set_scroll_area 0x33 +/* ************************************************************************* *\ +This command defines the display modules Vertical Scrolling Area. +\* ************************************************************************* */ +#define set_tear_off 0x34 +/* ************************************************************************* *\ +This command turns off the display modules Tearing Effect output signal on +the TE signal line. +\* ************************************************************************* */ +#define set_tear_on 0x35 +/* ************************************************************************* *\ +This command turns on the display modules Tearing Effect output signal +on the TE signal line. +\* ************************************************************************* */ +#define set_address_mode 0x36 +/* ************************************************************************* *\ +This command sets the data order for transfers from the host processor to +display modules frame memory,bits B[7:5] and B3, and from the display +modules frame memory to the display device, bits B[2:0] and B4. +\* ************************************************************************* */ +#define set_scroll_start 0x37 +/* ************************************************************************* *\ +This command sets the start of the vertical scrolling area in the frame memory. +The vertical scrolling area is fully defined when this command is used with +the set_scroll_area command The set_scroll_start command has one parameter, +the Vertical Scroll Pointer. The VSP defines the line in the frame memory +that is written to the display device as the first line of the vertical +scroll area. +\* ************************************************************************* */ +#define exit_idle_mode 0x38 +/* ************************************************************************* *\ +This command causes the display module to exit Idle mode. +\* ************************************************************************* */ +#define enter_idle_mode 0x39 +/* ************************************************************************* *\ +This command causes the display module to enter Idle Mode. +In Idle Mode, color expression is reduced. Colors are shown on the display +device using the MSB of each of the R, G and B color components in the frame +memory +\* ************************************************************************* */ +#define set_pixel_format 0x3a +/* ************************************************************************* *\ +This command sets the pixel format for the RGB image data used by the interface. +Bits D[6:4] DPI Pixel Format Definition +Bits D[2:0] DBI Pixel Format Definition +Bits D7 and D3 are not used. +\* ************************************************************************* */ +#define write_mem_cont 0x3c +/* ************************************************************************* *\ +This command transfers image data from the host processor to the display +module's frame memory continuing from the pixel location following the +previous write_memory_continue or write_memory_start command. +\* ************************************************************************* */ +#define set_tear_scanline 0x44 +/* ************************************************************************* *\ +This command turns on the display modules Tearing Effect output signal on the +TE signal line when the display module reaches line N. +\* ************************************************************************* */ +#define get_scanline 0x45 +/* ************************************************************************* *\ +The display module returns the current scanline, N, used to update the +display device. The total number of scanlines on a display device is +defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as +the first line of V Sync and is denoted as Line 0. +When in Sleep Mode, the value returned by get_scanline is undefined. +\* ************************************************************************* */ +/* DCS Interface Pixel Formats */ +#define DCS_PIXEL_FORMAT_3BPP 0x1 +#define DCS_PIXEL_FORMAT_8BPP 0x2 +#define DCS_PIXEL_FORMAT_12BPP 0x3 +#define DCS_PIXEL_FORMAT_16BPP 0x5 +#define DCS_PIXEL_FORMAT_18BPP 0x6 +#define DCS_PIXEL_FORMAT_24BPP 0x7 +/* ONE PARAMETER READ DATA */ +#define addr_mode_data 0xfc +#define diag_res_data 0x00 +#define disp_mode_data 0x23 +#define pxl_fmt_data 0x77 +#define pwr_mode_data 0x74 +#define sig_mode_data 0x00 +/* TWO PARAMETERS READ DATA */ +#define scanline_data1 0xff +#define scanline_data2 0xff +/* DPI PIXEL FORMATS */ +#define RGB_565_FMT 0x01 /* RGB 565 FORMAT */ +#define RGB_666_FMT 0x02 /* RGB 666 FORMAT */ +#define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED + * 666 FORMAT + */ +#define RGB_888_FMT 0x04 /* RGB 888 FORMAT */ +#define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode + * with Sync Pulse + */ +#define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode + * with Sync events + */ +#define BURST_MODE 0x03 /* Burst Mode */ +#define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */ +#define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */ +#define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */ +#define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */ +#define DBI_NOT_SUPPORTED 0x00 /* command mode + * is not supported + */ +#define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */ +#define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */ +#define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */ +#define DBI_COMMAND_BUFFER_SIZE 0x120 /* Allocate at least + * 0x100 Byte with 32 + * byte alignment + */ +#define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least + * 0x100 Byte with 32 + * byte alignment + */ +#define ALIGNMENT_32BYTE_MASK (~(BIT0|BIT1|BIT2|BIT3|BIT4)) +#define SKU_83 0x01 +#define SKU_100 0x02 +#define SKU_100L 0x04 +#define SKU_BYPASS 0x08 +#if 0 +/* ************************************************************************* *\ +DSI command data structure +\* ************************************************************************* */ +union DSI_LONG_PACKET_HEADER { + u32 DSI_longPacketHeader; + struct { + u8 dataID; + u16 wordCount; + u8 ECC; + }; +#if 0 /*FIXME JLIU7 */ + struct { + u8 DT:6; + u8 VC:2; + }; +#endif /*FIXME JLIU7 */ +}; + +union MIPI_ADPT_CMD_LNG_REG { + u32 commnadLengthReg; + struct { + u8 command0; + u8 command1; + u8 command2; + u8 command3; + }; +}; + +struct SET_COLUMN_ADDRESS_DATA { + u8 command; + u16 SC; /* Start Column */ + u16 EC; /* End Column */ +}; + +struct SET_PAGE_ADDRESS_DATA { + u8 command; + u16 SP; /* Start Page */ + u16 EP; /* End Page */ +}; +#endif --- /dev/null +++ b/drivers/staging/psb/intel_sdvo.c @@ -0,0 +1,1232 @@ +/* + * Copyright © 2006-2007 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + */ +/* + * Copyright 2006 Dave Airlie + * Jesse Barnes + */ + +#include +#include +#include +#include "intel_sdvo_regs.h" + +struct intel_sdvo_priv { + struct intel_i2c_chan *i2c_bus; + int slaveaddr; + int output_device; + + u16 active_outputs; + + struct intel_sdvo_caps caps; + int pixel_clock_min, pixel_clock_max; + + int save_sdvo_mult; + u16 save_active_outputs; + struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2; + struct intel_sdvo_dtd save_output_dtd[16]; + u32 save_SDVOX; +}; + +/** + * Writes the SDVOB or SDVOC with the given value, but always writes both + * SDVOB and SDVOC to work around apparent hardware issues (according to + * comments in the BIOS). + */ +void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val) +{ + struct drm_device *dev = intel_output->base.dev; + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + u32 bval = val, cval = val; + int i; + + if (sdvo_priv->output_device == SDVOB) + cval = REG_READ(SDVOC); + else + bval = REG_READ(SDVOB); + /* + * Write the registers twice for luck. Sometimes, + * writing them only once doesn't appear to 'stick'. + * The BIOS does this too. Yay, magic + */ + for (i = 0; i < 2; i++) { + REG_WRITE(SDVOB, bval); + REG_READ(SDVOB); + REG_WRITE(SDVOC, cval); + REG_READ(SDVOC); + } +} + +static bool intel_sdvo_read_byte(struct intel_output *intel_output, + u8 addr, u8 *ch) +{ + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + u8 out_buf[2]; + u8 buf[2]; + int ret; + + struct i2c_msg msgs[] = { + { + .addr = sdvo_priv->i2c_bus->slave_addr, + .flags = 0, + .len = 1, + .buf = out_buf, + }, + { + .addr = sdvo_priv->i2c_bus->slave_addr, + .flags = I2C_M_RD, + .len = 1, + .buf = buf, + } + }; + + out_buf[0] = addr; + out_buf[1] = 0; + + ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2); + if (ret == 2) { + /* DRM_DEBUG("got back from addr %02X = %02x\n", + * out_buf[0], buf[0]); + */ + *ch = buf[0]; + return true; + } + + DRM_DEBUG("i2c transfer returned %d\n", ret); + return false; +} + +static bool intel_sdvo_write_byte(struct intel_output *intel_output, + int addr, u8 ch) +{ + u8 out_buf[2]; + struct i2c_msg msgs[] = { + { + .addr = intel_output->i2c_bus->slave_addr, + .flags = 0, + .len = 2, + .buf = out_buf, + } + }; + + out_buf[0] = addr; + out_buf[1] = ch; + + if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1) + return true; + return false; +} + +#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} +/** Mapping of command numbers to names, for debug output */ +const static struct _sdvo_cmd_name { + u8 cmd; + char *name; +} sdvo_cmd_names[] = { +SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), + SDVO_CMD_NAME_ENTRY + (SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), + SDVO_CMD_NAME_ENTRY + (SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), + SDVO_CMD_NAME_ENTRY + (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), + SDVO_CMD_NAME_ENTRY + (SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), + SDVO_CMD_NAME_ENTRY + (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), + SDVO_CMD_NAME_ENTRY + (SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), + SDVO_CMD_NAME_ENTRY + (SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), + SDVO_CMD_NAME_ENTRY + (SDVO_CMD_SET_TV_RESOLUTION_SUPPORT), + SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),}; + +#define SDVO_NAME(dev_priv) \ + ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC") +#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv) + +static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd, + void *args, int args_len) +{ + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + int i; + + if (1) { + DRM_DEBUG("%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd); + for (i = 0; i < args_len; i++) + printk(KERN_INFO"%02X ", ((u8 *) args)[i]); + for (; i < 8; i++) + printk(" "); + for (i = 0; + i < + sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); + i++) { + if (cmd == sdvo_cmd_names[i].cmd) { + printk("(%s)", sdvo_cmd_names[i].name); + break; + } + } + if (i == + sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0])) + printk("(%02X)", cmd); + printk("\n"); + } + + for (i = 0; i < args_len; i++) { + intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i, + ((u8 *) args)[i]); + } + + intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd); +} + +static const char *cmd_status_names[] = { + "Power on", + "Success", + "Not supported", + "Invalid arg", + "Pending", + "Target not specified", + "Scaling not supported" +}; + +static u8 intel_sdvo_read_response(struct intel_output *intel_output, + void *response, int response_len) +{ + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + int i; + u8 status; + u8 retry = 50; + + while (retry--) { + /* Read the command response */ + for (i = 0; i < response_len; i++) { + intel_sdvo_read_byte(intel_output, + SDVO_I2C_RETURN_0 + i, + &((u8 *) response)[i]); + } + + /* read the return status */ + intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS, + &status); + + if (1) { + DRM_DEBUG("%s: R: ", SDVO_NAME(sdvo_priv)); + for (i = 0; i < response_len; i++) + printk(KERN_INFO"%02X ", ((u8 *) response)[i]); + for (; i < 8; i++) + printk(" "); + if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) + printk(KERN_INFO"(%s)", + cmd_status_names[status]); + else + printk(KERN_INFO"(??? %d)", status); + printk("\n"); + } + + if (status != SDVO_CMD_STATUS_PENDING) + return status; + + mdelay(50); + } + + return status; +} + +int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) +{ + if (mode->clock >= 100000) + return 1; + else if (mode->clock >= 50000) + return 2; + else + return 4; +} + +/** + * Don't check status code from this as it switches the bus back to the + * SDVO chips which defeats the purpose of doing a bus switch in the first + * place. + */ +void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output, + u8 target) +{ + intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, + &target, 1); +} + +static bool intel_sdvo_set_target_input(struct intel_output *intel_output, + bool target_0, bool target_1) +{ + struct intel_sdvo_set_target_input_args targets = { 0 }; + u8 status; + + if (target_0 && target_1) + return SDVO_CMD_STATUS_NOTSUPP; + + if (target_1) + targets.target_1 = 1; + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, + &targets, sizeof(targets)); + + status = intel_sdvo_read_response(intel_output, NULL, 0); + + return status == SDVO_CMD_STATUS_SUCCESS; +} + +/** + * Return whether each input is trained. + * + * This function is making an assumption about the layout of the response, + * which should be checked against the docs. + */ +static bool intel_sdvo_get_trained_inputs(struct intel_output + *intel_output, bool *input_1, + bool *input_2) +{ + struct intel_sdvo_get_trained_inputs_response response; + u8 status; + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, + NULL, 0); + status = + intel_sdvo_read_response(intel_output, &response, + sizeof(response)); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + *input_1 = response.input0_trained; + *input_2 = response.input1_trained; + return true; +} + +static bool intel_sdvo_get_active_outputs(struct intel_output + *intel_output, u16 *outputs) +{ + u8 status; + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, + NULL, 0); + status = + intel_sdvo_read_response(intel_output, outputs, + sizeof(*outputs)); + + return status == SDVO_CMD_STATUS_SUCCESS; +} + +static bool intel_sdvo_set_active_outputs(struct intel_output + *intel_output, u16 outputs) +{ + u8 status; + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, + &outputs, sizeof(outputs)); + status = intel_sdvo_read_response(intel_output, NULL, 0); + return status == SDVO_CMD_STATUS_SUCCESS; +} + +static bool intel_sdvo_set_encoder_power_state(struct intel_output + *intel_output, int mode) +{ + u8 status, state = SDVO_ENCODER_STATE_ON; + + switch (mode) { + case DRM_MODE_DPMS_ON: + state = SDVO_ENCODER_STATE_ON; + break; + case DRM_MODE_DPMS_STANDBY: + state = SDVO_ENCODER_STATE_STANDBY; + break; + case DRM_MODE_DPMS_SUSPEND: + state = SDVO_ENCODER_STATE_SUSPEND; + break; + case DRM_MODE_DPMS_OFF: + state = SDVO_ENCODER_STATE_OFF; + break; + } + + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_SET_ENCODER_POWER_STATE, &state, + sizeof(state)); + status = intel_sdvo_read_response(intel_output, NULL, 0); + + return status == SDVO_CMD_STATUS_SUCCESS; +} + +static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output + *intel_output, + int *clock_min, + int *clock_max) +{ + struct intel_sdvo_pixel_clock_range clocks; + u8 status; + + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, NULL, + 0); + + status = + intel_sdvo_read_response(intel_output, &clocks, + sizeof(clocks)); + + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + /* Convert the values from units of 10 kHz to kHz. */ + *clock_min = clocks.min * 10; + *clock_max = clocks.max * 10; + + return true; +} + +static bool intel_sdvo_set_target_output(struct intel_output *intel_output, + u16 outputs) +{ + u8 status; + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, + &outputs, sizeof(outputs)); + + status = intel_sdvo_read_response(intel_output, NULL, 0); + return status == SDVO_CMD_STATUS_SUCCESS; +} + +static bool intel_sdvo_get_timing(struct intel_output *intel_output, + u8 cmd, struct intel_sdvo_dtd *dtd) +{ + u8 status; + + intel_sdvo_write_cmd(intel_output, cmd, NULL, 0); + status = intel_sdvo_read_response(intel_output, &dtd->part1, + sizeof(dtd->part1)); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0); + status = intel_sdvo_read_response(intel_output, &dtd->part2, + sizeof(dtd->part2)); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + return true; +} + +static bool intel_sdvo_get_input_timing(struct intel_output *intel_output, + struct intel_sdvo_dtd *dtd) +{ + return intel_sdvo_get_timing(intel_output, + SDVO_CMD_GET_INPUT_TIMINGS_PART1, + dtd); +} + +static bool intel_sdvo_get_output_timing(struct intel_output *intel_output, + struct intel_sdvo_dtd *dtd) +{ + return intel_sdvo_get_timing(intel_output, + SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, + dtd); +} + +static bool intel_sdvo_set_timing(struct intel_output *intel_output, + u8 cmd, struct intel_sdvo_dtd *dtd) +{ + u8 status; + + intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, + sizeof(dtd->part1)); + status = intel_sdvo_read_response(intel_output, NULL, 0); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, + sizeof(dtd->part2)); + status = intel_sdvo_read_response(intel_output, NULL, 0); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + return true; +} + +static bool intel_sdvo_set_input_timing(struct intel_output *intel_output, + struct intel_sdvo_dtd *dtd) +{ + return intel_sdvo_set_timing(intel_output, + SDVO_CMD_SET_INPUT_TIMINGS_PART1, + dtd); +} + +static bool intel_sdvo_set_output_timing(struct intel_output *intel_output, + struct intel_sdvo_dtd *dtd) +{ + return intel_sdvo_set_timing(intel_output, + SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, + dtd); +} + +#if 0 +static bool intel_sdvo_get_preferred_input_timing(struct intel_output + *intel_output, + struct intel_sdvo_dtd + *dtd) +{ + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + u8 status; + + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, + NULL, 0); + + status = intel_sdvo_read_response(intel_output, &dtd->part1, + sizeof(dtd->part1)); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, + NULL, 0); + status = + intel_sdvo_read_response(intel_output, &dtd->part2, + sizeof(dtd->part2)); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + return true; +} +#endif + +static int intel_sdvo_get_clock_rate_mult(struct intel_output + *intel_output) +{ + u8 response, status; + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, + NULL, 0); + status = intel_sdvo_read_response(intel_output, &response, 1); + + if (status != SDVO_CMD_STATUS_SUCCESS) { + DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n"); + return SDVO_CLOCK_RATE_MULT_1X; + } else { + DRM_DEBUG("Current clock rate multiplier: %d\n", response); + } + + return response; +} + +static bool intel_sdvo_set_clock_rate_mult(struct intel_output + *intel_output, u8 val) +{ + u8 status; + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, + &val, 1); + status = intel_sdvo_read_response(intel_output, NULL, 0); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + return true; +} + +static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + /* Make the CRTC code factor in the SDVO pixel multiplier. The SDVO + * device will be told of the multiplier during mode_set. + */ + adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode); + return true; +} + +static void intel_sdvo_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + struct drm_device *dev = encoder->dev; + struct drm_crtc *crtc = encoder->crtc; + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct intel_output *intel_output = enc_to_intel_output(encoder); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + u16 width, height; + u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len; + u16 h_sync_offset, v_sync_offset; + u32 sdvox; + struct intel_sdvo_dtd output_dtd; + int sdvo_pixel_multiply; + + if (!mode) + return; + + width = mode->crtc_hdisplay; + height = mode->crtc_vdisplay; + + /* do some mode translations */ + h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; + h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; + + v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; + v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; + + h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; + v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; + + output_dtd.part1.clock = mode->clock / 10; + output_dtd.part1.h_active = width & 0xff; + output_dtd.part1.h_blank = h_blank_len & 0xff; + output_dtd.part1.h_high = (((width >> 8) & 0xf) << 4) | + ((h_blank_len >> 8) & 0xf); + output_dtd.part1.v_active = height & 0xff; + output_dtd.part1.v_blank = v_blank_len & 0xff; + output_dtd.part1.v_high = (((height >> 8) & 0xf) << 4) | + ((v_blank_len >> 8) & 0xf); + + output_dtd.part2.h_sync_off = h_sync_offset; + output_dtd.part2.h_sync_width = h_sync_len & 0xff; + output_dtd.part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | + (v_sync_len & 0xf); + output_dtd.part2.sync_off_width_high = + ((h_sync_offset & 0x300) >> 2) | ((h_sync_len & 0x300) >> 4) | + ((v_sync_offset & 0x30) >> 2) | ((v_sync_len & 0x30) >> 4); + + output_dtd.part2.dtd_flags = 0x18; + if (mode->flags & DRM_MODE_FLAG_PHSYNC) + output_dtd.part2.dtd_flags |= 0x2; + if (mode->flags & DRM_MODE_FLAG_PVSYNC) + output_dtd.part2.dtd_flags |= 0x4; + + output_dtd.part2.sdvo_flags = 0; + output_dtd.part2.v_sync_off_high = v_sync_offset & 0xc0; + output_dtd.part2.reserved = 0; + + /* Set the output timing to the screen */ + intel_sdvo_set_target_output(intel_output, + sdvo_priv->active_outputs); + intel_sdvo_set_output_timing(intel_output, &output_dtd); + + /* Set the input timing to the screen. Assume always input 0. */ + intel_sdvo_set_target_input(intel_output, true, false); + + /* We would like to use i830_sdvo_create_preferred_input_timing() to + * provide the device with a timing it can support, if it supports that + * feature. However, presumably we would need to adjust the CRTC to + * output the preferred timing, and we don't support that currently. + */ +#if 0 + success = + intel_sdvo_create_preferred_input_timing(intel_output, clock, + width, height); + if (success) { + struct intel_sdvo_dtd *input_dtd; + + intel_sdvo_get_preferred_input_timing(intel_output, + &input_dtd); + intel_sdvo_set_input_timing(intel_output, &input_dtd); + } +#else + intel_sdvo_set_input_timing(intel_output, &output_dtd); +#endif + + switch (intel_sdvo_get_pixel_multiplier(mode)) { + case 1: + intel_sdvo_set_clock_rate_mult(intel_output, + SDVO_CLOCK_RATE_MULT_1X); + break; + case 2: + intel_sdvo_set_clock_rate_mult(intel_output, + SDVO_CLOCK_RATE_MULT_2X); + break; + case 4: + intel_sdvo_set_clock_rate_mult(intel_output, + SDVO_CLOCK_RATE_MULT_4X); + break; + } + + /* Set the SDVO control regs. */ + if (0 /*IS_I965GM(dev) */) { + sdvox = SDVO_BORDER_ENABLE; + } else { + sdvox = REG_READ(sdvo_priv->output_device); + switch (sdvo_priv->output_device) { + case SDVOB: + sdvox &= SDVOB_PRESERVE_MASK; + break; + case SDVOC: + sdvox &= SDVOC_PRESERVE_MASK; + break; + } + sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; + } + if (intel_crtc->pipe == 1) + sdvox |= SDVO_PIPE_B_SELECT; + + sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode); + if (IS_I965G(dev)) { + /* done in crtc_mode_set as the dpll_md reg must be written + * early */ + } else if (IS_I945G(dev) || IS_I945GM(dev)) { + /* done in crtc_mode_set as it lives inside the + * dpll register */ + } else { + sdvox |= + (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT; + } + + intel_sdvo_write_sdvox(intel_output, sdvox); +} + +static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) +{ + struct drm_device *dev = encoder->dev; + struct intel_output *intel_output = enc_to_intel_output(encoder); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + u32 temp; + + if (mode != DRM_MODE_DPMS_ON) { + intel_sdvo_set_active_outputs(intel_output, 0); + if (0) + intel_sdvo_set_encoder_power_state(intel_output, + mode); + + if (mode == DRM_MODE_DPMS_OFF) { + temp = REG_READ(sdvo_priv->output_device); + if ((temp & SDVO_ENABLE) != 0) { + intel_sdvo_write_sdvox(intel_output, + temp & + ~SDVO_ENABLE); + } + } + } else { + bool input1, input2; + int i; + u8 status; + + temp = REG_READ(sdvo_priv->output_device); + if ((temp & SDVO_ENABLE) == 0) + intel_sdvo_write_sdvox(intel_output, + temp | SDVO_ENABLE); + for (i = 0; i < 2; i++) + intel_wait_for_vblank(dev); + + status = + intel_sdvo_get_trained_inputs(intel_output, &input1, + &input2); + + + /* Warn if the device reported failure to sync. + * A lot of SDVO devices fail to notify of sync, but it's + * a given it the status is a success, we succeeded. + */ + if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { + DRM_DEBUG + ("First %s output reported failure to sync\n", + SDVO_NAME(sdvo_priv)); + } + + if (0) + intel_sdvo_set_encoder_power_state(intel_output, + mode); + intel_sdvo_set_active_outputs(intel_output, + sdvo_priv->active_outputs); + } + return; +} + +static void intel_sdvo_save(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + int o; + + sdvo_priv->save_sdvo_mult = + intel_sdvo_get_clock_rate_mult(intel_output); + intel_sdvo_get_active_outputs(intel_output, + &sdvo_priv->save_active_outputs); + + if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { + intel_sdvo_set_target_input(intel_output, true, false); + intel_sdvo_get_input_timing(intel_output, + &sdvo_priv->save_input_dtd_1); + } + + if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { + intel_sdvo_set_target_input(intel_output, false, true); + intel_sdvo_get_input_timing(intel_output, + &sdvo_priv->save_input_dtd_2); + } + + for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) { + u16 this_output = (1 << o); + if (sdvo_priv->caps.output_flags & this_output) { + intel_sdvo_set_target_output(intel_output, + this_output); + intel_sdvo_get_output_timing(intel_output, + &sdvo_priv-> + save_output_dtd[o]); + } + } + + sdvo_priv->save_SDVOX = REG_READ(sdvo_priv->output_device); +} + +static void intel_sdvo_restore(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + int o; + int i; + bool input1, input2; + u8 status; + + intel_sdvo_set_active_outputs(intel_output, 0); + + for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++) { + u16 this_output = (1 << o); + if (sdvo_priv->caps.output_flags & this_output) { + intel_sdvo_set_target_output(intel_output, + this_output); + intel_sdvo_set_output_timing(intel_output, + &sdvo_priv-> + save_output_dtd[o]); + } + } + + if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) { + intel_sdvo_set_target_input(intel_output, true, false); + intel_sdvo_set_input_timing(intel_output, + &sdvo_priv->save_input_dtd_1); + } + + if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) { + intel_sdvo_set_target_input(intel_output, false, true); + intel_sdvo_set_input_timing(intel_output, + &sdvo_priv->save_input_dtd_2); + } + + intel_sdvo_set_clock_rate_mult(intel_output, + sdvo_priv->save_sdvo_mult); + + REG_WRITE(sdvo_priv->output_device, sdvo_priv->save_SDVOX); + + if (sdvo_priv->save_SDVOX & SDVO_ENABLE) { + for (i = 0; i < 2; i++) + intel_wait_for_vblank(dev); + status = + intel_sdvo_get_trained_inputs(intel_output, &input1, + &input2); + if (status == SDVO_CMD_STATUS_SUCCESS && !input1) + DRM_DEBUG + ("First %s output reported failure to sync\n", + SDVO_NAME(sdvo_priv)); + } + + intel_sdvo_set_active_outputs(intel_output, + sdvo_priv->save_active_outputs); +} + +static int intel_sdvo_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + struct intel_output *intel_output = to_intel_output(connector); + struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv; + + if (mode->flags & DRM_MODE_FLAG_DBLSCAN) + return MODE_NO_DBLESCAN; + + if (sdvo_priv->pixel_clock_min > mode->clock) + return MODE_CLOCK_LOW; + + if (sdvo_priv->pixel_clock_max < mode->clock) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + +static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, + struct intel_sdvo_caps *caps) +{ + u8 status; + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, + 0); + status = + intel_sdvo_read_response(intel_output, caps, sizeof(*caps)); + if (status != SDVO_CMD_STATUS_SUCCESS) + return false; + + return true; +} + +struct drm_connector *intel_sdvo_find(struct drm_device *dev, int sdvoB) +{ + struct drm_connector *connector = NULL; + struct intel_output *iout = NULL; + struct intel_sdvo_priv *sdvo; + + /* find the sdvo connector */ + list_for_each_entry(connector, &dev->mode_config.connector_list, + head) { + iout = to_intel_output(connector); + + if (iout->type != INTEL_OUTPUT_SDVO) + continue; + + sdvo = iout->dev_priv; + + if (sdvo->output_device == SDVOB && sdvoB) + return connector; + + if (sdvo->output_device == SDVOC && !sdvoB) + return connector; + + } + + return NULL; +} + +int intel_sdvo_supports_hotplug(struct drm_connector *connector) +{ + u8 response[2]; + u8 status; + struct intel_output *intel_output; + DRM_DEBUG("\n"); + + if (!connector) + return 0; + + intel_output = to_intel_output(connector); + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, + NULL, 0); + status = intel_sdvo_read_response(intel_output, &response, 2); + + if (response[0] != 0) + return 1; + + return 0; +} + +void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) +{ + u8 response[2]; + u8 status; + struct intel_output *intel_output = to_intel_output(connector); + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, + NULL, 0); + intel_sdvo_read_response(intel_output, &response, 2); + + if (on) { + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, + 0); + status = + intel_sdvo_read_response(intel_output, &response, 2); + + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_SET_ACTIVE_HOT_PLUG, + &response, 2); + } else { + response[0] = 0; + response[1] = 0; + intel_sdvo_write_cmd(intel_output, + SDVO_CMD_SET_ACTIVE_HOT_PLUG, + &response, 2); + } + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, + NULL, 0); + intel_sdvo_read_response(intel_output, &response, 2); +} + +static enum drm_connector_status intel_sdvo_detect(struct drm_connector + *connector) +{ + u8 response[2]; + u8 status; + struct intel_output *intel_output = to_intel_output(connector); + + intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, + NULL, 0); + status = intel_sdvo_read_response(intel_output, &response, 2); + + DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]); + if ((response[0] != 0) || (response[1] != 0)) + return connector_status_connected; + else + return connector_status_disconnected; +} + +static int intel_sdvo_get_modes(struct drm_connector *connector) +{ + struct intel_output *intel_output = to_intel_output(connector); + + /* set the bus switch and get the modes */ + intel_sdvo_set_control_bus_switch(intel_output, + SDVO_CONTROL_BUS_DDC2); + intel_ddc_get_modes(intel_output); + + if (list_empty(&connector->probed_modes)) + return 0; + return 1; +#if 0 + /* Mac mini hack. On this device, I get DDC through the analog, which + * load-detects as disconnected. I fail to DDC through the SDVO DDC, + * but it does load-detect as connected. So, just steal the DDC bits + * from analog when we fail at finding it the right way. + */ + /* TODO */ + return NULL; + + return NULL; +#endif +} + +static void intel_sdvo_destroy(struct drm_connector *connector) +{ + struct intel_output *intel_output = to_intel_output(connector); + + if (intel_output->i2c_bus) + intel_i2c_destroy(intel_output->i2c_bus); + drm_sysfs_connector_remove(connector); + drm_connector_cleanup(connector); + kfree(intel_output); +} + +static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { + .dpms = intel_sdvo_dpms, + .mode_fixup = intel_sdvo_mode_fixup, + .prepare = intel_encoder_prepare, + .mode_set = intel_sdvo_mode_set, + .commit = intel_encoder_commit, +}; + +static const struct drm_connector_funcs intel_sdvo_connector_funcs = { + .save = intel_sdvo_save, + .restore = intel_sdvo_restore, + .detect = intel_sdvo_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = intel_sdvo_destroy, +}; + +static const struct drm_connector_helper_funcs + intel_sdvo_connector_helper_funcs = { + .get_modes = intel_sdvo_get_modes, + .mode_valid = intel_sdvo_mode_valid, + .best_encoder = intel_best_encoder, +}; + +void intel_sdvo_enc_destroy(struct drm_encoder *encoder) +{ + drm_encoder_cleanup(encoder); +} + +static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { + .destroy = intel_sdvo_enc_destroy, +}; + + +void intel_sdvo_init(struct drm_device *dev, int output_device) +{ + struct drm_connector *connector; + struct intel_output *intel_output; + struct intel_sdvo_priv *sdvo_priv; + struct intel_i2c_chan *i2cbus = NULL; + int connector_type; + u8 ch[0x40]; + int i; + int encoder_type, output_id; + + intel_output = + kcalloc(sizeof(struct intel_output) + + sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL); + if (!intel_output) + return; + + connector = &intel_output->base; + + drm_connector_init(dev, connector, &intel_sdvo_connector_funcs, + DRM_MODE_CONNECTOR_Unknown); + drm_connector_helper_add(connector, + &intel_sdvo_connector_helper_funcs); + sdvo_priv = (struct intel_sdvo_priv *) (intel_output + 1); + intel_output->type = INTEL_OUTPUT_SDVO; + + connector->interlace_allowed = 0; + connector->doublescan_allowed = 0; + + /* setup the DDC bus. */ + if (output_device == SDVOB) + i2cbus = + intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB"); + else + i2cbus = + intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC"); + + if (!i2cbus) + goto err_connector; + + sdvo_priv->i2c_bus = i2cbus; + + if (output_device == SDVOB) { + output_id = 1; + sdvo_priv->i2c_bus->slave_addr = 0x38; + } else { + output_id = 2; + sdvo_priv->i2c_bus->slave_addr = 0x39; + } + + sdvo_priv->output_device = output_device; + intel_output->i2c_bus = i2cbus; + intel_output->dev_priv = sdvo_priv; + + + /* Read the regs to test if we can talk to the device */ + for (i = 0; i < 0x40; i++) { + if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) { + DRM_DEBUG("No SDVO device found on SDVO%c\n", + output_device == SDVOB ? 'B' : 'C'); + goto err_i2c; + } + } + + intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps); + + memset(&sdvo_priv->active_outputs, 0, + sizeof(sdvo_priv->active_outputs)); + + /* TODO, CVBS, SVID, YPRPB & SCART outputs. */ + if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0) { + sdvo_priv->active_outputs = SDVO_OUTPUT_RGB0; + connector->display_info.subpixel_order = + SubPixelHorizontalRGB; + encoder_type = DRM_MODE_ENCODER_DAC; + connector_type = DRM_MODE_CONNECTOR_VGA; + } else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1) { + sdvo_priv->active_outputs = SDVO_OUTPUT_RGB1; + connector->display_info.subpixel_order = + SubPixelHorizontalRGB; + encoder_type = DRM_MODE_ENCODER_DAC; + connector_type = DRM_MODE_CONNECTOR_VGA; + } else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0) { + sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS0; + connector->display_info.subpixel_order = + SubPixelHorizontalRGB; + encoder_type = DRM_MODE_ENCODER_TMDS; + connector_type = DRM_MODE_CONNECTOR_DVID; + } else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS1) { + sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS1; + connector->display_info.subpixel_order = + SubPixelHorizontalRGB; + encoder_type = DRM_MODE_ENCODER_TMDS; + connector_type = DRM_MODE_CONNECTOR_DVID; + } else { + unsigned char bytes[2]; + + memcpy(bytes, &sdvo_priv->caps.output_flags, 2); + DRM_DEBUG + ("%s: No active RGB or TMDS outputs (0x%02x%02x)\n", + SDVO_NAME(sdvo_priv), bytes[0], bytes[1]); + goto err_i2c; + } + + drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, + encoder_type); + drm_encoder_helper_add(&intel_output->enc, + &intel_sdvo_helper_funcs); + connector->connector_type = connector_type; + + drm_mode_connector_attach_encoder(&intel_output->base, + &intel_output->enc); + drm_sysfs_connector_add(connector); + + /* Set the input timing to the screen. Assume always input 0. */ + intel_sdvo_set_target_input(intel_output, true, false); + + intel_sdvo_get_input_pixel_clock_range(intel_output, + &sdvo_priv->pixel_clock_min, + &sdvo_priv-> + pixel_clock_max); + + + DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, " + "clock range %dMHz - %dMHz, " + "input 1: %c, input 2: %c, " + "output 1: %c, output 2: %c\n", + SDVO_NAME(sdvo_priv), + sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id, + sdvo_priv->caps.device_rev_id, + sdvo_priv->pixel_clock_min / 1000, + sdvo_priv->pixel_clock_max / 1000, + (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', + (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', + /* check currently supported outputs */ + sdvo_priv->caps.output_flags & + (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', + sdvo_priv->caps.output_flags & + (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); + + intel_output->ddc_bus = i2cbus; + + return; + +err_i2c: + intel_i2c_destroy(intel_output->i2c_bus); +err_connector: + drm_connector_cleanup(connector); + kfree(intel_output); + + return; +} --- /dev/null +++ b/drivers/staging/psb/intel_sdvo_regs.h @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2008, Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + */ + +/** + * @file SDVO command definitions and structures. + */ + +#define SDVO_OUTPUT_FIRST (0) +#define SDVO_OUTPUT_TMDS0 (1 << 0) +#define SDVO_OUTPUT_RGB0 (1 << 1) +#define SDVO_OUTPUT_CVBS0 (1 << 2) +#define SDVO_OUTPUT_SVID0 (1 << 3) +#define SDVO_OUTPUT_YPRPB0 (1 << 4) +#define SDVO_OUTPUT_SCART0 (1 << 5) +#define SDVO_OUTPUT_LVDS0 (1 << 6) +#define SDVO_OUTPUT_TMDS1 (1 << 8) +#define SDVO_OUTPUT_RGB1 (1 << 9) +#define SDVO_OUTPUT_CVBS1 (1 << 10) +#define SDVO_OUTPUT_SVID1 (1 << 11) +#define SDVO_OUTPUT_YPRPB1 (1 << 12) +#define SDVO_OUTPUT_SCART1 (1 << 13) +#define SDVO_OUTPUT_LVDS1 (1 << 14) +#define SDVO_OUTPUT_LAST (14) + +struct intel_sdvo_caps { + u8 vendor_id; + u8 device_id; + u8 device_rev_id; + u8 sdvo_version_major; + u8 sdvo_version_minor; + unsigned int sdvo_inputs_mask:2; + unsigned int smooth_scaling:1; + unsigned int sharp_scaling:1; + unsigned int up_scaling:1; + unsigned int down_scaling:1; + unsigned int stall_support:1; + unsigned int pad:1; + u16 output_flags; +} __attribute__ ((packed)); + +/** This matches the EDID DTD structure, more or less */ +struct intel_sdvo_dtd { + struct { + u16 clock; /**< pixel clock, in 10kHz units */ + u8 h_active; /**< lower 8 bits (pixels) */ + u8 h_blank; /**< lower 8 bits (pixels) */ + u8 h_high; /**< upper 4 bits each h_active, h_blank */ + u8 v_active; /**< lower 8 bits (lines) */ + u8 v_blank; /**< lower 8 bits (lines) */ + u8 v_high; /**< upper 4 bits each v_active, v_blank */ + } part1; + + struct { + u8 h_sync_off; + /**< lower 8 bits, from hblank start */ + u8 h_sync_width;/**< lower 8 bits (pixels) */ + /** lower 4 bits each vsync offset, vsync width */ + u8 v_sync_off_width; + /** + * 2 high bits of hsync offset, 2 high bits of hsync width, + * bits 4-5 of vsync offset, and 2 high bits of vsync width. + */ + u8 sync_off_width_high; + u8 dtd_flags; + u8 sdvo_flags; + /** bits 6-7 of vsync offset at bits 6-7 */ + u8 v_sync_off_high; + u8 reserved; + } part2; +} __attribute__ ((packed)); + +struct intel_sdvo_pixel_clock_range { + u16 min; /**< pixel clock, in 10kHz units */ + u16 max; /**< pixel clock, in 10kHz units */ +} __attribute__ ((packed)); + +struct intel_sdvo_preferred_input_timing_args { + u16 clock; + u16 width; + u16 height; +} __attribute__ ((packed)); + +/* I2C registers for SDVO */ +#define SDVO_I2C_ARG_0 0x07 +#define SDVO_I2C_ARG_1 0x06 +#define SDVO_I2C_ARG_2 0x05 +#define SDVO_I2C_ARG_3 0x04 +#define SDVO_I2C_ARG_4 0x03 +#define SDVO_I2C_ARG_5 0x02 +#define SDVO_I2C_ARG_6 0x01 +#define SDVO_I2C_ARG_7 0x00 +#define SDVO_I2C_OPCODE 0x08 +#define SDVO_I2C_CMD_STATUS 0x09 +#define SDVO_I2C_RETURN_0 0x0a +#define SDVO_I2C_RETURN_1 0x0b +#define SDVO_I2C_RETURN_2 0x0c +#define SDVO_I2C_RETURN_3 0x0d +#define SDVO_I2C_RETURN_4 0x0e +#define SDVO_I2C_RETURN_5 0x0f +#define SDVO_I2C_RETURN_6 0x10 +#define SDVO_I2C_RETURN_7 0x11 +#define SDVO_I2C_VENDOR_BEGIN 0x20 + +/* Status results */ +#define SDVO_CMD_STATUS_POWER_ON 0x0 +#define SDVO_CMD_STATUS_SUCCESS 0x1 +#define SDVO_CMD_STATUS_NOTSUPP 0x2 +#define SDVO_CMD_STATUS_INVALID_ARG 0x3 +#define SDVO_CMD_STATUS_PENDING 0x4 +#define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5 +#define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6 + +/* SDVO commands, argument/result registers */ + +#define SDVO_CMD_RESET 0x01 + +/** Returns a struct intel_sdvo_caps */ +#define SDVO_CMD_GET_DEVICE_CAPS 0x02 + +#define SDVO_CMD_GET_FIRMWARE_REV 0x86 +# define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0 +# define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1 +# define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2 + +/** + * Reports which inputs are trained (managed to sync). + * + * Devices must have trained within 2 vsyncs of a mode change. + */ +#define SDVO_CMD_GET_TRAINED_INPUTS 0x03 +struct intel_sdvo_get_trained_inputs_response { + unsigned int input0_trained:1; + unsigned int input1_trained:1; + unsigned int pad:6; +} __attribute__ ((packed)); + +/** Returns a struct intel_sdvo_output_flags of active outputs. */ +#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04 + +/** + * Sets the current set of active outputs. + * + * Takes a struct intel_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP + * on multi-output devices. + */ +#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05 + +/** + * Returns the current mapping of SDVO inputs to outputs on the device. + * + * Returns two struct intel_sdvo_output_flags structures. + */ +#define SDVO_CMD_GET_IN_OUT_MAP 0x06 + +/** + * Sets the current mapping of SDVO inputs to outputs on the device. + * + * Takes two struct i380_sdvo_output_flags structures. + */ +#define SDVO_CMD_SET_IN_OUT_MAP 0x07 + +/** + * Returns a struct intel_sdvo_output_flags of attached displays. + */ +#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b + +/** + * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging. + */ +#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c + +/** + * Takes a struct intel_sdvo_output_flags. + */ +#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d + +/** + * Returns a struct intel_sdvo_output_flags of displays with hot plug + * interrupts enabled. + */ +#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e + +#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f +struct intel_sdvo_get_interrupt_event_source_response { + u16 interrupt_status; + unsigned int ambient_light_interrupt:1; + unsigned int pad:7; +} __attribute__ ((packed)); + +/** + * Selects which input is affected by future input commands. + * + * Commands affected include SET_INPUT_TIMINGS_PART[12], + * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12], + * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS. + */ +#define SDVO_CMD_SET_TARGET_INPUT 0x10 +struct intel_sdvo_set_target_input_args { + unsigned int target_1:1; + unsigned int pad:7; +} __attribute__ ((packed)); + +/** + * Takes a struct intel_sdvo_output_flags of which outputs are targetted by + * future output commands. + * + * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12], + * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE. + */ +#define SDVO_CMD_SET_TARGET_OUTPUT 0x11 + +#define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12 +#define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13 +#define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14 +#define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15 +#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16 +#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17 +#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18 +#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19 +/* Part 1 */ +# define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0 +# define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1 +# define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2 +# define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3 +# define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4 +# define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5 +# define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6 +# define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7 +/* Part 2 */ +# define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0 +# define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1 +# define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2 +# define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3 +# define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4 +# define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7) +# define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5) +# define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3) +# define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1) +# define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5 +# define SDVO_DTD_SDVO_FLAG_STALL (1 << 7) +# define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6) +# define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6) +# define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4) +# define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4) +# define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4) +# define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4) +# define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6 + +/** + * Generates a DTD based on the given width, height, and flags. + * + * This will be supported by any device supporting scaling or interlaced + * modes. + */ +#define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a +# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0 +# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1 +# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2 +# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3 +# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4 +# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5 +# define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6 +# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0) +# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1) + +#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b +#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c + +/** Returns a struct intel_sdvo_pixel_clock_range */ +#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d +/** Returns a struct intel_sdvo_pixel_clock_range */ +#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e + +/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */ +#define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f + +/** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ +#define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20 +/** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */ +#define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21 +# define SDVO_CLOCK_RATE_MULT_1X (1 << 0) +# define SDVO_CLOCK_RATE_MULT_2X (1 << 1) +# define SDVO_CLOCK_RATE_MULT_4X (1 << 3) + +#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27 + +#define SDVO_CMD_GET_TV_FORMAT 0x28 + +#define SDVO_CMD_SET_TV_FORMAT 0x29 + +#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a +#define SDVO_CMD_GET_ENCODER_POWER_STATE 0x2b +#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c +# define SDVO_ENCODER_STATE_ON (1 << 0) +# define SDVO_ENCODER_STATE_STANDBY (1 << 1) +# define SDVO_ENCODER_STATE_SUSPEND (1 << 2) +# define SDVO_ENCODER_STATE_OFF (1 << 3) + +#define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93 + +#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a +# define SDVO_CONTROL_BUS_PROM 0x0 +# define SDVO_CONTROL_BUS_DDC1 0x1 +# define SDVO_CONTROL_BUS_DDC2 0x2 +# define SDVO_CONTROL_BUS_DDC3 0x3 --- /dev/null +++ b/drivers/staging/psb/Kconfig @@ -0,0 +1,9 @@ +config DRM_PSB + tristate "Intel Poulsbo/Moorestown DRM support" + depends on DRM && PCI + select FB_CFB_COPYAREA + select FB_CFB_FILLRECT + select FB_CFB_IMAGEBLIT + help + Choose this option if you have a Poulsbo or Moorestown platform. + If M is selected the module will be called psb. --- /dev/null +++ b/drivers/staging/psb/lnc_topaz.c @@ -0,0 +1,695 @@ +/** + * file lnc_topaz.c + * TOPAZ I/O operations and IRQ handling + * + */ + +/************************************************************************** + * + * Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA + * Copyright (c) Imagination Technologies Limited, UK + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +/* include headers */ +/* #define DRM_DEBUG_CODE 2 */ + +#include +#include + +#include "psb_drv.h" +#include "psb_drm.h" +#include "lnc_topaz.h" + +#include +#include + +static int drm_psb_ospmxxx = 0x0; + +/* static function define */ +static int lnc_topaz_deliver_command(struct drm_device *dev, + struct ttm_buffer_object *cmd_buffer, + unsigned long cmd_offset, + unsigned long cmd_size, + void **topaz_cmd, uint32_t sequence, + int copy_cmd); +static int lnc_topaz_send(struct drm_device *dev, void *cmd, + unsigned long cmd_size, uint32_t sync_seq); +static int lnc_mtx_send(struct drm_psb_private *dev_priv, const void *cmd); +static int lnc_topaz_dequeue_send(struct drm_device *dev); +static int lnc_topaz_save_command(struct drm_device *dev, void *cmd, + unsigned long cmd_size, uint32_t sequence); + +void lnc_topaz_interrupt(struct drm_device *dev, uint32_t topaz_stat) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *)dev->dev_private; + uint32_t clr_flag = lnc_topaz_queryirq(dev); + + lnc_topaz_clearirq(dev, clr_flag); + + /* ignore non-SYNC interrupts */ + if ((CCB_CTRL_SEQ(dev_priv) & 0x8000) == 0) + return; + + dev_priv->topaz_current_sequence = + *(uint32_t *)dev_priv->topaz_sync_addr; + + PSB_DEBUG_IRQ("TOPAZ:Got SYNC IRQ,sync seq:0x%08x (MTX) vs 0x%08x\n", + dev_priv->topaz_current_sequence, + dev_priv->sequence[LNC_ENGINE_ENCODE]); + + psb_fence_handler(dev, LNC_ENGINE_ENCODE); + + dev_priv->topaz_busy = 1; + lnc_topaz_dequeue_send(dev); +} + +static int lnc_submit_encode_cmdbuf(struct drm_device *dev, + struct ttm_buffer_object *cmd_buffer, + unsigned long cmd_offset, unsigned long cmd_size, + struct ttm_fence_object *fence) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + unsigned long irq_flags; + int ret = 0; + void *cmd; + uint32_t sequence = dev_priv->sequence[LNC_ENGINE_ENCODE]; + + PSB_DEBUG_GENERAL("TOPAZ: command submit\n"); + + /* # lock topaz's mutex [msvdx_mutex] */ + mutex_lock(&dev_priv->topaz_mutex); + + PSB_DEBUG_GENERAL("TOPAZ: topaz busy = %d\n", dev_priv->topaz_busy); + + if (dev_priv->topaz_fw_loaded == 0) { + /* #.# load fw to driver */ + PSB_DEBUG_INIT("TOPAZ: load /lib/firmware/topaz_fw.bin\n"); + ret = topaz_init_fw(dev); + if (ret != 0) { + mutex_unlock(&dev_priv->topaz_mutex); + + /* FIXME: find a proper return value */ + DRM_ERROR("TOPAX:load /lib/firmware/topaz_fw.bin fail," + "ensure udevd is configured correctly!\n"); + + return -EFAULT; + } + dev_priv->topaz_fw_loaded = 1; + } else { + /* OSPM power state change */ + /* FIXME: why here? why not in the NEW_CODEC case? */ + if (drm_psb_ospmxxx & ENABLE_TOPAZ_OSPM_D0IX) { + psb_power_up_topaz(dev); + lnc_topaz_restore_mtx_state(dev); + } + } + + /* # schedule watchdog */ + /* psb_schedule_watchdog(dev_priv); */ + + /* # spin lock irq save [msvdx_lock] */ + spin_lock_irqsave(&dev_priv->topaz_lock, irq_flags); + + /* # if topaz need to reset, reset it */ + if (dev_priv->topaz_needs_reset) { + /* #.# reset it */ + spin_unlock_irqrestore(&dev_priv->topaz_lock, irq_flags); + PSB_DEBUG_GENERAL("TOPAZ: needs reset.\n"); + + if (lnc_topaz_reset(dev_priv)) { + mutex_unlock(&dev_priv->topaz_mutex); + ret = -EBUSY; + DRM_ERROR("TOPAZ: reset failed.\n"); + return ret; + } + + PSB_DEBUG_GENERAL("TOPAZ: reset ok.\n"); + + /* #.# reset any related flags */ + dev_priv->topaz_needs_reset = 0; + dev_priv->topaz_busy = 0; + PSB_DEBUG_GENERAL("XXX: does we need idle flag??\n"); + dev_priv->topaz_start_idle = 0; + + /* #.# init topaz */ + lnc_topaz_init(dev); + + /* avoid another fw init */ + dev_priv->topaz_fw_loaded = 1; + + spin_lock_irqsave(&dev_priv->topaz_lock, irq_flags); + } + + if (!dev_priv->topaz_busy) { + /* # direct map topaz command if topaz is free */ + PSB_DEBUG_GENERAL("TOPAZ:direct send command,sequence %08x \n", + sequence); + + dev_priv->topaz_busy = 1; + spin_unlock_irqrestore(&dev_priv->topaz_lock, irq_flags); + + ret = lnc_topaz_deliver_command(dev, cmd_buffer, cmd_offset, + cmd_size, NULL, sequence, 0); + + if (ret) { + DRM_ERROR("TOPAZ: failed to extract cmd...\n"); + mutex_unlock(&dev_priv->topaz_mutex); + return ret; + } + } else { + PSB_DEBUG_GENERAL("TOPAZ: queue command,sequence %08x \n", + sequence); + cmd = NULL; + + spin_unlock_irqrestore(&dev_priv->topaz_lock, irq_flags); + + ret = lnc_topaz_deliver_command(dev, cmd_buffer, cmd_offset, + cmd_size, &cmd, sequence, 1); + if (cmd == NULL || ret) { + DRM_ERROR("TOPAZ: map command for save fialed\n"); + mutex_unlock(&dev_priv->topaz_mutex); + return ret; + } + + ret = lnc_topaz_save_command(dev, cmd, cmd_size, sequence); + if (ret) + DRM_ERROR("TOPAZ: save command failed\n"); + } + + /* OPSM D0IX power state change */ + if (drm_psb_ospmxxx & ENABLE_TOPAZ_OSPM_D0IX) + lnc_topaz_save_mtx_state(dev); + + mutex_unlock(&dev_priv->topaz_mutex); + + return ret; +} + +static int lnc_topaz_save_command(struct drm_device *dev, void *cmd, + unsigned long cmd_size, uint32_t sequence) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + struct lnc_topaz_cmd_queue *topaz_cmd; + unsigned long irq_flags; + + PSB_DEBUG_GENERAL("TOPAZ: queue command,sequence: %08x..\n", + sequence); + + topaz_cmd = drm_calloc(1, sizeof(struct lnc_topaz_cmd_queue), + DRM_MEM_DRIVER); + if (topaz_cmd == NULL) { + mutex_unlock(&dev_priv->topaz_mutex); + DRM_ERROR("TOPAZ: out of memory....\n"); + return -ENOMEM; + } + + topaz_cmd->cmd = cmd; + topaz_cmd->cmd_size = cmd_size; + topaz_cmd->sequence = sequence; + + spin_lock_irqsave(&dev_priv->topaz_lock, irq_flags); + list_add_tail(&topaz_cmd->head, &dev_priv->topaz_queue); + if (!dev_priv->topaz_busy) { + /* dev_priv->topaz_busy = 1; */ + PSB_DEBUG_GENERAL("TOPAZ: need immediate dequeue...\n"); + lnc_topaz_dequeue_send(dev); + PSB_DEBUG_GENERAL("TOPAZ: after dequeue command\n"); + } + + spin_unlock_irqrestore(&dev_priv->topaz_lock, irq_flags); + + return 0; +} + + +int lnc_cmdbuf_video(struct drm_file *priv, + struct list_head *validate_list, + uint32_t fence_type, + struct drm_psb_cmdbuf_arg *arg, + struct ttm_buffer_object *cmd_buffer, + struct psb_ttm_fence_rep *fence_arg) +{ + struct drm_device *dev = priv->minor->dev; + struct ttm_fence_object *fence = NULL; + int ret; + + ret = lnc_submit_encode_cmdbuf(dev, cmd_buffer, arg->cmdbuf_offset, + arg->cmdbuf_size, fence); + if (ret) + return ret; + +#if LNC_TOPAZ_NO_IRQ /* workaround for interrupt issue */ + psb_fence_or_sync(priv, LNC_ENGINE_ENCODE, fence_type, arg->fence_flags, + validate_list, fence_arg, &fence); + + if (fence) + ttm_fence_object_unref(&fence); +#endif + + mutex_lock(&cmd_buffer->mutex); + if (cmd_buffer->sync_obj != NULL) + ttm_fence_sync_obj_unref(&cmd_buffer->sync_obj); + mutex_unlock(&cmd_buffer->mutex); + + return 0; +} + +static int lnc_topaz_sync(struct drm_device *dev, uint32_t sync_seq) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + uint32_t sync_cmd[3]; + int count = 10000; +#if 0 + struct ttm_fence_device *fdev = &dev_priv->fdev; + struct ttm_fence_class_manager *fc = + &fdev->fence_class[LNC_ENGINE_ENCODE]; + unsigned long irq_flags; +#endif + uint32_t *sync_p = (uint32_t *)dev_priv->topaz_sync_addr; + + /* insert a SYNC command here */ + dev_priv->topaz_sync_cmd_seq = (1 << 15) | dev_priv->topaz_cmd_seq++; + sync_cmd[0] = MTX_CMDID_SYNC | (3 << 8) | + (dev_priv->topaz_sync_cmd_seq << 16); + sync_cmd[1] = dev_priv->topaz_sync_offset; + sync_cmd[2] = sync_seq; + + PSB_DEBUG_GENERAL("TOPAZ:MTX_CMDID_SYNC: size(3),cmd seq (0x%04x)," + "sync_seq (0x%08x)\n", + dev_priv->topaz_sync_cmd_seq, sync_seq); + + lnc_mtx_send(dev_priv, sync_cmd); + +#if LNC_TOPAZ_NO_IRQ /* workaround for interrupt issue */ + /* # poll topaz register for certain times */ + while (count && *sync_p != sync_seq) { + DRM_UDELAY(100); + --count; + } + if ((count == 0) && (*sync_p != sync_seq)) { + DRM_ERROR("TOPAZ: wait sycn timeout (0x%08x),actual 0x%08x\n", + sync_seq, *sync_p); + return -EBUSY; + } + PSB_DEBUG_GENERAL("TOPAZ: SYNC done, seq=0x%08x\n", *sync_p); + + dev_priv->topaz_busy = 0; + + /* XXX: check psb_fence_handler is suitable for topaz */ + dev_priv->topaz_current_sequence = *sync_p; +#if 0 + write_lock_irqsave(&fc->lock, irq_flags); + ttm_fence_handler(fdev, LNC_ENGINE_ENCODE, + dev_priv->topaz_current_sequence, + _PSB_FENCE_TYPE_EXE, 0); + write_unlock_irqrestore(&fc->lock, irq_flags); +#endif +#endif + return 0; +} + +int +lnc_topaz_deliver_command(struct drm_device *dev, + struct ttm_buffer_object *cmd_buffer, + unsigned long cmd_offset, unsigned long cmd_size, + void **topaz_cmd, uint32_t sequence, + int copy_cmd) +{ + unsigned long cmd_page_offset = cmd_offset & ~PAGE_MASK; + struct ttm_bo_kmap_obj cmd_kmap; + bool is_iomem; + int ret; + unsigned char *cmd_start, *tmp; + + ret = ttm_bo_kmap(cmd_buffer, cmd_offset >> PAGE_SHIFT, 2, + &cmd_kmap); + if (ret) { + DRM_ERROR("TOPAZ: drm_bo_kmap failed: %d\n", ret); + return ret; + } + cmd_start = (unsigned char *) ttm_kmap_obj_virtual(&cmd_kmap, + &is_iomem) + cmd_page_offset; + + if (copy_cmd) { + PSB_DEBUG_GENERAL("TOPAZ: queue commands\n"); + tmp = drm_calloc(1, cmd_size, DRM_MEM_DRIVER); + if (tmp == NULL) { + ret = -ENOMEM; + goto out; + } + memcpy(tmp, cmd_start, cmd_size); + *topaz_cmd = tmp; + } else { + PSB_DEBUG_GENERAL("TOPAZ: directly send the command\n"); + ret = lnc_topaz_send(dev, cmd_start, cmd_size, sequence); + if (ret) { + DRM_ERROR("TOPAZ: commit commands failed.\n"); + ret = -EINVAL; + } + } + +out: + PSB_DEBUG_GENERAL("TOPAZ:cmd_size(%ld), sequence(%d) copy_cmd(%d)\n", + cmd_size, sequence, copy_cmd); + + ttm_bo_kunmap(&cmd_kmap); + + return ret; +} + +int +lnc_topaz_send(struct drm_device *dev, void *cmd, + unsigned long cmd_size, uint32_t sync_seq) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + int ret = 0; + unsigned char *command = (unsigned char *) cmd; + struct topaz_cmd_header *cur_cmd_header; + uint32_t cur_cmd_size, cur_cmd_id; + uint32_t codec; + + PSB_DEBUG_GENERAL("TOPAZ: send the command in the buffer one by one\n"); + + while (cmd_size > 0) { + cur_cmd_header = (struct topaz_cmd_header *) command; + cur_cmd_size = cur_cmd_header->size * 4; + cur_cmd_id = cur_cmd_header->id; + + switch (cur_cmd_id) { + case MTX_CMDID_SW_NEW_CODEC: + codec = *((uint32_t *) cmd + 1); + + PSB_DEBUG_GENERAL("TOPAZ: setup new codec %s (%d)\n", + codec_to_string(codec), codec); + if (topaz_setup_fw(dev, codec)) { + DRM_ERROR("TOPAZ: upload FW to HW failed\n"); + return -EBUSY; + } + + dev_priv->topaz_cur_codec = codec; + break; + + case MTX_CMDID_SW_ENTER_LOWPOWER: + PSB_DEBUG_GENERAL("TOPAZ: enter lowpower.... \n"); + PSB_DEBUG_GENERAL("XXX: implement it\n"); + break; + + case MTX_CMDID_SW_LEAVE_LOWPOWER: + PSB_DEBUG_GENERAL("TOPAZ: leave lowpower... \n"); + PSB_DEBUG_GENERAL("XXX: implement it\n"); + break; + + /* ordinary commmand */ + case MTX_CMDID_START_PIC: + /* XXX: specially handle START_PIC hw command */ + CCB_CTRL_SET_QP(dev_priv, + *(command + cur_cmd_size - 4)); + /* strip the QP parameter (it's software arg) */ + cur_cmd_header->size--; + default: + cur_cmd_header->seq = 0x7fff & + dev_priv->topaz_cmd_seq++; + + PSB_DEBUG_GENERAL("TOPAZ: %s: size(%d)," + " seq (0x%04x)\n", + cmd_to_string(cur_cmd_id), + cur_cmd_size, cur_cmd_header->seq); + ret = lnc_mtx_send(dev_priv, command); + if (ret) { + DRM_ERROR("TOPAZ: error -- ret(%d)\n", ret); + goto out; + } + break; + } + + command += cur_cmd_size; + cmd_size -= cur_cmd_size; + } + lnc_topaz_sync(dev, sync_seq); +out: + return ret; +} + +static int lnc_mtx_send(struct drm_psb_private *dev_priv, const void *cmd) +{ + struct topaz_cmd_header *cur_cmd_header = + (struct topaz_cmd_header *) cmd; + uint32_t cmd_size = cur_cmd_header->size; + uint32_t read_index, write_index; + const uint32_t *cmd_pointer = (uint32_t *) cmd; + + int ret = 0; + + /* # enable all clock */ + + write_index = dev_priv->topaz_cmd_windex; + if (write_index + cmd_size + 1 > dev_priv->topaz_ccb_size) { + int free_space = dev_priv->topaz_ccb_size - write_index; + + PSB_DEBUG_GENERAL("TOPAZ: -------will wrap CCB write point.\n"); + if (free_space > 0) { + struct topaz_cmd_header pad_cmd; + + pad_cmd.id = MTX_CMDID_NULL; + pad_cmd.size = free_space; + pad_cmd.seq = 0x7fff & dev_priv->topaz_cmd_seq++; + + PSB_DEBUG_GENERAL("TOPAZ: MTX_CMDID_NULL:" + " size(%d),seq (0x%04x)\n", + pad_cmd.size, pad_cmd.seq); + + TOPAZ_BEGIN_CCB(dev_priv); + TOPAZ_OUT_CCB(dev_priv, pad_cmd.val); + TOPAZ_END_CCB(dev_priv, 1); + } + POLL_WB_RINDEX(dev_priv, 0); + if (ret == 0) + dev_priv->topaz_cmd_windex = 0; + else { + DRM_ERROR("TOPAZ: poll rindex timeout\n"); + return ret; /* HW may hang, need reset */ + } + PSB_DEBUG_GENERAL("TOPAZ: -------wrap CCB was done.\n"); + } + + read_index = CCB_CTRL_RINDEX(dev_priv);/* temperily use CCB CTRL */ + write_index = dev_priv->topaz_cmd_windex; + + PSB_DEBUG_GENERAL("TOPAZ: write index(%d), read index(%d,WB=%d)\n", + write_index, read_index, WB_CCB_CTRL_RINDEX(dev_priv)); + TOPAZ_BEGIN_CCB(dev_priv); + while (cmd_size > 0) { + TOPAZ_OUT_CCB(dev_priv, *cmd_pointer++); + --cmd_size; + } + TOPAZ_END_CCB(dev_priv, 1); + + POLL_WB_RINDEX(dev_priv, dev_priv->topaz_cmd_windex); + +#if 0 + DRM_UDELAY(1000); + lnc_topaz_clearirq(dev, + lnc_topaz_queryirq(dev)); + LNC_TRACEL("TOPAZ: after clear, query again\n"); + lnc_topaz_queryirq(dev_priv); +#endif + + return ret; +} + +int lnc_topaz_dequeue_send(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + struct lnc_topaz_cmd_queue *topaz_cmd = NULL; + int ret; + + PSB_DEBUG_GENERAL("TOPAZ: dequeue command and send it to topaz\n"); + + if (list_empty(&dev_priv->topaz_queue)) { + dev_priv->topaz_busy = 0; + return 0; + } + + topaz_cmd = list_first_entry(&dev_priv->topaz_queue, + struct lnc_topaz_cmd_queue, head); + + PSB_DEBUG_GENERAL("TOPAZ: queue has id %08x\n", topaz_cmd->sequence); + ret = lnc_topaz_send(dev, topaz_cmd->cmd, topaz_cmd->cmd_size, + topaz_cmd->sequence); + if (ret) { + DRM_ERROR("TOPAZ: lnc_topaz_send failed.\n"); + ret = -EINVAL; + } + + list_del(&topaz_cmd->head); + kfree(topaz_cmd->cmd); + drm_free(topaz_cmd, sizeof(struct lnc_topaz_cmd_queue), + DRM_MEM_DRIVER); + + return ret; +} + +void +lnc_topaz_lockup(struct drm_psb_private *dev_priv, + int *topaz_lockup, int *topaz_idle) +{ + unsigned long irq_flags; + uint32_t tmp; + + /* if have printk in this function, you will have plenties here */ + spin_lock_irqsave(&dev_priv->topaz_lock, irq_flags); + *topaz_lockup = 0; + *topaz_idle = 1; + + if (!dev_priv->has_topaz) { + spin_unlock_irqrestore(&dev_priv->topaz_lock, irq_flags); + return; + } + + tmp = dev_priv->topaz_current_sequence + - dev_priv->sequence[LNC_ENGINE_ENCODE]; + if (tmp > 0x0FFFFFFF) { + if (dev_priv->topaz_current_sequence == + dev_priv->topaz_last_sequence) { + *topaz_lockup = 1; + } else { + dev_priv->topaz_last_sequence = + dev_priv->topaz_current_sequence; + *topaz_idle = 0; + } + + if (dev_priv->topaz_start_idle) + dev_priv->topaz_start_idle = 0; + } else { + if (dev_priv->topaz_needs_reset == 0) { + if (dev_priv->topaz_start_idle && + (dev_priv->topaz_finished_sequence + == dev_priv->topaz_current_sequence)) { + if (time_after_eq(jiffies, + dev_priv->topaz_idle_start_jiffies + + TOPAZ_MAX_IDELTIME)) { + + /* XXX: disable clock */ + dev_priv->topaz_needs_reset = 1; + } else + *topaz_idle = 0; + } else { + dev_priv->topaz_start_idle = 1; + dev_priv->topaz_idle_start_jiffies = jiffies; + dev_priv->topaz_finished_sequence = + dev_priv->topaz_current_sequence; + *topaz_idle = 0; + } + } + } + spin_unlock_irqrestore(&dev_priv->topaz_lock, irq_flags); +} + + +void topaz_mtx_kick(struct drm_psb_private *dev_priv, uint32_t kick_count) +{ + PSB_DEBUG_GENERAL("TOPAZ: kick mtx count(%d).\n", kick_count); + MTX_WRITE32(MTX_CR_MTX_KICK, kick_count); +} + +/* power up msvdx, OSPM function */ +int psb_power_up_topaz(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *)dev->dev_private; + + if (dev_priv->topaz_power_state == LNC_TOPAZ_POWERON) + return 0; + + psb_up_island_power(dev, PSB_VIDEO_ENC_ISLAND); + + PSB_DEBUG_GENERAL("FIXME: how to write clock state for topaz?" + " so many clock\n"); + /* PSB_WMSVDX32(dev_priv->topaz_clk_state, MSVDX_MAN_CLK_ENABLE); */ + + PSB_DEBUG_GENERAL("FIXME restore registers or init msvdx\n"); + + PSB_DEBUG_GENERAL("FIXME: flush all mmu\n"); + + dev_priv->topaz_power_state = LNC_TOPAZ_POWERON; + + return 0; +} + +int psb_power_down_topaz(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *)dev->dev_private; + + if (dev_priv->topaz_power_state == LNC_TOPAZ_POWEROFF) + return 0; + + if (dev_priv->topaz_busy) { + PSB_DEBUG_GENERAL("FIXME: MSVDX is busy, should wait it\n"); + return -EBUSY; + } + PSB_DEBUG_GENERAL("FIXME: how to read clock state for topaz?" + " so many clock\n"); + /* dev_priv->topaz_clk_state = PSB_RMSVDX32(MSVDX_MAN_CLK_ENABLE); */ + PSB_DEBUG_GENERAL("FIXME: save MSVDX register\n"); + PSB_DEBUG_GENERAL("FIXME: save MSVDX context\n"); + + psb_down_island_power(dev, PSB_VIDEO_ENC_ISLAND); + + dev_priv->topaz_power_state = LNC_TOPAZ_POWEROFF; + + return 0; +} + +int lnc_prepare_topaz_suspend(struct drm_device *dev) +{ + /* FIXME: need reset when resume? + * Is mtx restore enough for encoder continue run? */ + /* dev_priv->topaz_needs_reset = 1; */ + + /* make sure all IRQs are seviced */ + + /* make sure all the fence is signaled */ + + /* save mtx context into somewhere */ + /* lnc_topaz_save_mtx_state(dev); */ + + return 0; +} + +int lnc_prepare_topaz_resume(struct drm_device *dev) +{ + /* FIXME: need reset when resume? + * Is mtx restore enough for encoder continue run? */ + /* dev_priv->topaz_needs_reset = 1; */ + + /* make sure IRQ is open */ + + /* restore mtx context */ + /* lnc_topaz_restore_mtx_state(dev); */ + + return 0; +} --- /dev/null +++ b/drivers/staging/psb/lnc_topaz.h @@ -0,0 +1,803 @@ +/************************************************************************** + * + * Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA + * Copyright (c) Imagination Technologies Limited, UK + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +#ifndef _LNC_TOPAZ_H_ +#define _LNC_TOPAZ_H_ + +#include "psb_drv.h" + +#define LNC_TOPAZ_NO_IRQ 1 +#define TOPAZ_MTX_REG_SIZE (34 * 4 + 183 * 4) +#define ENABLE_TOPAZ_OSPM_D0IX (0x10) + +/* extern int drm_psb_ospm; */ + +int psb_power_up_topaz(struct drm_device *dev); +int psb_power_down_topaz(struct drm_device *dev); +int lnc_prepare_topaz_suspend(struct drm_device *dev); +int lnc_prepare_topaz_resume(struct drm_device *dev); + +/* + * MACROS to insert values into fields within a word. The basename of the + * field must have MASK_BASENAME and SHIFT_BASENAME constants. + */ +#define MM_WRITE32(base, offset, value) \ +do { \ + *((unsigned long *)((unsigned char *)(dev_priv->topaz_reg) \ + + base + offset)) = value; \ +} while (0) + +#define MM_READ32(base, offset, pointer) \ +do { \ + *(pointer) = *((unsigned long *)((unsigned char *)(dev_priv->topaz_reg)\ + + base + offset)); \ +} while (0) + +#define F_MASK(basename) (MASK_##basename) +#define F_SHIFT(basename) (SHIFT_##basename) + +#define F_ENCODE(val, basename) \ + (((val) << (F_SHIFT(basename))) & (F_MASK(basename))) + +/* MVEA macro */ +#define MVEA_START 0x03000 + +#define MVEA_WRITE32(offset, value) MM_WRITE32(MVEA_START, offset, value) +#define MVEA_READ32(offset, pointer) MM_READ32(MVEA_START, offset, pointer); + +#define F_MASK_MVEA(basename) (MASK_MVEA_##basename) /* MVEA */ +#define F_SHIFT_MVEA(basename) (SHIFT_MVEA_##basename) /* MVEA */ +#define F_ENCODE_MVEA(val, basename) \ + (((val)<<(F_SHIFT_MVEA(basename)))&(F_MASK_MVEA(basename))) + +/* VLC macro */ +#define TOPAZ_VLC_START 0x05000 + +/* TOPAZ macro */ +#define TOPAZ_START 0x02000 + +#define TOPAZ_WRITE32(offset, value) MM_WRITE32(TOPAZ_START, offset, value) +#define TOPAZ_READ32(offset, pointer) MM_READ32(TOPAZ_START, offset, pointer) + +#define F_MASK_TOPAZ(basename) (MASK_TOPAZ_##basename) +#define F_SHIFT_TOPAZ(basename) (SHIFT_TOPAZ_##basename) +#define F_ENCODE_TOPAZ(val,basename) \ + (((val)<<(F_SHIFT_TOPAZ(basename)))&(F_MASK_TOPAZ(basename))) + +/* MTX macro */ +#define MTX_START 0x0 + +#define MTX_WRITE32(offset, value) MM_WRITE32(MTX_START, offset, value) +#define MTX_READ32(offset, pointer) MM_READ32(MTX_START, offset, pointer) + +/* DMAC macro */ +#define DMAC_START 0x0f000 + +#define DMAC_WRITE32(offset, value) MM_WRITE32(DMAC_START, offset, value) +#define DMAC_READ32(offset, pointer) MM_READ32(DMAC_START, offset, pointer) + +#define F_MASK_DMAC(basename) (MASK_DMAC_##basename) +#define F_SHIFT_DMAC(basename) (SHIFT_DMAC_##basename) +#define F_ENCODE_DMAC(val,basename) \ + (((val)<<(F_SHIFT_DMAC(basename)))&(F_MASK_DMAC(basename))) + + +/* Register CR_IMG_TOPAZ_INTENAB */ +#define TOPAZ_CR_IMG_TOPAZ_INTENAB 0x0008 +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTEN_MVEA 0x00000001 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTEN_MVEA 0 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTEN_MVEA 0x0008 + +#define MASK_TOPAZ_CR_IMG_TOPAZ_MAS_INTEN 0x80000000 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_MAS_INTEN 31 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_MAS_INTEN 0x0008 + +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTEN_MMU_FAULT 0x00000008 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTEN_MMU_FAULT 3 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTEN_MMU_FAULT 0x0008 + +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTEN_MTX 0x00000002 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTEN_MTX 1 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTEN_MTX 0x0008 + +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTEN_MTX_HALT 0x00000004 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTEN_MTX_HALT 2 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTEN_MTX_HALT 0x0008 + +#define TOPAZ_CR_IMG_TOPAZ_INTCLEAR 0x000C +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTCLR_MVEA 0x00000001 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTCLR_MVEA 0 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTCLR_MVEA 0x000C + +#define TOPAZ_CR_IMG_TOPAZ_INTSTAT 0x0004 +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTS_MVEA 0x00000001 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTS_MVEA 0 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTS_MVEA 0x0004 + +#define MTX_CCBCTRL_ROFF 0 +#define MTX_CCBCTRL_COMPLETE 4 +#define MTX_CCBCTRL_CCBSIZE 8 +#define MTX_CCBCTRL_QP 12 +#define MTX_CCBCTRL_INITQP 24 + +#define TOPAZ_CR_MMU_STATUS 0x001C +#define MASK_TOPAZ_CR_MMU_PF_N_RW 0x00000001 +#define SHIFT_TOPAZ_CR_MMU_PF_N_RW 0 +#define REGNUM_TOPAZ_CR_MMU_PF_N_RW 0x001C + +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTCLR_MMU_FAULT 0x00000008 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTCLR_MMU_FAULT 3 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTCLR_MMU_FAULT 0x000C + +#define TOPAZ_CR_MMU_MEM_REQ 0x0020 +#define MASK_TOPAZ_CR_MEM_REQ_STAT_READS 0x000000FF +#define SHIFT_TOPAZ_CR_MEM_REQ_STAT_READS 0 +#define REGNUM_TOPAZ_CR_MEM_REQ_STAT_READS 0x0020 + +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX 0x00000002 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX 1 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX 0x000C + +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX_HALT 0x00000004 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX_HALT 2 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX_HALT 0x000C + +#define MTX_CR_MTX_KICK 0x0080 +#define MASK_MTX_MTX_KICK 0x0000FFFF +#define SHIFT_MTX_MTX_KICK 0 +#define REGNUM_MTX_MTX_KICK 0x0080 + +#define MTX_DATA_MEM_BASE 0x82880000 + +#define MTX_CR_MTX_RAM_ACCESS_CONTROL 0x0108 +#define MASK_MTX_MTX_MCMR 0x00000001 +#define SHIFT_MTX_MTX_MCMR 0 +#define REGNUM_MTX_MTX_MCMR 0x0108 + +#define MASK_MTX_MTX_MCMID 0x0FF00000 +#define SHIFT_MTX_MTX_MCMID 20 +#define REGNUM_MTX_MTX_MCMID 0x0108 + +#define MASK_MTX_MTX_MCM_ADDR 0x000FFFFC +#define SHIFT_MTX_MTX_MCM_ADDR 2 +#define REGNUM_MTX_MTX_MCM_ADDR 0x0108 + +#define MTX_CR_MTX_RAM_ACCESS_STATUS 0x010C +#define MASK_MTX_MTX_MTX_MCM_STAT 0x00000001 +#define SHIFT_MTX_MTX_MTX_MCM_STAT 0 +#define REGNUM_MTX_MTX_MTX_MCM_STAT 0x010C + +#define MASK_MTX_MTX_MCMAI 0x00000002 +#define SHIFT_MTX_MTX_MCMAI 1 +#define REGNUM_MTX_MTX_MCMAI 0x0108 + +#define MTX_CR_MTX_RAM_ACCESS_DATA_TRANSFER 0x0104 + +#define MVEA_CR_IMG_MVEA_SRST 0x0000 +#define MASK_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0x00000001 +#define SHIFT_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0 +#define REGNUM_MVEA_CR_IMG_MVEA_SPE_SOFT_RESET 0x0000 + +#define MASK_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 0x00000002 +#define SHIFT_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 1 +#define REGNUM_MVEA_CR_IMG_MVEA_IPE_SOFT_RESET 0x0000 + +#define MASK_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 0x00000004 +#define SHIFT_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 2 +#define REGNUM_MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET 0x0000 + +#define MASK_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 0x00000008 +#define SHIFT_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 3 +#define REGNUM_MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET 0x0000 + +#define MASK_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 0x00000010 +#define SHIFT_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 4 +#define REGNUM_MVEA_CR_IMG_MVEA_CMC_SOFT_RESET 0x0000 + +#define MASK_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 0x00000020 +#define SHIFT_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 5 +#define REGNUM_MVEA_CR_IMG_MVEA_DCF_SOFT_RESET 0x0000 + +#define TOPAZ_CR_IMG_TOPAZ_CORE_ID 0x03C0 +#define TOPAZ_CR_IMG_TOPAZ_CORE_REV 0x03D0 + +#define TOPAZ_MTX_PC (0x00000005) +#define PC_START_ADDRESS (0x80900000) + +#define TOPAZ_CR_TOPAZ_AUTO_CLK_GATE 0x0014 +#define MASK_TOPAZ_CR_TOPAZ_VLC_AUTO_CLK_GATE 0x00000001 +#define SHIFT_TOPAZ_CR_TOPAZ_VLC_AUTO_CLK_GATE 0 +#define REGNUM_TOPAZ_CR_TOPAZ_VLC_AUTO_CLK_GATE 0x0014 + +#define MASK_TOPAZ_CR_TOPAZ_DB_AUTO_CLK_GATE 0x00000002 +#define SHIFT_TOPAZ_CR_TOPAZ_DB_AUTO_CLK_GATE 1 +#define REGNUM_TOPAZ_CR_TOPAZ_DB_AUTO_CLK_GATE 0x0014 + +#define MASK_TOPAZ_CR_TOPAZ_MTX_MAN_CLK_GATE 0x00000002 +#define SHIFT_TOPAZ_CR_TOPAZ_MTX_MAN_CLK_GATE 1 +#define REGNUM_TOPAZ_CR_TOPAZ_MTX_MAN_CLK_GATE 0x0010 + +#define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_DATA_OFFSET 0x000000F8 +#define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_OFFSET 0x000000FC +#define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_MASK 0x00010000 +#define MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK 0x80000000 + +#define TOPAZ_CORE_CR_MTX_DEBUG_OFFSET 0x0000003C + +#define MASK_TOPAZ_CR_MTX_DBG_IS_SLAVE 0x00000004 +#define SHIFT_TOPAZ_CR_MTX_DBG_IS_SLAVE 2 +#define REGNUM_TOPAZ_CR_MTX_DBG_IS_SLAVE 0x003C + +#define MASK_TOPAZ_CR_MTX_DBG_GPIO_OUT 0x00000018 +#define SHIFT_TOPAZ_CR_MTX_DBG_GPIO_OUT 3 +#define REGNUM_TOPAZ_CR_MTX_DBG_GPIO_OUT 0x003C + +#define MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_OFFSET 0x00000108 + +#define TOPAZ_CR_MMU_CONTROL0 0x0024 +#define MASK_TOPAZ_CR_MMU_BYPASS 0x00000800 +#define SHIFT_TOPAZ_CR_MMU_BYPASS 11 +#define REGNUM_TOPAZ_CR_MMU_BYPASS 0x0024 + +#define TOPAZ_CR_MMU_DIR_LIST_BASE(X) (0x0030 + (4 * (X))) +#define MASK_TOPAZ_CR_MMU_DIR_LIST_BASE_ADDR 0xFFFFF000 +#define SHIFT_TOPAZ_CR_MMU_DIR_LIST_BASE_ADDR 12 +#define REGNUM_TOPAZ_CR_MMU_DIR_LIST_BASE_ADDR 0x0030 + +#define MASK_TOPAZ_CR_MMU_INVALDC 0x00000008 +#define SHIFT_TOPAZ_CR_MMU_INVALDC 3 +#define REGNUM_TOPAZ_CR_MMU_INVALDC 0x0024 + +#define MASK_TOPAZ_CR_MMU_FLUSH 0x00000004 +#define SHIFT_TOPAZ_CR_MMU_FLUSH 2 +#define REGNUM_TOPAZ_CR_MMU_FLUSH 0x0024 + +#define TOPAZ_CR_MMU_BANK_INDEX 0x0038 +#define MASK_TOPAZ_CR_MMU_BANK_N_INDEX_M(i) (0x00000003 << (8 + ((i) * 2))) +#define SHIFT_TOPAZ_CR_MMU_BANK_N_INDEX_M(i) (8 + ((i) * 2)) +#define REGNUM_TOPAZ_CR_MMU_BANK_N_INDEX_M(i) 0x0038 + +#define TOPAZ_CR_TOPAZ_MAN_CLK_GATE 0x0010 +#define MASK_TOPAZ_CR_TOPAZ_MVEA_MAN_CLK_GATE 0x00000001 +#define SHIFT_TOPAZ_CR_TOPAZ_MVEA_MAN_CLK_GATE 0 +#define REGNUM_TOPAZ_CR_TOPAZ_MVEA_MAN_CLK_GATE 0x0010 + +#define MTX_CORE_CR_MTX_TXRPT_OFFSET 0x0000000c +#define TXRPT_WAITONKICK_VALUE 0x8ade0000 + +#define MTX_CORE_CR_MTX_ENABLE_MTX_TOFF_MASK 0x00000002 + +#define MTX_CORE_CR_MTX_ENABLE_OFFSET 0x00000000 +#define MTX_CORE_CR_MTX_ENABLE_MTX_ENABLE_MASK 0x00000001 + +#define MASK_TOPAZ_CR_IMG_TOPAZ_INTS_MTX 0x00000002 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_INTS_MTX 1 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_INTS_MTX 0x0004 + +#define MTX_CORE_CR_MTX_SOFT_RESET_OFFSET 0x00000200 +#define MTX_CORE_CR_MTX_SOFT_RESET_MTX_RESET_MASK 0x00000001 + +#define MTX_CR_MTX_SYSC_CDMAA 0x0344 +#define MASK_MTX_CDMAA_ADDRESS 0x03FFFFFC +#define SHIFT_MTX_CDMAA_ADDRESS 2 +#define REGNUM_MTX_CDMAA_ADDRESS 0x0344 + +#define MTX_CR_MTX_SYSC_CDMAC 0x0340 +#define MASK_MTX_LENGTH 0x0000FFFF +#define SHIFT_MTX_LENGTH 0 +#define REGNUM_MTX_LENGTH 0x0340 + +#define MASK_MTX_BURSTSIZE 0x07000000 +#define SHIFT_MTX_BURSTSIZE 24 +#define REGNUM_MTX_BURSTSIZE 0x0340 + +#define MASK_MTX_RNW 0x00020000 +#define SHIFT_MTX_RNW 17 +#define REGNUM_MTX_RNW 0x0340 + +#define MASK_MTX_ENABLE 0x00010000 +#define SHIFT_MTX_ENABLE 16 +#define REGNUM_MTX_ENABLE 0x0340 + +#define MASK_MTX_LENGTH 0x0000FFFF +#define SHIFT_MTX_LENGTH 0 +#define REGNUM_MTX_LENGTH 0x0340 + +#define TOPAZ_CR_IMG_TOPAZ_SRST 0x0000 +#define MASK_TOPAZ_CR_IMG_TOPAZ_MVEA_SOFT_RESET 0x00000001 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_MVEA_SOFT_RESET 0 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_MVEA_SOFT_RESET 0x0000 + +#define MASK_TOPAZ_CR_IMG_TOPAZ_VLC_SOFT_RESET 0x00000008 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_VLC_SOFT_RESET 3 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_VLC_SOFT_RESET 0x0000 + +#define MASK_TOPAZ_CR_IMG_TOPAZ_MTX_SOFT_RESET 0x00000002 +#define SHIFT_TOPAZ_CR_IMG_TOPAZ_MTX_SOFT_RESET 1 +#define REGNUM_TOPAZ_CR_IMG_TOPAZ_MTX_SOFT_RESET 0x0000 + +#define MVEA_CR_MVEA_AUTO_CLOCK_GATING 0x0024 +#define MASK_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0x00000001 +#define SHIFT_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0 +#define REGNUM_MVEA_CR_MVEA_SPE_AUTO_CLK_GATE 0x0024 + +#define MASK_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 0x00000002 +#define SHIFT_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 1 +#define REGNUM_MVEA_CR_MVEA_IPE_AUTO_CLK_GATE 0x0024 + +#define MASK_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 0x00000004 +#define SHIFT_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 2 +#define REGNUM_MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE 0x0024 + +#define MASK_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 0x00000008 +#define SHIFT_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 3 +#define REGNUM_MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE 0x0024 + +#define TOPAZ_CR_IMG_TOPAZ_DMAC_MODE 0x0040 +#define MASK_TOPAZ_CR_DMAC_MASTER_MODE 0x00000001 +#define SHIFT_TOPAZ_CR_DMAC_MASTER_MODE 0 +#define REGNUM_TOPAZ_CR_DMAC_MASTER_MODE 0x0040 + +#define MTX_CR_MTX_SYSC_CDMAT 0x0350 +#define MASK_MTX_TRANSFERDATA 0xFFFFFFFF +#define SHIFT_MTX_TRANSFERDATA 0 +#define REGNUM_MTX_TRANSFERDATA 0x0350 + +#define IMG_SOC_DMAC_IRQ_STAT(X) (0x000C + (32 * (X))) +#define MASK_IMG_SOC_TRANSFER_FIN 0x00020000 +#define SHIFT_IMG_SOC_TRANSFER_FIN 17 +#define REGNUM_IMG_SOC_TRANSFER_FIN 0x000C + +#define IMG_SOC_DMAC_COUNT(X) (0x0004 + (32 * (X))) +#define MASK_IMG_SOC_CNT 0x0000FFFF +#define SHIFT_IMG_SOC_CNT 0 +#define REGNUM_IMG_SOC_CNT 0x0004 + +#define MASK_IMG_SOC_EN 0x00010000 +#define SHIFT_IMG_SOC_EN 16 +#define REGNUM_IMG_SOC_EN 0x0004 + +#define MASK_IMG_SOC_LIST_EN 0x00040000 +#define SHIFT_IMG_SOC_LIST_EN 18 +#define REGNUM_IMG_SOC_LIST_EN 0x0004 + +#define IMG_SOC_DMAC_PER_HOLD(X) (0x0018 + (32 * (X))) +#define MASK_IMG_SOC_PER_HOLD 0x0000007F +#define SHIFT_IMG_SOC_PER_HOLD 0 +#define REGNUM_IMG_SOC_PER_HOLD 0x0018 + +#define IMG_SOC_DMAC_SETUP(X) (0x0000 + (32 * (X))) +#define MASK_IMG_SOC_START_ADDRESS 0xFFFFFFF +#define SHIFT_IMG_SOC_START_ADDRESS 0 +#define REGNUM_IMG_SOC_START_ADDRESS 0x0000 + +#define MASK_IMG_SOC_BSWAP 0x40000000 +#define SHIFT_IMG_SOC_BSWAP 30 +#define REGNUM_IMG_SOC_BSWAP 0x0004 + +#define MASK_IMG_SOC_PW 0x18000000 +#define SHIFT_IMG_SOC_PW 27 +#define REGNUM_IMG_SOC_PW 0x0004 + +#define MASK_IMG_SOC_DIR 0x04000000 +#define SHIFT_IMG_SOC_DIR 26 +#define REGNUM_IMG_SOC_DIR 0x0004 + +#define MASK_IMG_SOC_PI 0x03000000 +#define SHIFT_IMG_SOC_PI 24 +#define REGNUM_IMG_SOC_PI 0x0004 +#define IMG_SOC_PI_1 0x00000002 +#define IMG_SOC_PI_2 0x00000001 +#define IMG_SOC_PI_4 0x00000000 + +#define MASK_IMG_SOC_TRANSFER_IEN 0x20000000 +#define SHIFT_IMG_SOC_TRANSFER_IEN 29 +#define REGNUM_IMG_SOC_TRANSFER_IEN 0x0004 + +#define DMAC_VALUE_COUNT(BSWAP, PW, DIR, PERIPH_INCR, COUNT) \ + ((((BSWAP) << SHIFT_IMG_SOC_BSWAP) & MASK_IMG_SOC_BSWAP)| \ + (((PW) << SHIFT_IMG_SOC_PW) & MASK_IMG_SOC_PW)| \ + (((DIR) << SHIFT_IMG_SOC_DIR) & MASK_IMG_SOC_DIR)| \ + (((PERIPH_INCR) << SHIFT_IMG_SOC_PI) & MASK_IMG_SOC_PI)| \ + (((COUNT) << SHIFT_IMG_SOC_CNT) & MASK_IMG_SOC_CNT)) + +#define IMG_SOC_DMAC_PERIPH(X) (0x0008 + (32 * (X))) +#define MASK_IMG_SOC_EXT_SA 0x0000000F +#define SHIFT_IMG_SOC_EXT_SA 0 +#define REGNUM_IMG_SOC_EXT_SA 0x0008 + +#define MASK_IMG_SOC_ACC_DEL 0xE0000000 +#define SHIFT_IMG_SOC_ACC_DEL 29 +#define REGNUM_IMG_SOC_ACC_DEL 0x0008 + +#define MASK_IMG_SOC_INCR 0x08000000 +#define SHIFT_IMG_SOC_INCR 27 +#define REGNUM_IMG_SOC_INCR 0x0008 + +#define MASK_IMG_SOC_BURST 0x07000000 +#define SHIFT_IMG_SOC_BURST 24 +#define REGNUM_IMG_SOC_BURST 0x0008 + +#define DMAC_VALUE_PERIPH_PARAM(ACC_DEL, INCR, BURST) \ +((((ACC_DEL) << SHIFT_IMG_SOC_ACC_DEL) & MASK_IMG_SOC_ACC_DEL)| \ +(((INCR) << SHIFT_IMG_SOC_INCR) & MASK_IMG_SOC_INCR)| \ +(((BURST) << SHIFT_IMG_SOC_BURST) & MASK_IMG_SOC_BURST)) + +#define IMG_SOC_DMAC_PERIPHERAL_ADDR(X) (0x0014 + (32 * (X))) +#define MASK_IMG_SOC_ADDR 0x007FFFFF +#define SHIFT_IMG_SOC_ADDR 0 +#define REGNUM_IMG_SOC_ADDR 0x0014 + +/* **************** DMAC define **************** */ +enum DMAC_eBSwap { + DMAC_BSWAP_NO_SWAP = 0x0,/* !< No byte swapping will be performed. */ + DMAC_BSWAP_REVERSE = 0x1,/* !< Byte order will be reversed. */ +}; + +enum DMAC_ePW { + DMAC_PWIDTH_32_BIT = 0x0,/* !< Peripheral width 32-bit. */ + DMAC_PWIDTH_16_BIT = 0x1,/* !< Peripheral width 16-bit. */ + DMAC_PWIDTH_8_BIT = 0x2,/* !< Peripheral width 8-bit. */ +}; + +enum DMAC_eAccDel { + DMAC_ACC_DEL_0 = 0x0, /* !< Access delay zero clock cycles */ + DMAC_ACC_DEL_256 = 0x1, /* !< Access delay 256 clock cycles */ + DMAC_ACC_DEL_512 = 0x2, /* !< Access delay 512 clock cycles */ + DMAC_ACC_DEL_768 = 0x3, /* !< Access delay 768 clock cycles */ + DMAC_ACC_DEL_1024 = 0x4,/* !< Access delay 1024 clock cycles */ + DMAC_ACC_DEL_1280 = 0x5,/* !< Access delay 1280 clock cycles */ + DMAC_ACC_DEL_1536 = 0x6,/* !< Access delay 1536 clock cycles */ + DMAC_ACC_DEL_1792 = 0x7,/* !< Access delay 1792 clock cycles */ +}; + +enum DMAC_eBurst { + DMAC_BURST_0 = 0x0, /* !< burst size of 0 */ + DMAC_BURST_1 = 0x1, /* !< burst size of 1 */ + DMAC_BURST_2 = 0x2, /* !< burst size of 2 */ + DMAC_BURST_3 = 0x3, /* !< burst size of 3 */ + DMAC_BURST_4 = 0x4, /* !< burst size of 4 */ + DMAC_BURST_5 = 0x5, /* !< burst size of 5 */ + DMAC_BURST_6 = 0x6, /* !< burst size of 6 */ + DMAC_BURST_7 = 0x7, /* !< burst size of 7 */ +}; + +/* commands for topaz,shared with user space driver */ +enum drm_lnc_topaz_cmd { + MTX_CMDID_NULL = 0, + MTX_CMDID_DO_HEADER = 1, + MTX_CMDID_ENCODE_SLICE = 2, + MTX_CMDID_WRITEREG = 3, + MTX_CMDID_START_PIC = 4, + MTX_CMDID_END_PIC = 5, + MTX_CMDID_SYNC = 6, + MTX_CMDID_ENCODE_ONE_ROW = 7, + MTX_CMDID_FLUSH = 8, + MTX_CMDID_SW_LEAVE_LOWPOWER = 0xfc, + MTX_CMDID_SW_ENTER_LOWPOWER = 0xfe, + MTX_CMDID_SW_NEW_CODEC = 0xff +}; + +/* codecs topaz supports,shared with user space driver */ +enum drm_lnc_topaz_codec { + IMG_CODEC_JPEG = 0, + IMG_CODEC_H264_NO_RC, + IMG_CODEC_H264_VBR, + IMG_CODEC_H264_CBR, + IMG_CODEC_H263_NO_RC, + IMG_CODEC_H263_VBR, + IMG_CODEC_H263_CBR, + IMG_CODEC_MPEG4_NO_RC, + IMG_CODEC_MPEG4_VBR, + IMG_CODEC_MPEG4_CBR, + IMG_CODEC_NUM +}; + +/* XXX: it's a copy of msvdx cmd queue. should have some change? */ +struct lnc_topaz_cmd_queue { + struct list_head head; + void *cmd; + unsigned long cmd_size; + uint32_t sequence; +}; + + +struct topaz_cmd_header { + union { + struct { + unsigned long id:8; + unsigned long size:8; + unsigned long seq:16; + }; + uint32_t val; + }; +}; + +/* external function declare */ +/* lnc_topazinit.c */ +int lnc_topaz_init(struct drm_device *dev); +int lnc_topaz_uninit(struct drm_device *dev); +int lnc_topaz_reset(struct drm_psb_private *dev_priv); +int topaz_init_fw(struct drm_device *dev); +int topaz_setup_fw(struct drm_device *dev, enum drm_lnc_topaz_codec codec); +int topaz_wait_for_register(struct drm_psb_private *dev_priv, + uint32_t addr, uint32_t value, + uint32_t enable); +void topaz_write_mtx_mem(struct drm_psb_private *dev_priv, + uint32_t byte_addr, uint32_t val); +uint32_t topaz_read_mtx_mem(struct drm_psb_private *dev_priv, + uint32_t byte_addr); +void topaz_write_mtx_mem_multiple_setup(struct drm_psb_private *dev_priv, + uint32_t addr); +void topaz_write_mtx_mem_multiple(struct drm_psb_private *dev_priv, + uint32_t val); +void topaz_mmu_flushcache(struct drm_psb_private *dev_priv); +int lnc_topaz_save_mtx_state(struct drm_device *dev); +int lnc_topaz_restore_mtx_state(struct drm_device *dev); + +/* lnc_topaz.c */ +void lnc_topaz_interrupt(struct drm_device *dev, uint32_t topaz_stat); + +int lnc_cmdbuf_video(struct drm_file *priv, + struct list_head *validate_list, + uint32_t fence_type, + struct drm_psb_cmdbuf_arg *arg, + struct ttm_buffer_object *cmd_buffer, + struct psb_ttm_fence_rep *fence_arg); + +void lnc_topaz_flush_cmd_queue(struct drm_device *dev); +void lnc_topaz_lockup(struct drm_psb_private *dev_priv, int *topaz_lockup, + int *topaz_idle); +void topaz_mtx_kick(struct drm_psb_private *dev_priv, uint32_t kick_cout); + +uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver); + +/* macros to get/set CCB control data */ +#define WB_CCB_CTRL_RINDEX(dev_priv) (*((uint32_t *)dev_priv->topaz_ccb_wb)) +#define WB_CCB_CTRL_SEQ(dev_priv) (*((uint32_t *)dev_priv->topaz_ccb_wb+1)) + +#define POLL_WB_RINDEX(dev_priv,value) \ +do { \ + int i; \ + for (i = 0; i < 10000; i++) { \ + if (WB_CCB_CTRL_RINDEX(dev_priv) == value) \ + break; \ + else \ + DRM_UDELAY(100); \ + } \ + if (WB_CCB_CTRL_RINDEX(dev_priv) != value) { \ + DRM_ERROR("TOPAZ: poll rindex timeout\n"); \ + ret = -EBUSY; \ + } \ +} while (0) + +#define POLL_WB_SEQ(dev_priv,value) \ +do { \ + int i; \ + for (i = 0; i < 10000; i++) { \ + if (WB_CCB_CTRL_SEQ(dev_priv) == value) \ + break; \ + else \ + DRM_UDELAY(1000); \ + } \ + if (WB_CCB_CTRL_SEQ(dev_priv) != value) { \ + DRM_ERROR("TOPAZ:poll mtxseq timeout,0x%04x(mtx) vs 0x%04x\n",\ + WB_CCB_CTRL_SEQ(dev_priv), value); \ + ret = -EBUSY; \ + } \ +} while (0) + +#define CCB_CTRL_RINDEX(dev_priv) \ + topaz_read_mtx_mem(dev_priv, \ + dev_priv->topaz_ccb_ctrl_addr + MTX_CCBCTRL_ROFF) + +#define CCB_CTRL_RINDEX(dev_priv) \ + topaz_read_mtx_mem(dev_priv, \ + dev_priv->topaz_ccb_ctrl_addr + MTX_CCBCTRL_ROFF) + +#define CCB_CTRL_QP(dev_priv) \ + topaz_read_mtx_mem(dev_priv, \ + dev_priv->topaz_ccb_ctrl_addr + MTX_CCBCTRL_QP) + +#define CCB_CTRL_SEQ(dev_priv) \ + topaz_read_mtx_mem(dev_priv, \ + dev_priv->topaz_ccb_ctrl_addr + MTX_CCBCTRL_COMPLETE) + +#define CCB_CTRL_FRAMESKIP(dev_priv) \ + topaz_read_mtx_mem(dev_priv, \ + dev_priv->topaz_ccb_ctrl_addr + MTX_CCBCTRL_FRAMESKIP) + +#define CCB_CTRL_SET_QP(dev_priv, qp) \ + topaz_write_mtx_mem(dev_priv, \ + dev_priv->topaz_ccb_ctrl_addr + MTX_CCBCTRL_QP, qp) + +#define CCB_CTRL_SET_INITIALQP(dev_priv, qp) \ + topaz_write_mtx_mem(dev_priv, \ + dev_priv->topaz_ccb_ctrl_addr + MTX_CCBCTRL_INITQP, qp) + + +#define TOPAZ_BEGIN_CCB(dev_priv) \ + topaz_write_mtx_mem_multiple_setup(dev_priv, \ + dev_priv->topaz_ccb_buffer_addr + \ + dev_priv->topaz_cmd_windex * 4) + +#define TOPAZ_OUT_CCB(dev_priv, cmd) \ +do { \ + topaz_write_mtx_mem_multiple(dev_priv, cmd); \ + dev_priv->topaz_cmd_windex++; \ +} while (0) + +#define TOPAZ_END_CCB(dev_priv,kick_count) \ + topaz_mtx_kick(dev_priv, 1); + +static inline char *cmd_to_string(int cmd_id) +{ + switch (cmd_id) { + case MTX_CMDID_START_PIC: + return "MTX_CMDID_START_PIC"; + case MTX_CMDID_END_PIC: + return "MTX_CMDID_END_PIC"; + case MTX_CMDID_DO_HEADER: + return "MTX_CMDID_DO_HEADER"; + case MTX_CMDID_ENCODE_SLICE: + return "MTX_CMDID_ENCODE_SLICE"; + case MTX_CMDID_SYNC: + return "MTX_CMDID_SYNC"; + + default: + return "Undefined command"; + + } +} + +static inline char *codec_to_string(int codec) +{ + switch (codec) { + case IMG_CODEC_H264_NO_RC: + return "H264_NO_RC"; + case IMG_CODEC_H264_VBR: + return "H264_VBR"; + case IMG_CODEC_H264_CBR: + return "H264_CBR"; + case IMG_CODEC_H263_NO_RC: + return "H263_NO_RC"; + case IMG_CODEC_H263_VBR: + return "H263_VBR"; + case IMG_CODEC_H263_CBR: + return "H263_CBR"; + case IMG_CODEC_MPEG4_NO_RC: + return "MPEG4_NO_RC"; + case IMG_CODEC_MPEG4_VBR: + return "MPEG4_VBR"; + case IMG_CODEC_MPEG4_CBR: + return "MPEG4_CBR"; + default: + return "Undefined codec"; + } +} + +static inline void lnc_topaz_enableirq(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + uint32_t ier = dev_priv->vdc_irq_mask | _LNC_IRQ_TOPAZ_FLAG; + + PSB_DEBUG_IRQ("TOPAZ: enable IRQ\n"); + + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_INTENAB, + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_MAS_INTEN) | + /* F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTEN_MVEA) | */ + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTEN_MMU_FAULT) | + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTEN_MTX) | + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTEN_MTX_HALT)); + + PSB_WVDC32(ier, PSB_INT_ENABLE_R); /* essential */ +} + +static inline void lnc_topaz_disableirq(struct drm_device *dev) +{ + + struct drm_psb_private *dev_priv = dev->dev_private; + uint32_t ier = dev_priv->vdc_irq_mask & (~_LNC_IRQ_TOPAZ_FLAG); + + PSB_DEBUG_INIT("TOPAZ: disable IRQ\n"); + + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_INTENAB, 0); + PSB_WVDC32(ier, PSB_INT_ENABLE_R); /* essential */ +} + +static inline void lnc_topaz_clearirq(struct drm_device *dev, + uint32_t clear_topaz) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + + PSB_DEBUG_INIT("TOPAZ: clear IRQ\n"); + if (clear_topaz != 0) + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_INTCLEAR, clear_topaz); + + PSB_WVDC32(_LNC_IRQ_TOPAZ_FLAG, PSB_INT_IDENTITY_R); +} + +static inline uint32_t lnc_topaz_queryirq(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + uint32_t val, iir, clear = 0; + + TOPAZ_READ32(TOPAZ_CR_IMG_TOPAZ_INTSTAT, &val); + iir = PSB_RVDC32(PSB_INT_IDENTITY_R); + + if ((val == 0) && (iir == 0)) {/* no interrupt */ + PSB_DEBUG_GENERAL("TOPAZ: no interrupt,IIR=TOPAZ_INTSTAT=0\n"); + return 0; + } + + PSB_DEBUG_IRQ("TOPAZ:TOPAZ_INTSTAT=0x%08x,IIR=0%08x\n", val, iir); + + if (val & (1<<31)) + PSB_DEBUG_IRQ("TOPAZ:IRQ pin activated,cmd seq=0x%04x," + "sync seq: 0x%08x vs 0x%08x (MTX)\n", + CCB_CTRL_SEQ(dev_priv), + dev_priv->sequence[LNC_ENGINE_ENCODE], + *(uint32_t *)dev_priv->topaz_sync_addr); + else + PSB_DEBUG_IRQ("TOPAZ:IRQ pin not activated,cmd seq=0x%04x," + "sync seq: 0x%08x vs 0x%08x (MTX)\n", + CCB_CTRL_SEQ(dev_priv), + dev_priv->sequence[LNC_ENGINE_ENCODE], + *(uint32_t *)dev_priv->topaz_sync_addr); + + if (val & 0x8) { + uint32_t mmu_status, mmu_req; + + TOPAZ_READ32(TOPAZ_CR_MMU_STATUS, &mmu_status); + TOPAZ_READ32(TOPAZ_CR_MMU_MEM_REQ, &mmu_req); + + PSB_DEBUG_IRQ("TOPAZ: detect a page fault interrupt, " + "address=0x%08x,mem req=0x%08x\n", + mmu_status, mmu_req); + clear |= F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MMU_FAULT); + } + + if (val & 0x4) { + PSB_DEBUG_IRQ("TOPAZ: detect a MTX_HALT interrupt\n"); + clear |= F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX_HALT); + } + + if (val & 0x2) { + PSB_DEBUG_IRQ("TOPAZ: detect a MTX interrupt\n"); + clear |= F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX); + } + + if (val & 0x1) { + PSB_DEBUG_IRQ("TOPAZ: detect a MVEA interrupt\n"); + clear |= F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MVEA); + } + + return clear; +} + +#endif /* _LNC_TOPAZ_H_ */ --- /dev/null +++ b/drivers/staging/psb/lnc_topazinit.c @@ -0,0 +1,1896 @@ +/** + * file lnc_topazinit.c + * TOPAZ initialization and mtx-firmware upload + * + */ + +/************************************************************************** + * + * Copyright (c) 2007 Intel Corporation, Hillsboro, OR, USA + * Copyright (c) Imagination Technologies Limited, UK + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +/* NOTE: (READ BEFORE REFINE CODE) + * 1. The FIRMWARE's SIZE is measured by byte, we have to pass the size + * measured by word to DMAC. + * + * + * + */ + +/* include headers */ + +/* #define DRM_DEBUG_CODE 2 */ + +#include + +#include +#include + +#include "psb_drv.h" +#include "lnc_topaz.h" + +/* WARNING: this define is very important */ +#define RAM_SIZE (1024 * 24) + +static int drm_psb_ospmxxx = 0x10; + +/* register default values + * THIS HEADER IS ONLY INCLUDE ONCE*/ +static unsigned long topaz_default_regs[183][3] = { + {MVEA_START, 0x00000000, 0x00000000}, + {MVEA_START, 0x00000004, 0x00000400}, + {MVEA_START, 0x00000008, 0x00000000}, + {MVEA_START, 0x0000000C, 0x00000000}, + {MVEA_START, 0x00000010, 0x00000000}, + {MVEA_START, 0x00000014, 0x00000000}, + {MVEA_START, 0x00000018, 0x00000000}, + {MVEA_START, 0x0000001C, 0x00000000}, + {MVEA_START, 0x00000020, 0x00000120}, + {MVEA_START, 0x00000024, 0x00000000}, + {MVEA_START, 0x00000028, 0x00000000}, + {MVEA_START, 0x00000100, 0x00000000}, + {MVEA_START, 0x00000104, 0x00000000}, + {MVEA_START, 0x00000108, 0x00000000}, + {MVEA_START, 0x0000010C, 0x00000000}, + {MVEA_START, 0x0000011C, 0x00000001}, + {MVEA_START, 0x0000012C, 0x00000000}, + {MVEA_START, 0x00000180, 0x00000000}, + {MVEA_START, 0x00000184, 0x00000000}, + {MVEA_START, 0x00000188, 0x00000000}, + {MVEA_START, 0x0000018C, 0x00000000}, + {MVEA_START, 0x00000190, 0x00000000}, + {MVEA_START, 0x00000194, 0x00000000}, + {MVEA_START, 0x00000198, 0x00000000}, + {MVEA_START, 0x0000019C, 0x00000000}, + {MVEA_START, 0x000001A0, 0x00000000}, + {MVEA_START, 0x000001A4, 0x00000000}, + {MVEA_START, 0x000001A8, 0x00000000}, + {MVEA_START, 0x000001AC, 0x00000000}, + {MVEA_START, 0x000001B0, 0x00000000}, + {MVEA_START, 0x000001B4, 0x00000000}, + {MVEA_START, 0x000001B8, 0x00000000}, + {MVEA_START, 0x000001BC, 0x00000000}, + {MVEA_START, 0x000001F8, 0x00000000}, + {MVEA_START, 0x000001FC, 0x00000000}, + {MVEA_START, 0x00000200, 0x00000000}, + {MVEA_START, 0x00000204, 0x00000000}, + {MVEA_START, 0x00000208, 0x00000000}, + {MVEA_START, 0x0000020C, 0x00000000}, + {MVEA_START, 0x00000210, 0x00000000}, + {MVEA_START, 0x00000220, 0x00000001}, + {MVEA_START, 0x00000224, 0x0000001F}, + {MVEA_START, 0x00000228, 0x00000100}, + {MVEA_START, 0x0000022C, 0x00001F00}, + {MVEA_START, 0x00000230, 0x00000101}, + {MVEA_START, 0x00000234, 0x00001F1F}, + {MVEA_START, 0x00000238, 0x00001F01}, + {MVEA_START, 0x0000023C, 0x0000011F}, + {MVEA_START, 0x00000240, 0x00000200}, + {MVEA_START, 0x00000244, 0x00001E00}, + {MVEA_START, 0x00000248, 0x00000002}, + {MVEA_START, 0x0000024C, 0x0000001E}, + {MVEA_START, 0x00000250, 0x00000003}, + {MVEA_START, 0x00000254, 0x0000001D}, + {MVEA_START, 0x00000258, 0x00001F02}, + {MVEA_START, 0x0000025C, 0x00000102}, + {MVEA_START, 0x00000260, 0x0000011E}, + {MVEA_START, 0x00000264, 0x00000000}, + {MVEA_START, 0x00000268, 0x00000000}, + {MVEA_START, 0x0000026C, 0x00000000}, + {MVEA_START, 0x00000270, 0x00000000}, + {MVEA_START, 0x00000274, 0x00000000}, + {MVEA_START, 0x00000278, 0x00000000}, + {MVEA_START, 0x00000280, 0x00008000}, + {MVEA_START, 0x00000284, 0x00000000}, + {MVEA_START, 0x00000288, 0x00000000}, + {MVEA_START, 0x0000028C, 0x00000000}, + {MVEA_START, 0x00000314, 0x00000000}, + {MVEA_START, 0x00000318, 0x00000000}, + {MVEA_START, 0x0000031C, 0x00000000}, + {MVEA_START, 0x00000320, 0x00000000}, + {MVEA_START, 0x00000324, 0x00000000}, + {MVEA_START, 0x00000348, 0x00000000}, + {MVEA_START, 0x00000380, 0x00000000}, + {MVEA_START, 0x00000384, 0x00000000}, + {MVEA_START, 0x00000388, 0x00000000}, + {MVEA_START, 0x0000038C, 0x00000000}, + {MVEA_START, 0x00000390, 0x00000000}, + {MVEA_START, 0x00000394, 0x00000000}, + {MVEA_START, 0x00000398, 0x00000000}, + {MVEA_START, 0x0000039C, 0x00000000}, + {MVEA_START, 0x000003A0, 0x00000000}, + {MVEA_START, 0x000003A4, 0x00000000}, + {MVEA_START, 0x000003A8, 0x00000000}, + {MVEA_START, 0x000003B0, 0x00000000}, + {MVEA_START, 0x000003B4, 0x00000000}, + {MVEA_START, 0x000003B8, 0x00000000}, + {MVEA_START, 0x000003BC, 0x00000000}, + {MVEA_START, 0x000003D4, 0x00000000}, + {MVEA_START, 0x000003D8, 0x00000000}, + {MVEA_START, 0x000003DC, 0x00000000}, + {MVEA_START, 0x000003E0, 0x00000000}, + {MVEA_START, 0x000003E4, 0x00000000}, + {MVEA_START, 0x000003EC, 0x00000000}, + {MVEA_START, 0x000002D0, 0x00000000}, + {MVEA_START, 0x000002D4, 0x00000000}, + {MVEA_START, 0x000002D8, 0x00000000}, + {MVEA_START, 0x000002DC, 0x00000000}, + {MVEA_START, 0x000002E0, 0x00000000}, + {MVEA_START, 0x000002E4, 0x00000000}, + {MVEA_START, 0x000002E8, 0x00000000}, + {MVEA_START, 0x000002EC, 0x00000000}, + {MVEA_START, 0x000002F0, 0x00000000}, + {MVEA_START, 0x000002F4, 0x00000000}, + {MVEA_START, 0x000002F8, 0x00000000}, + {MVEA_START, 0x000002FC, 0x00000000}, + {MVEA_START, 0x00000300, 0x00000000}, + {MVEA_START, 0x00000304, 0x00000000}, + {MVEA_START, 0x00000308, 0x00000000}, + {MVEA_START, 0x0000030C, 0x00000000}, + {MVEA_START, 0x00000290, 0x00000000}, + {MVEA_START, 0x00000294, 0x00000000}, + {MVEA_START, 0x00000298, 0x00000000}, + {MVEA_START, 0x0000029C, 0x00000000}, + {MVEA_START, 0x000002A0, 0x00000000}, + {MVEA_START, 0x000002A4, 0x00000000}, + {MVEA_START, 0x000002A8, 0x00000000}, + {MVEA_START, 0x000002AC, 0x00000000}, + {MVEA_START, 0x000002B0, 0x00000000}, + {MVEA_START, 0x000002B4, 0x00000000}, + {MVEA_START, 0x000002B8, 0x00000000}, + {MVEA_START, 0x000002BC, 0x00000000}, + {MVEA_START, 0x000002C0, 0x00000000}, + {MVEA_START, 0x000002C4, 0x00000000}, + {MVEA_START, 0x000002C8, 0x00000000}, + {MVEA_START, 0x000002CC, 0x00000000}, + {MVEA_START, 0x00000080, 0x00000000}, + {MVEA_START, 0x00000084, 0x80705700}, + {MVEA_START, 0x00000088, 0x00000000}, + {MVEA_START, 0x0000008C, 0x00000000}, + {MVEA_START, 0x00000090, 0x00000000}, + {MVEA_START, 0x00000094, 0x00000000}, + {MVEA_START, 0x00000098, 0x00000000}, + {MVEA_START, 0x0000009C, 0x00000000}, + {MVEA_START, 0x000000A0, 0x00000000}, + {MVEA_START, 0x000000A4, 0x00000000}, + {MVEA_START, 0x000000A8, 0x00000000}, + {MVEA_START, 0x000000AC, 0x00000000}, + {MVEA_START, 0x000000B0, 0x00000000}, + {MVEA_START, 0x000000B4, 0x00000000}, + {MVEA_START, 0x000000B8, 0x00000000}, + {MVEA_START, 0x000000BC, 0x00000000}, + {MVEA_START, 0x000000C0, 0x00000000}, + {MVEA_START, 0x000000C4, 0x00000000}, + {MVEA_START, 0x000000C8, 0x00000000}, + {MVEA_START, 0x000000CC, 0x00000000}, + {MVEA_START, 0x000000D0, 0x00000000}, + {MVEA_START, 0x000000D4, 0x00000000}, + {MVEA_START, 0x000000D8, 0x00000000}, + {MVEA_START, 0x000000DC, 0x00000000}, + {MVEA_START, 0x000000E0, 0x00000000}, + {MVEA_START, 0x000000E4, 0x00000000}, + {MVEA_START, 0x000000E8, 0x00000000}, + {MVEA_START, 0x000000EC, 0x00000000}, + {MVEA_START, 0x000000F0, 0x00000000}, + {MVEA_START, 0x000000F4, 0x00000000}, + {MVEA_START, 0x000000F8, 0x00000000}, + {MVEA_START, 0x000000FC, 0x00000000}, + {TOPAZ_VLC_START, 0x00000000, 0x00000000}, + {TOPAZ_VLC_START, 0x00000004, 0x00000000}, + {TOPAZ_VLC_START, 0x00000008, 0x00000000}, + {TOPAZ_VLC_START, 0x0000000C, 0x00000000}, + {TOPAZ_VLC_START, 0x00000010, 0x00000000}, + {TOPAZ_VLC_START, 0x00000014, 0x00000000}, + {TOPAZ_VLC_START, 0x0000001C, 0x00000000}, + {TOPAZ_VLC_START, 0x00000020, 0x00000000}, + {TOPAZ_VLC_START, 0x00000024, 0x00000000}, + {TOPAZ_VLC_START, 0x0000002C, 0x00000000}, + {TOPAZ_VLC_START, 0x00000034, 0x00000000}, + {TOPAZ_VLC_START, 0x00000038, 0x00000000}, + {TOPAZ_VLC_START, 0x0000003C, 0x00000000}, + {TOPAZ_VLC_START, 0x00000040, 0x00000000}, + {TOPAZ_VLC_START, 0x00000044, 0x00000000}, + {TOPAZ_VLC_START, 0x00000048, 0x00000000}, + {TOPAZ_VLC_START, 0x0000004C, 0x00000000}, + {TOPAZ_VLC_START, 0x00000050, 0x00000000}, + {TOPAZ_VLC_START, 0x00000054, 0x00000000}, + {TOPAZ_VLC_START, 0x00000058, 0x00000000}, + {TOPAZ_VLC_START, 0x0000005C, 0x00000000}, + {TOPAZ_VLC_START, 0x00000060, 0x00000000}, + {TOPAZ_VLC_START, 0x00000064, 0x00000000}, + {TOPAZ_VLC_START, 0x00000068, 0x00000000}, + {TOPAZ_VLC_START, 0x0000006C, 0x00000000} +}; + +#define FIRMWARE_NAME "topaz_fw.bin" + +/* define structure */ +/* firmware file's info head */ +struct topaz_fwinfo { + unsigned int ver:16; + unsigned int codec:16; + + unsigned int text_size; + unsigned int data_size; + unsigned int data_location; +}; + +/* firmware data array define */ +struct topaz_codec_fw { + uint32_t ver; + uint32_t codec; + + uint32_t text_size; + uint32_t data_size; + uint32_t data_location; + + struct ttm_buffer_object *text; + struct ttm_buffer_object *data; +}; + + + +/* static function define */ +static int topaz_upload_fw(struct drm_device *dev, + enum drm_lnc_topaz_codec codec); +static inline void topaz_set_default_regs(struct drm_psb_private + *dev_priv); + +#define UPLOAD_FW_BY_DMA 1 + +#if UPLOAD_FW_BY_DMA +static void topaz_dma_transfer(struct drm_psb_private *dev_priv, + uint32_t channel, uint32_t src_phy_addr, + uint32_t offset, uint32_t dst_addr, + uint32_t byte_num, uint32_t is_increment, + uint32_t is_write); +#else +static void topaz_mtx_upload_by_register(struct drm_device *dev, + uint32_t mtx_mem, uint32_t addr, + uint32_t size, + struct ttm_buffer_object *buf); +#endif + +static void topaz_write_core_reg(struct drm_psb_private *dev_priv, + uint32_t reg, const uint32_t val); +static void topaz_read_core_reg(struct drm_psb_private *dev_priv, + uint32_t reg, uint32_t *ret_val); +static void get_mtx_control_from_dash(struct drm_psb_private *dev_priv); +static void release_mtx_control_from_dash(struct drm_psb_private + *dev_priv); +static void topaz_mmu_hwsetup(struct drm_psb_private *dev_priv); +static void mtx_dma_read(struct drm_device *dev, uint32_t source_addr, + uint32_t size); +static void mtx_dma_write(struct drm_device *dev); + + +#if 0 /* DEBUG_FUNCTION */ +static int topaz_test_null(struct drm_device *dev, uint32_t seq); +static void topaz_mmu_flush(struct drm_device *dev); +static void topaz_mmu_test(struct drm_device *dev, uint32_t sync_value); +#endif +#if 0 +static void topaz_save_default_regs(struct drm_psb_private *dev_priv, + uint32_t *data); +static void topaz_restore_default_regs(struct drm_psb_private *dev_priv, + uint32_t *data); +#endif + +/* globale variable define */ +struct topaz_codec_fw topaz_fw[IMG_CODEC_NUM]; + +uint32_t topaz_read_mtx_mem(struct drm_psb_private *dev_priv, + uint32_t byte_addr) +{ + uint32_t read_val; + uint32_t reg, bank_size, ram_bank_size, ram_id; + + TOPAZ_READ32(0x3c, ®); + reg = 0x0a0a0606; + bank_size = (reg & 0xF0000) >> 16; + + ram_bank_size = (uint32_t) (1 << (bank_size + 2)); + ram_id = (byte_addr - MTX_DATA_MEM_BASE) / ram_bank_size; + + MTX_WRITE32(MTX_CR_MTX_RAM_ACCESS_CONTROL, + F_ENCODE(0x18 + ram_id, MTX_MTX_MCMID) | + F_ENCODE(byte_addr >> 2, MTX_MTX_MCM_ADDR) | + F_ENCODE(1, MTX_MTX_MCMR)); + + /* ?? poll this reg? */ + topaz_wait_for_register(dev_priv, + MTX_START + MTX_CR_MTX_RAM_ACCESS_STATUS, + 1, 1); + + MTX_READ32(MTX_CR_MTX_RAM_ACCESS_DATA_TRANSFER, &read_val); + + return read_val; +} + +void topaz_write_mtx_mem(struct drm_psb_private *dev_priv, + uint32_t byte_addr, uint32_t val) +{ + uint32_t ram_id = 0; + uint32_t reg, bank_size, ram_bank_size; + + TOPAZ_READ32(0x3c, ®); + + /* PSB_DEBUG_GENERAL ("TOPAZ: DEBUG REG(%x)\n", reg); */ + reg = 0x0a0a0606; + + bank_size = (reg & 0xF0000) >> 16; + + ram_bank_size = (uint32_t) (1 << (bank_size + 2)); + ram_id = (byte_addr - MTX_DATA_MEM_BASE) / ram_bank_size; + + MTX_WRITE32(MTX_CR_MTX_RAM_ACCESS_CONTROL, + F_ENCODE(0x18 + ram_id, MTX_MTX_MCMID) | + F_ENCODE(byte_addr >> 2, MTX_MTX_MCM_ADDR)); + + MTX_WRITE32(MTX_CR_MTX_RAM_ACCESS_DATA_TRANSFER, val); + + /* ?? poll this reg? */ + topaz_wait_for_register(dev_priv, + MTX_START + MTX_CR_MTX_RAM_ACCESS_STATUS, + 1, 1); + + return; +} + +void topaz_write_mtx_mem_multiple_setup(struct drm_psb_private *dev_priv, + uint32_t byte_addr) +{ + uint32_t ram_id = 0; + uint32_t reg, bank_size, ram_bank_size; + + TOPAZ_READ32(0x3c, ®); + + reg = 0x0a0a0606; + + bank_size = (reg & 0xF0000) >> 16; + + ram_bank_size = (uint32_t) (1 << (bank_size + 2)); + ram_id = (byte_addr - MTX_DATA_MEM_BASE) / ram_bank_size; + + MTX_WRITE32(MTX_CR_MTX_RAM_ACCESS_CONTROL, + F_ENCODE(0x18 + ram_id, MTX_MTX_MCMID) | + F_ENCODE(1, MTX_MTX_MCMAI) | + F_ENCODE(byte_addr >> 2, MTX_MTX_MCM_ADDR)); +} + +void topaz_write_mtx_mem_multiple(struct drm_psb_private *dev_priv, + uint32_t val) +{ + MTX_WRITE32(MTX_CR_MTX_RAM_ACCESS_DATA_TRANSFER, val); +} + + +int topaz_wait_for_register(struct drm_psb_private *dev_priv, + uint32_t addr, uint32_t value, uint32_t mask) +{ + uint32_t tmp; + uint32_t count = 10000; + + /* # poll topaz register for certain times */ + while (count) { + /* #.# read */ + MM_READ32(addr, 0, &tmp); + + if (value == (tmp & mask)) + return 0; + + /* #.# delay and loop */ + DRM_UDELAY(100); + --count; + } + + /* # now waiting is timeout, return 1 indicat failed */ + /* XXX: testsuit means a timeout 10000 */ + + DRM_ERROR("TOPAZ:time out to poll addr(0x%x) expected value(0x%08x), " + "actual 0x%08x (0x%08x & 0x%08x)\n", + addr, value, tmp & mask, tmp, mask); + + return -EBUSY; + +} + + +void lnc_topaz_reset_wq(struct work_struct *work) +{ + struct drm_psb_private *dev_priv = + container_of(work, struct drm_psb_private, topaz_watchdog_wq); + + struct psb_scheduler *scheduler = &dev_priv->scheduler; + unsigned long irq_flags; + + mutex_lock(&dev_priv->topaz_mutex); + dev_priv->topaz_needs_reset = 1; + dev_priv->topaz_current_sequence++; + PSB_DEBUG_GENERAL + ("MSVDXFENCE: incremented topaz_current_sequence to :%d\n", + dev_priv->topaz_current_sequence); + + psb_fence_error(scheduler->dev, LNC_ENGINE_ENCODE, + dev_priv->topaz_current_sequence, _PSB_FENCE_TYPE_EXE, + DRM_CMD_HANG); + + spin_lock_irqsave(&dev_priv->watchdog_lock, irq_flags); + dev_priv->timer_available = 1; + spin_unlock_irqrestore(&dev_priv->watchdog_lock, irq_flags); + + spin_lock_irqsave(&dev_priv->topaz_lock, irq_flags); + + /* psb_msvdx_flush_cmd_queue(scheduler->dev); */ + + spin_unlock_irqrestore(&dev_priv->topaz_lock, irq_flags); + + psb_schedule_watchdog(dev_priv); + mutex_unlock(&dev_priv->topaz_mutex); +} + + +/* this function finish the first part of initialization, the rest + * should be done in topaz_setup_fw + */ +int lnc_topaz_init(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + struct ttm_bo_device *bdev = &dev_priv->bdev; + uint32_t core_id, core_rev; + void *topaz_bo_virt; + int ret = 0; + bool is_iomem; + + PSB_DEBUG_GENERAL("TOPAZ: init topaz data structures\n"); + + /* # initialize comand topaz queueing [msvdx_queue] */ + INIT_LIST_HEAD(&dev_priv->topaz_queue); + /* # init mutex? CHECK: mutex usage [msvdx_mutex] */ + mutex_init(&dev_priv->topaz_mutex); + /* # spin lock init? CHECK spin lock usage [msvdx_lock] */ + spin_lock_init(&dev_priv->topaz_lock); + + /* # topaz status init. [msvdx_busy] */ + dev_priv->topaz_busy = 0; + dev_priv->topaz_cmd_seq = 0; + dev_priv->topaz_fw_loaded = 0; + dev_priv->topaz_cur_codec = 0; + dev_priv->topaz_mtx_data_mem = NULL; + dev_priv->cur_mtx_data_size = 0; + + dev_priv->topaz_mtx_reg_state = kmalloc(TOPAZ_MTX_REG_SIZE, + GFP_KERNEL); + if (dev_priv->topaz_mtx_reg_state == NULL) { + DRM_ERROR("TOPAZ: failed to allocate space " + "for mtx register\n"); + return -1; + } + + /* # gain write back structure,we may only need 32+4=40DW */ + if (!dev_priv->topaz_bo) { + ret = ttm_buffer_object_create(bdev, 4096, + ttm_bo_type_kernel, + DRM_PSB_FLAG_MEM_MMU | TTM_PL_FLAG_NO_EVICT, + 0, 0, 0, NULL, &(dev_priv->topaz_bo)); + if (ret != 0) { + DRM_ERROR("TOPAZ: failed to allocate topaz BO.\n"); + return ret; + } + } + + ret = ttm_bo_kmap(dev_priv->topaz_bo, 0, + dev_priv->topaz_bo->num_pages, + &dev_priv->topaz_bo_kmap); + if (ret) { + DRM_ERROR("TOPAZ: map topaz BO bo failed......\n"); + ttm_bo_unref(&dev_priv->topaz_bo); + return ret; + } + + topaz_bo_virt = ttm_kmap_obj_virtual(&dev_priv->topaz_bo_kmap, + &is_iomem); + dev_priv->topaz_ccb_wb = (void *) topaz_bo_virt; + dev_priv->topaz_wb_offset = dev_priv->topaz_bo->offset; + dev_priv->topaz_sync_addr = (uint32_t *) (topaz_bo_virt + 2048); + dev_priv->topaz_sync_offset = dev_priv->topaz_wb_offset + 2048; + PSB_DEBUG_GENERAL("TOPAZ: allocated BO for WriteBack and SYNC command," + "WB offset=0x%08x, SYNC offset=0x%08x\n", + dev_priv->topaz_wb_offset, dev_priv->topaz_sync_offset); + + *(dev_priv->topaz_sync_addr) = ~0; /* reset sync seq */ + + /* # reset topaz */ + MVEA_WRITE32(MVEA_CR_IMG_MVEA_SRST, + F_ENCODE(1, MVEA_CR_IMG_MVEA_SPE_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_IPE_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_CMC_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_DCF_SOFT_RESET)); + + MVEA_WRITE32(MVEA_CR_IMG_MVEA_SRST, + F_ENCODE(0, MVEA_CR_IMG_MVEA_SPE_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_IPE_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_CMC_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_DCF_SOFT_RESET)); + + /* # set up MMU */ + topaz_mmu_hwsetup(dev_priv); + + PSB_DEBUG_GENERAL("TOPAZ: defer firmware loading to the place" + "when receiving user space commands\n"); + +#if 0 /* can't load FW here */ + /* #.# load fw to driver */ + PSB_DEBUG_GENERAL("TOPAZ: will init firmware\n"); + ret = topaz_init_fw(dev); + if (ret != 0) + return -1; + + topaz_setup_fw(dev, FW_H264_NO_RC);/* just for test */ +#endif + /* # minimal clock */ + + /* # return 0 */ + TOPAZ_READ32(TOPAZ_CR_IMG_TOPAZ_CORE_ID, &core_id); + TOPAZ_READ32(TOPAZ_CR_IMG_TOPAZ_CORE_REV, &core_rev); + + PSB_DEBUG_GENERAL("TOPAZ: core_id(%x) core_rev(%x)\n", + core_id, core_rev); + + if (drm_psb_ospmxxx & ENABLE_TOPAZ_OSPM_D0IX) + psb_power_down_topaz(dev); + + return 0; +} + +int lnc_topaz_uninit(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + /* int n;*/ + + /* flush MMU */ + PSB_DEBUG_GENERAL("XXX: need to flush mmu cache here??\n"); + /* topaz_mmu_flushcache (dev_priv); */ + + /* # reset TOPAZ chip */ + lnc_topaz_reset(dev_priv); + + /* release resources */ + /* # release write back memory */ + dev_priv->topaz_ccb_wb = NULL; + + ttm_bo_unref(&dev_priv->topaz_bo); + + /* release mtx register save space */ + kfree(dev_priv->topaz_mtx_reg_state); + + /* release mtx data memory save space */ + if (dev_priv->topaz_mtx_data_mem) + ttm_bo_unref(&dev_priv->topaz_mtx_data_mem); + + /* # release firmware */ + /* XXX: but this handlnig should be reconsidered */ + /* XXX: there is no jpeg firmware...... */ +#if 0 /* FIX WHEN FIRMWARE IS LOADED */ + for (n = 1; n < IMG_CODEC_NUM; ++n) { + ttm_bo_unref(&topaz_fw[n].text); + ttm_bo_unref(&topaz_fw[n].data); + } +#endif + ttm_bo_kunmap(&dev_priv->topaz_bo_kmap); + ttm_bo_unref(&dev_priv->topaz_bo); + + return 0; +} + +int lnc_topaz_reset(struct drm_psb_private *dev_priv) +{ + return 0; +#if 0 + int ret = 0; + /* # software reset */ + MTX_WRITE32(MTX_CORE_CR_MTX_SOFT_RESET_OFFSET, + MTX_CORE_CR_MTX_SOFT_RESET_MTX_RESET_MASK); + + /* # call lnc_wait_for_register, wait reset finished */ + topaz_wait_for_register(dev_priv, + MTX_START + MTX_CORE_CR_MTX_ENABLE_OFFSET, + MTX_CORE_CR_MTX_ENABLE_MTX_ENABLE_MASK, + MTX_CORE_CR_MTX_ENABLE_MTX_ENABLE_MASK); + + /* # if reset finised */ + PSB_DEBUG_GENERAL("XXX: add condition judgement for topaz wait...\n"); + /* #.# clear interrupt enable flag */ + + /* #.# clear pending interrupt flags */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_INTCLEAR, + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX) | + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX_HALT) | + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MVEA) | + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MMU_FAULT) + ); + /* # destroy topaz mutex in drm_psb_privaet [msvdx_mutex] */ + + /* # return register value which is waited above */ + + PSB_DEBUG_GENERAL("called\n"); + return 0; +#endif +} + +/* read firmware bin file and load all data into driver */ +int topaz_init_fw(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + struct ttm_bo_device *bdev = &dev_priv->bdev; + const struct firmware *raw = NULL; + unsigned char *ptr; + int ret = 0; + int n; + struct topaz_fwinfo *cur_fw; + int cur_size; + struct topaz_codec_fw *cur_codec; + struct ttm_buffer_object **cur_drm_obj; + struct ttm_bo_kmap_obj tmp_kmap; + bool is_iomem; + + dev_priv->stored_initial_qp = 0; + + /* # get firmware */ + ret = request_firmware(&raw, FIRMWARE_NAME, &dev->pdev->dev); + if (ret != 0) { + DRM_ERROR("TOPAZ: request_firmware failed: %d\n", ret); + return ret; + } + + PSB_DEBUG_GENERAL("TOPAZ: opened firmware\n"); + + if (raw && (raw->size < sizeof(struct topaz_fwinfo))) { + DRM_ERROR("TOPAZ: firmware file is not correct size.\n"); + goto out; + } + + ptr = (unsigned char *) raw->data; + + if (!ptr) { + DRM_ERROR("TOPAZ: failed to load firmware.\n"); + goto out; + } + + /* # load fw from file */ + PSB_DEBUG_GENERAL("TOPAZ: load firmware.....\n"); + cur_fw = NULL; + /* didn't use the first element */ + for (n = 1; n < IMG_CODEC_NUM; ++n) { + cur_fw = (struct topaz_fwinfo *) ptr; + + cur_codec = &topaz_fw[cur_fw->codec]; + cur_codec->ver = cur_fw->ver; + cur_codec->codec = cur_fw->codec; + cur_codec->text_size = cur_fw->text_size; + cur_codec->data_size = cur_fw->data_size; + cur_codec->data_location = cur_fw->data_location; + + PSB_DEBUG_GENERAL("TOPAZ: load firemware %s.\n", + codec_to_string(cur_fw->codec)); + + /* #.# handle text section */ + cur_codec->text = NULL; + ptr += sizeof(struct topaz_fwinfo); + cur_drm_obj = &cur_codec->text; + cur_size = cur_fw->text_size; + + /* #.# malloc DRM object for fw storage */ + ret = ttm_buffer_object_create(bdev, cur_size, + ttm_bo_type_kernel, + DRM_PSB_FLAG_MEM_MMU | TTM_PL_FLAG_NO_EVICT, + 0, 0, 0, NULL, cur_drm_obj); + if (ret) { + DRM_ERROR("Failed to allocate firmware.\n"); + goto out; + } + + /* #.# fill DRM object with firmware data */ + ret = ttm_bo_kmap(*cur_drm_obj, 0, (*cur_drm_obj)->num_pages, + &tmp_kmap); + if (ret) { + PSB_DEBUG_GENERAL("drm_bo_kmap failed: %d\n", ret); + ttm_bo_unref(cur_drm_obj); + *cur_drm_obj = NULL; + goto out; + } + + memcpy(ttm_kmap_obj_virtual(&tmp_kmap, &is_iomem), ptr, + cur_size); + + ttm_bo_kunmap(&tmp_kmap); + + /* #.# handle data section */ + cur_codec->data = NULL; + ptr += cur_fw->text_size; + cur_drm_obj = &cur_codec->data; + cur_size = cur_fw->data_size; + + /* #.# malloc DRM object for fw storage */ + ret = ttm_buffer_object_create(bdev, cur_size, + ttm_bo_type_kernel, + DRM_PSB_FLAG_MEM_MMU | TTM_PL_FLAG_NO_EVICT, + 0, 0, 0, NULL, cur_drm_obj); + if (ret) { + DRM_ERROR("Failed to allocate firmware.\n"); + goto out; + } + + /* #.# fill DRM object with firmware data */ + ret = ttm_bo_kmap(*cur_drm_obj, 0, (*cur_drm_obj)->num_pages, + &tmp_kmap); + if (ret) { + PSB_DEBUG_GENERAL("drm_bo_kmap failed: %d\n", ret); + ttm_bo_unref(cur_drm_obj); + *cur_drm_obj = NULL; + goto out; + } + + memcpy(ttm_kmap_obj_virtual(&tmp_kmap, &is_iomem), ptr, + cur_size); + + ttm_bo_kunmap(&tmp_kmap); + + /* #.# validate firmware */ + + /* #.# update ptr */ + ptr += cur_fw->data_size; + } + + release_firmware(raw); + + PSB_DEBUG_GENERAL("TOPAZ: return from firmware init\n"); + + return 0; + +out: + if (raw) { + PSB_DEBUG_GENERAL("release firmware....\n"); + release_firmware(raw); + } + + return -1; +} + +/* setup fw when start a new context */ +int topaz_setup_fw(struct drm_device *dev, enum drm_lnc_topaz_codec codec) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + struct ttm_bo_device *bdev = &dev_priv->bdev; + uint32_t mem_size = RAM_SIZE; /* follow DDK */ + uint32_t verify_pc; + int ret; + +#if 0 + if (codec == dev_priv->topaz_current_codec) { + LNC_TRACEL("TOPAZ: reuse previous codec\n"); + return 0; + } +#endif + + if (drm_psb_ospmxxx & ENABLE_TOPAZ_OSPM_D0IX) + psb_power_up_topaz(dev); + + /* XXX: need to rest topaz? */ + PSB_DEBUG_GENERAL("XXX: should reset topaz when context change?\n"); + + /* XXX: interrupt enable shouldn't be enable here, + * this funtion is called when interrupt is enable, + * but here, we've no choice since we have to call setup_fw by + * manual */ + /* # upload firmware, clear interruputs and start the firmware + * -- from hostutils.c in TestSuits*/ + + /* # reset MVEA */ + MVEA_WRITE32(MVEA_CR_IMG_MVEA_SRST, + F_ENCODE(1, MVEA_CR_IMG_MVEA_SPE_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_IPE_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_CMC_SOFT_RESET) | + F_ENCODE(1, MVEA_CR_IMG_MVEA_DCF_SOFT_RESET)); + + MVEA_WRITE32(MVEA_CR_IMG_MVEA_SRST, + F_ENCODE(0, MVEA_CR_IMG_MVEA_SPE_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_IPE_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_CMPRS_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_JMCOMP_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_CMC_SOFT_RESET) | + F_ENCODE(0, MVEA_CR_IMG_MVEA_DCF_SOFT_RESET)); + + + topaz_mmu_hwsetup(dev_priv); + +#if !LNC_TOPAZ_NO_IRQ + lnc_topaz_disableirq(dev); +#endif + + PSB_DEBUG_GENERAL("TOPAZ: will setup firmware....\n"); + + topaz_set_default_regs(dev_priv); + + /* # reset mtx */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_SRST, + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_MVEA_SOFT_RESET) | + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_MTX_SOFT_RESET) | + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_VLC_SOFT_RESET)); + + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_SRST, 0x0); + + /* # upload fw by drm */ + PSB_DEBUG_GENERAL("TOPAZ: will upload firmware\n"); + + topaz_upload_fw(dev, codec); + + /* allocate the space for context save & restore if needed */ + if (dev_priv->topaz_mtx_data_mem == NULL) { + ret = ttm_buffer_object_create(bdev, + dev_priv->cur_mtx_data_size * 4, + ttm_bo_type_kernel, + DRM_PSB_FLAG_MEM_MMU | + TTM_PL_FLAG_NO_EVICT, + 0, 0, 0, NULL, + &dev_priv->topaz_mtx_data_mem); + if (ret) { + DRM_ERROR("TOPAZ: failed to allocate ttm buffer for " + "mtx data save\n"); + return -1; + } + } + PSB_DEBUG_GENERAL("TOPAZ: after upload fw ....\n"); + + /* XXX: In power save mode, need to save the complete data memory + * and restore it. MTX_FWIF.c record the data size */ + PSB_DEBUG_GENERAL("TOPAZ:in power save mode need to save memory?\n"); + + PSB_DEBUG_GENERAL("TOPAZ: setting up pc address\n"); + topaz_write_core_reg(dev_priv, TOPAZ_MTX_PC, PC_START_ADDRESS); + + PSB_DEBUG_GENERAL("TOPAZ: verify pc address\n"); + + topaz_read_core_reg(dev_priv, TOPAZ_MTX_PC, &verify_pc); + + /* enable auto clock is essential for this driver */ + TOPAZ_WRITE32(TOPAZ_CR_TOPAZ_AUTO_CLK_GATE, + F_ENCODE(1, TOPAZ_CR_TOPAZ_VLC_AUTO_CLK_GATE) | + F_ENCODE(1, TOPAZ_CR_TOPAZ_DB_AUTO_CLK_GATE)); + MVEA_WRITE32(MVEA_CR_MVEA_AUTO_CLOCK_GATING, + F_ENCODE(1, MVEA_CR_MVEA_IPE_AUTO_CLK_GATE) | + F_ENCODE(1, MVEA_CR_MVEA_SPE_AUTO_CLK_GATE) | + F_ENCODE(1, MVEA_CR_MVEA_CMPRS_AUTO_CLK_GATE) | + F_ENCODE(1, MVEA_CR_MVEA_JMCOMP_AUTO_CLK_GATE)); + + PSB_DEBUG_GENERAL("TOPAZ: current pc(%08X) vs %08X\n", + verify_pc, PC_START_ADDRESS); + + /* # turn on MTX */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_INTCLEAR, + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX)); + + MTX_WRITE32(MTX_CORE_CR_MTX_ENABLE_OFFSET, + MTX_CORE_CR_MTX_ENABLE_MTX_ENABLE_MASK); + + /* # poll on the interrupt which the firmware will generate */ + topaz_wait_for_register(dev_priv, + TOPAZ_START + TOPAZ_CR_IMG_TOPAZ_INTSTAT, + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTS_MTX), + F_MASK(TOPAZ_CR_IMG_TOPAZ_INTS_MTX)); + + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_INTCLEAR, + F_ENCODE(1, TOPAZ_CR_IMG_TOPAZ_INTCLR_MTX)); + + PSB_DEBUG_GENERAL("TOPAZ: after topaz mtx setup ....\n"); + + /* # get ccb buffer addr -- file hostutils.c */ + dev_priv->topaz_ccb_buffer_addr = + topaz_read_mtx_mem(dev_priv, + MTX_DATA_MEM_BASE + mem_size - 4); + dev_priv->topaz_ccb_ctrl_addr = + topaz_read_mtx_mem(dev_priv, + MTX_DATA_MEM_BASE + mem_size - 8); + dev_priv->topaz_ccb_size = + topaz_read_mtx_mem(dev_priv, + dev_priv->topaz_ccb_ctrl_addr + + MTX_CCBCTRL_CCBSIZE); + + dev_priv->topaz_cmd_windex = 0; + + PSB_DEBUG_GENERAL("TOPAZ:ccb_buffer_addr(%x),ctrl_addr(%x) size(%d)\n", + dev_priv->topaz_ccb_buffer_addr, + dev_priv->topaz_ccb_ctrl_addr, + dev_priv->topaz_ccb_size); + + /* # write back the initial QP Value */ + topaz_write_mtx_mem(dev_priv, + dev_priv->topaz_ccb_ctrl_addr + MTX_CCBCTRL_INITQP, + dev_priv->stored_initial_qp); + + PSB_DEBUG_GENERAL("TOPAZ: write WB mem address 0x%08x\n", + dev_priv->topaz_wb_offset); + topaz_write_mtx_mem(dev_priv, MTX_DATA_MEM_BASE + mem_size - 12, + dev_priv->topaz_wb_offset); + + /* this kick is essential for mtx.... */ + *((uint32_t *) dev_priv->topaz_ccb_wb) = 0x01020304; + topaz_mtx_kick(dev_priv, 1); + DRM_UDELAY(1000); + PSB_DEBUG_GENERAL("TOPAZ: DDK expected 0x12345678 in WB memory," + " and here it is 0x%08x\n", + *((uint32_t *) dev_priv->topaz_ccb_wb)); + + *((uint32_t *) dev_priv->topaz_ccb_wb) = 0x0;/* reset it to 0 */ + PSB_DEBUG_GENERAL("TOPAZ: firmware uploaded.\n"); + + /* XXX: is there any need to record next cmd num?? + * we use fence seqence number to record it + */ + dev_priv->topaz_busy = 0; + dev_priv->topaz_cmd_seq = 0; + +#if !LNC_TOPAZ_NO_IRQ + lnc_topaz_enableirq(dev); +#endif + +#if 0 + /* test sync command */ + { + uint32_t sync_cmd[3]; + uint32_t *sync_p = (uint32_t *)dev_priv->topaz_sync_addr; + int count = 10000; + + /* insert a SYNC command here */ + sync_cmd[0] = MTX_CMDID_SYNC | (3 << 8) | + (0x5b << 16); + sync_cmd[1] = dev_priv->topaz_sync_offset; + sync_cmd[2] = 0x3c; + + TOPAZ_BEGIN_CCB(dev_priv); + TOPAZ_OUT_CCB(dev_priv, sync_cmd[0]); + TOPAZ_OUT_CCB(dev_priv, sync_cmd[1]); + TOPAZ_OUT_CCB(dev_priv, sync_cmd[2]); + TOPAZ_END_CCB(dev_priv, 1); + + while (count && *sync_p != 0x3c) { + DRM_UDELAY(1000); + --count; + } + if ((count == 0) && (*sync_p != 0x3c)) { + DRM_ERROR("TOPAZ: wait sycn timeout (0x%08x)," + "actual 0x%08x\n", + 0x3c, *sync_p); + } + PSB_DEBUG_GENERAL("TOPAZ: SYNC done, seq=0x%08x\n", *sync_p); + } +#endif +#if 0 + topaz_mmu_flush(dev); + + topaz_test_null(dev, 0xe1e1); + topaz_test_null(dev, 0xe2e2); + topaz_mmu_test(dev, 0x12345678); + topaz_test_null(dev, 0xe3e3); + topaz_mmu_test(dev, 0x8764321); + + topaz_test_null(dev, 0xe4e4); + topaz_test_null(dev, 0xf3f3); +#endif + + return 0; +} + +#if UPLOAD_FW_BY_DMA +int topaz_upload_fw(struct drm_device *dev, enum drm_lnc_topaz_codec codec) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + const struct topaz_codec_fw *cur_codec_fw; + uint32_t text_size, data_size; + uint32_t data_location; + uint32_t cur_mtx_data_size; + + /* # refer HLD document */ + + /* # MTX reset */ + PSB_DEBUG_GENERAL("TOPAZ: mtx reset.\n"); + MTX_WRITE32(MTX_CORE_CR_MTX_SOFT_RESET_OFFSET, + MTX_CORE_CR_MTX_SOFT_RESET_MTX_RESET_MASK); + + DRM_UDELAY(6000); + + /* # upload the firmware by DMA */ + cur_codec_fw = &topaz_fw[codec]; + + PSB_DEBUG_GENERAL("Topaz:upload codec %s(%d) text sz=%d data sz=%d" + " data location(%d)\n", codec_to_string(codec), codec, + cur_codec_fw->text_size, cur_codec_fw->data_size, + cur_codec_fw->data_location); + + /* # upload text */ + text_size = cur_codec_fw->text_size / 4; + + /* setup the MTX to start recieving data: + use a register for the transfer which will point to the source + (MTX_CR_MTX_SYSC_CDMAT) */ + /* #.# fill the dst addr */ + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAA, 0x80900000); + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAC, + F_ENCODE(2, MTX_BURSTSIZE) | + F_ENCODE(0, MTX_RNW) | + F_ENCODE(1, MTX_ENABLE) | + F_ENCODE(text_size, MTX_LENGTH)); + + /* #.# set DMAC access to host memory via BIF */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 1); + + /* #.# transfer the codec */ + topaz_dma_transfer(dev_priv, 0, cur_codec_fw->text->offset, 0, + MTX_CR_MTX_SYSC_CDMAT, text_size, 0, 0); + + /* #.# wait dma finish */ + topaz_wait_for_register(dev_priv, + DMAC_START + IMG_SOC_DMAC_IRQ_STAT(0), + F_ENCODE(1, IMG_SOC_TRANSFER_FIN), + F_ENCODE(1, IMG_SOC_TRANSFER_FIN)); + + /* #.# clear interrupt */ + DMAC_WRITE32(IMG_SOC_DMAC_IRQ_STAT(0), 0); + + /* # return access to topaz core */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 0); + + /* # upload data */ + data_size = cur_codec_fw->data_size / 4; + data_location = cur_codec_fw->data_location; + + /* #.# fill the dst addr */ + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAA, + 0x80900000 + data_location - 0x82880000); + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAC, + F_ENCODE(2, MTX_BURSTSIZE) | + F_ENCODE(0, MTX_RNW) | + F_ENCODE(1, MTX_ENABLE) | + F_ENCODE(data_size, MTX_LENGTH)); + + /* #.# set DMAC access to host memory via BIF */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 1); + + /* #.# transfer the codec */ + topaz_dma_transfer(dev_priv, 0, cur_codec_fw->data->offset, 0, + MTX_CR_MTX_SYSC_CDMAT, data_size, 0, 0); + + /* #.# wait dma finish */ + topaz_wait_for_register(dev_priv, + DMAC_START + IMG_SOC_DMAC_IRQ_STAT(0), + F_ENCODE(1, IMG_SOC_TRANSFER_FIN), + F_ENCODE(1, IMG_SOC_TRANSFER_FIN)); + + /* #.# clear interrupt */ + DMAC_WRITE32(IMG_SOC_DMAC_IRQ_STAT(0), 0); + + /* # return access to topaz core */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 0); + + /* record this codec's mtx data size for + * context save & restore */ + cur_mtx_data_size = RAM_SIZE - (data_location - 0x82880000); + if (dev_priv->cur_mtx_data_size != cur_mtx_data_size) { + dev_priv->cur_mtx_data_size = cur_mtx_data_size; + if (dev_priv->topaz_mtx_data_mem) + ttm_bo_unref(&dev_priv->topaz_mtx_data_mem); + dev_priv->topaz_mtx_data_mem = NULL; + } + + return 0; +} + +#else + +void topaz_mtx_upload_by_register(struct drm_device *dev, uint32_t mtx_mem, + uint32_t addr, uint32_t size, + struct ttm_buffer_object *buf) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + uint32_t *buf_p; + uint32_t debug_reg, bank_size, bank_ram_size, bank_count; + uint32_t cur_ram_id, ram_addr , ram_id; + int map_ret, lp; + struct ttm_bo_kmap_obj bo_kmap; + bool is_iomem; + uint32_t cur_addr; + + get_mtx_control_from_dash(dev_priv); + + map_ret = ttm_bo_kmap(buf, 0, buf->num_pages, &bo_kmap); + if (map_ret) { + DRM_ERROR("TOPAZ: drm_bo_kmap failed: %d\n", map_ret); + return; + } + buf_p = (uint32_t *) ttm_kmap_obj_virtual(&bo_kmap, &is_iomem); + + + TOPAZ_READ32(TOPAZ_CORE_CR_MTX_DEBUG_OFFSET, &debug_reg); + debug_reg = 0x0a0a0606; + bank_size = (debug_reg & 0xf0000) >> 16; + bank_ram_size = 1 << (bank_size + 2); + + bank_count = (debug_reg & 0xf00) >> 8; + + topaz_wait_for_register(dev_priv, + MTX_START+MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_OFFSET, + MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_MTX_MTX_MCM_STAT_MASK, + MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_MTX_MTX_MCM_STAT_MASK); + + cur_ram_id = -1; + cur_addr = addr; + for (lp = 0; lp < size / 4; ++lp) { + ram_id = mtx_mem + (cur_addr / bank_ram_size); + + if (cur_ram_id != ram_id) { + ram_addr = cur_addr >> 2; + + MTX_WRITE32(MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_OFFSET, + F_ENCODE(ram_id, MTX_MTX_MCMID) | + F_ENCODE(ram_addr, MTX_MTX_MCM_ADDR) | + F_ENCODE(1, MTX_MTX_MCMAI)); + + cur_ram_id = ram_id; + } + cur_addr += 4; + + MTX_WRITE32(MTX_CORE_CR_MTX_RAM_ACCESS_DATA_TRANSFER_OFFSET, + *(buf_p + lp)); + + topaz_wait_for_register(dev_priv, + MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_OFFSET + MTX_START, + MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_MTX_MTX_MCM_STAT_MASK, + MTX_CORE_CR_MTX_RAM_ACCESS_STATUS_MTX_MTX_MCM_STAT_MASK); + } + + ttm_bo_kunmap(&bo_kmap); + + PSB_DEBUG_GENERAL("TOPAZ: register data upload done\n"); + return; +} + +int topaz_upload_fw(struct drm_device *dev, enum drm_lnc_topaz_codec codec) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + const struct topaz_codec_fw *cur_codec_fw; + uint32_t text_size, data_size; + uint32_t data_location; + + /* # refer HLD document */ + /* # MTX reset */ + PSB_DEBUG_GENERAL("TOPAZ: mtx reset.\n"); + MTX_WRITE32(MTX_CORE_CR_MTX_SOFT_RESET_OFFSET, + MTX_CORE_CR_MTX_SOFT_RESET_MTX_RESET_MASK); + + DRM_UDELAY(6000); + + /* # upload the firmware by DMA */ + cur_codec_fw = &topaz_fw[codec]; + + PSB_DEBUG_GENERAL("Topaz: upload codec %s text size(%d) data size(%d)" + " data location(0x%08x)\n", codec_to_string(codec), + cur_codec_fw->text_size, cur_codec_fw->data_size, + cur_codec_fw->data_location); + + /* # upload text */ + text_size = cur_codec_fw->text_size; + + topaz_mtx_upload_by_register(dev, LNC_MTX_CORE_CODE_MEM, + PC_START_ADDRESS - MTX_MEMORY_BASE, + text_size, cur_codec_fw->text); + + /* # upload data */ + data_size = cur_codec_fw->data_size; + data_location = cur_codec_fw->data_location; + + topaz_mtx_upload_by_register(dev, LNC_MTX_CORE_DATA_MEM, + data_location - 0x82880000, data_size, + cur_codec_fw->data); + + return 0; +} + +#endif /* UPLOAD_FW_BY_DMA */ + +void +topaz_dma_transfer(struct drm_psb_private *dev_priv, uint32_t channel, + uint32_t src_phy_addr, uint32_t offset, + uint32_t soc_addr, uint32_t byte_num, + uint32_t is_increment, uint32_t is_write) +{ + uint32_t dmac_count; + uint32_t irq_stat; + uint32_t count; + + PSB_DEBUG_GENERAL("TOPAZ: using dma to transfer firmware\n"); + /* # check that no transfer is currently in progress and no + interrupts are outstanding ?? (why care interrupt) */ + DMAC_READ32(IMG_SOC_DMAC_COUNT(channel), &dmac_count); + if (0 != (dmac_count & (MASK_IMG_SOC_EN | MASK_IMG_SOC_LIST_EN))) + DRM_ERROR("TOPAZ: there is tranfer in progress\n"); + + /* assert(0==(dmac_count & (MASK_IMG_SOC_EN | MASK_IMG_SOC_LIST_EN)));*/ + + /* no hold off period */ + DMAC_WRITE32(IMG_SOC_DMAC_PER_HOLD(channel), 0); + /* clear previous interrupts */ + DMAC_WRITE32(IMG_SOC_DMAC_IRQ_STAT(channel), 0); + /* check irq status */ + DMAC_READ32(IMG_SOC_DMAC_IRQ_STAT(channel), &irq_stat); + /* assert(0 == irq_stat); */ + if (0 != irq_stat) + DRM_ERROR("TOPAZ: there is hold up\n"); + + DMAC_WRITE32(IMG_SOC_DMAC_SETUP(channel), + (src_phy_addr + offset)); + count = DMAC_VALUE_COUNT(DMAC_BSWAP_NO_SWAP, DMAC_PWIDTH_32_BIT, + is_write, DMAC_PWIDTH_32_BIT, byte_num); + /* generate an interrupt at the end of transfer */ + count |= MASK_IMG_SOC_TRANSFER_IEN; + count |= F_ENCODE(is_write, IMG_SOC_DIR); + DMAC_WRITE32(IMG_SOC_DMAC_COUNT(channel), count); + + DMAC_WRITE32(IMG_SOC_DMAC_PERIPH(channel), + DMAC_VALUE_PERIPH_PARAM(DMAC_ACC_DEL_0, + is_increment, DMAC_BURST_2)); + + DMAC_WRITE32(IMG_SOC_DMAC_PERIPHERAL_ADDR(channel), soc_addr); + + /* Finally, rewrite the count register with + * the enable bit set to kick off the transfer + */ + DMAC_WRITE32(IMG_SOC_DMAC_COUNT(channel), count | MASK_IMG_SOC_EN); + + PSB_DEBUG_GENERAL("TOPAZ: dma transfer started.\n"); + + return; +} + +void topaz_set_default_regs(struct drm_psb_private *dev_priv) +{ + int n; + int count = sizeof(topaz_default_regs) / (sizeof(unsigned long) * 3); + + for (n = 0; n < count; n++) + MM_WRITE32(topaz_default_regs[n][0], + topaz_default_regs[n][1], + topaz_default_regs[n][2]); + +} + +void topaz_write_core_reg(struct drm_psb_private *dev_priv, uint32_t reg, + const uint32_t val) +{ + uint32_t tmp; + get_mtx_control_from_dash(dev_priv); + + /* put data into MTX_RW_DATA */ + MTX_WRITE32(MTX_CORE_CR_MTX_REGISTER_READ_WRITE_DATA_OFFSET, val); + + /* request a write */ + tmp = reg & + ~MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK; + MTX_WRITE32(MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_OFFSET, tmp); + + /* wait for operation finished */ + topaz_wait_for_register(dev_priv, + MTX_START + + MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_OFFSET, + MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK, + MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK); + + release_mtx_control_from_dash(dev_priv); +} + +void topaz_read_core_reg(struct drm_psb_private *dev_priv, uint32_t reg, + uint32_t *ret_val) +{ + uint32_t tmp; + + get_mtx_control_from_dash(dev_priv); + + /* request a write */ + tmp = (reg & + ~MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK); + MTX_WRITE32(MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_OFFSET, + MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_RNW_MASK | tmp); + + /* wait for operation finished */ + topaz_wait_for_register(dev_priv, + MTX_START + + MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_OFFSET, + MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK, + MTX_CORE_CR_MTX_REGISTER_READ_WRITE_REQUEST_MTX_DREADY_MASK); + + /* read */ + MTX_READ32(MTX_CORE_CR_MTX_REGISTER_READ_WRITE_DATA_OFFSET, + ret_val); + + release_mtx_control_from_dash(dev_priv); +} + +void get_mtx_control_from_dash(struct drm_psb_private *dev_priv) +{ + int debug_reg_slave_val; + + /* GetMTXControlFromDash */ + TOPAZ_WRITE32(TOPAZ_CORE_CR_MTX_DEBUG_OFFSET, + F_ENCODE(1, TOPAZ_CR_MTX_DBG_IS_SLAVE) | + F_ENCODE(2, TOPAZ_CR_MTX_DBG_GPIO_OUT)); + do { + TOPAZ_READ32(TOPAZ_CORE_CR_MTX_DEBUG_OFFSET, + &debug_reg_slave_val); + } while ((debug_reg_slave_val & 0x18) != 0); + + /* save access control */ + TOPAZ_READ32(MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_OFFSET, + &dev_priv->topaz_dash_access_ctrl); +} + +void release_mtx_control_from_dash(struct drm_psb_private *dev_priv) +{ + /* restore access control */ + TOPAZ_WRITE32(MTX_CORE_CR_MTX_RAM_ACCESS_CONTROL_OFFSET, + dev_priv->topaz_dash_access_ctrl); + + /* release bus */ + TOPAZ_WRITE32(TOPAZ_CORE_CR_MTX_DEBUG_OFFSET, + F_ENCODE(1, TOPAZ_CR_MTX_DBG_IS_SLAVE)); +} + +void topaz_mmu_hwsetup(struct drm_psb_private *dev_priv) +{ + uint32_t pd_addr = psb_get_default_pd_addr(dev_priv->mmu); + + /* bypass all request while MMU is being configured */ + TOPAZ_WRITE32(TOPAZ_CR_MMU_CONTROL0, + F_ENCODE(1, TOPAZ_CR_MMU_BYPASS)); + + /* set MMU hardware at the page table directory */ + PSB_DEBUG_GENERAL("TOPAZ: write PD phyaddr=0x%08x " + "into MMU_DIR_LIST0/1\n", pd_addr); + TOPAZ_WRITE32(TOPAZ_CR_MMU_DIR_LIST_BASE(0), pd_addr); + TOPAZ_WRITE32(TOPAZ_CR_MMU_DIR_LIST_BASE(1), 0); + + /* setup index register, all pointing to directory bank 0 */ + TOPAZ_WRITE32(TOPAZ_CR_MMU_BANK_INDEX, 0); + + /* now enable MMU access for all requestors */ + TOPAZ_WRITE32(TOPAZ_CR_MMU_CONTROL0, 0); +} + +void topaz_mmu_flushcache(struct drm_psb_private *dev_priv) +{ + uint32_t mmu_control; + +#if 0 + PSB_DEBUG_GENERAL("XXX: Only one PTD/PTE cache" + " so flush using the master core\n"); +#endif + /* XXX: disable interrupt */ + + TOPAZ_READ32(TOPAZ_CR_MMU_CONTROL0, &mmu_control); + mmu_control |= F_ENCODE(1, TOPAZ_CR_MMU_INVALDC); + mmu_control |= F_ENCODE(1, TOPAZ_CR_MMU_FLUSH); + +#if 0 + PSB_DEBUG_GENERAL("Set Invalid flag (this causes a flush with MMU\n" + "still operating afterwards even if not cleared,\n" + "but may want to replace with MMU_FLUSH?\n"); +#endif + TOPAZ_WRITE32(TOPAZ_CR_MMU_CONTROL0, mmu_control); + + /* clear it */ + mmu_control &= (~F_ENCODE(1, TOPAZ_CR_MMU_INVALDC)); + mmu_control &= (~F_ENCODE(1, TOPAZ_CR_MMU_FLUSH)); + TOPAZ_WRITE32(TOPAZ_CR_MMU_CONTROL0, mmu_control); +} + +#if 0 /* DEBUG_FUNCTION */ +struct reg_pair { + uint32_t base; + uint32_t offset; +}; + + +static int ccb_offset; + +static int topaz_test_null(struct drm_device *dev, uint32_t seq) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + + /* XXX: here we finished firmware setup.... + * using a NULL command to verify the + * correctness of firmware + */ + uint32_t null_cmd; + uint32_t cmd_seq; + + null_cmd = 0 | (1 << 8) | (seq) << 16; + topaz_write_mtx_mem(dev_priv, + dev_priv->topaz_ccb_buffer_addr + ccb_offset, + null_cmd); + + topaz_mtx_kick(dev_priv, 1); + + DRM_UDELAY(1000); /* wait to finish */ + + cmd_seq = topaz_read_mtx_mem(dev_priv, + dev_priv->topaz_ccb_ctrl_addr + 4); + + PSB_DEBUG_GENERAL("Topaz: Sent NULL with sequence=0x%08x," + " got sequence=0x%08x (WB_seq=0x%08x,WB_roff=%d)\n", + seq, cmd_seq, WB_SEQ, WB_ROFF); + + PSB_DEBUG_GENERAL("Topaz: after NULL test, query IRQ and clear it\n"); + + topaz_test_queryirq(dev); + topaz_test_clearirq(dev); + + ccb_offset += 4; + + return 0; +} + +void topaz_mmu_flush(struct drm_psb_private *dev_priv) +{ + uint32_t val; + + TOPAZ_READ32(TOPAZ_CR_MMU_CONTROL0, &val); + TOPAZ_WRITE32(TOPAZ_CR_MMU_CONTROL0, + val | F_ENCODE(1, TOPAZ_CR_MMU_INVALDC)); + wmb(); + TOPAZ_WRITE32(TOPAZ_CR_MMU_CONTROL0, + val & ~F_ENCODE(0, TOPAZ_CR_MMU_INVALDC)); + TOPAZ_READ32(TOPAZ_CR_MMU_CONTROL0, &val); +} + +/* + * this function will test whether the mmu is correct: + * it get a drm_buffer_object and use CMD_SYNC to write + * certain value into this buffer. + */ +static void topaz_mmu_test(struct drm_device *dev, uint32_t sync_value) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + uint32_t sync_cmd; + unsigned long real_pfn; + int ret; + uint32_t cmd_seq; + + *((uint32_t *)dev_priv->topaz_sync_addr) = 0xeeeeeeee; + + /* topaz_mmu_flush(dev); */ + + sync_cmd = MTX_CMDID_SYNC | (3 << 8) | (0xeeee) << 16; + + topaz_write_mtx_mem_multiple_setup(dev_priv, + dev_priv->topaz_ccb_buffer_addr + ccb_offset); + + topaz_write_mtx_mem_multiple(dev_priv, sync_cmd); + topaz_write_mtx_mem_multiple(dev_priv, dev_priv->topaz_sync_offset); + topaz_write_mtx_mem_multiple(dev_priv, sync_value); + + topaz_mtx_kick(dev_priv, 1); + + ret = psb_mmu_virtual_to_pfn(psb_mmu_get_default_pd(dev_priv->mmu), + dev_priv->topaz_sync_offset, &real_pfn); + if (ret != 0) { + PSB_DEBUG_GENERAL("psb_mmu_virtual_to_pfn failed,exit\n"); + return; + } + PSB_DEBUG_GENERAL("TOPAZ: issued SYNC command, " + "BO offset=0x%08x (pfn=%lu), synch value=0x%08x\n", + dev_priv->topaz_sync_offset, real_pfn, sync_value); + + /* XXX: if we can use interrupt, we can wait this command finish */ + /* topaz_wait_for_register (dev_priv, + TOPAZ_START + TOPAZ_CR_IMG_TOPAZ_INTSTAT, 0xf, 0xf); */ + DRM_UDELAY(1000); + + cmd_seq = topaz_read_mtx_mem(dev_priv, + dev_priv->topaz_ccb_ctrl_addr + 4); + PSB_DEBUG_GENERAL("Topaz: cmd_seq equals 0x%x, and expected 0x%x " + "(WB_seq=0x%08x,WB_roff=%d),synch value is 0x%x," + "expected 0x%08x\n", + cmd_seq, 0xeeee, WB_SEQ, WB_ROFF, + *((uint32_t *)dev_priv->topaz_sync_addr), sync_value); + + PSB_DEBUG_GENERAL("Topaz: after MMU test, query IRQ and clear it\n"); + topaz_test_queryirq(dev); + topaz_test_clearirq(dev); + + ccb_offset += 3*4; /* shift 3DWs */ +} + +#endif + +int lnc_topaz_restore_mtx_state(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *)dev->dev_private; + uint32_t reg_val; + uint32_t *mtx_reg_state; + int i; + + if (dev_priv->topaz_mtx_data_mem == NULL) { + DRM_ERROR("TOPAZ: try to restore context without " + "space allocated\n"); + return -1; + } + + /* turn on mtx clocks */ + MTX_READ32(TOPAZ_CR_TOPAZ_MAN_CLK_GATE, ®_val); + MTX_WRITE32(TOPAZ_CR_TOPAZ_MAN_CLK_GATE, + reg_val & (~MASK_TOPAZ_CR_TOPAZ_MTX_MAN_CLK_GATE)); + + /* reset mtx */ + /* FIXME: should use core_write??? */ + MTX_WRITE32(MTX_CORE_CR_MTX_SOFT_RESET_OFFSET, + MTX_CORE_CR_MTX_SOFT_RESET_MTX_RESET_MASK); + DRM_UDELAY(6000); + + topaz_mmu_hwsetup(dev_priv); + /* upload code, restore mtx data */ + mtx_dma_write(dev); + + mtx_reg_state = dev_priv->topaz_mtx_reg_state; + /* restore register */ + /* FIXME: conside to put read/write into one function */ + /* Saves 8 Registers of D0 Bank */ + /* DoRe0, D0Ar6, D0Ar4, D0Ar2, D0FrT, D0.5, D0.6 and D0.7 */ + for (i = 0; i < 8; i++) { + topaz_write_core_reg(dev_priv, 0x1 | (i<<4), + *mtx_reg_state); + mtx_reg_state++; + } + /* Saves 8 Registers of D1 Bank */ + /* D1Re0, D1Ar5, D1Ar3, D1Ar1, D1RtP, D1.5, D1.6 and D1.7 */ + for (i = 0; i < 8; i++) { + topaz_write_core_reg(dev_priv, 0x2 | (i<<4), + *mtx_reg_state); + mtx_reg_state++; + } + /* Saves 4 Registers of A0 Bank */ + /* A0StP, A0FrP, A0.2 and A0.3 */ + for (i = 0; i < 4; i++) { + topaz_write_core_reg(dev_priv, 0x3 | (i<<4), + *mtx_reg_state); + mtx_reg_state++; + } + /* Saves 4 Registers of A1 Bank */ + /* A1GbP, A1LbP, A1.2 and A1.3 */ + for (i = 0; i < 4; i++) { + topaz_write_core_reg(dev_priv, 0x4 | (i<<4), + *mtx_reg_state); + mtx_reg_state++; + } + /* Saves PC and PCX */ + for (i = 0; i < 2; i++) { + topaz_write_core_reg(dev_priv, 0x5 | (i<<4), + *mtx_reg_state); + mtx_reg_state++; + } + /* Saves 8 Control Registers */ + /* TXSTAT, TXMASK, TXSTATI, TXMASKI, TXPOLL, TXGPIOI, TXPOLLI, + * TXGPIOO */ + for (i = 0; i < 8; i++) { + topaz_write_core_reg(dev_priv, 0x7 | (i<<4), + *mtx_reg_state); + mtx_reg_state++; + } + + /* turn on MTX */ + MTX_WRITE32(MTX_CORE_CR_MTX_ENABLE_OFFSET, + MTX_CORE_CR_MTX_ENABLE_MTX_ENABLE_MASK); + + return 0; +} + +int lnc_topaz_save_mtx_state(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *)dev->dev_private; + uint32_t *mtx_reg_state; + int i; + struct topaz_codec_fw *cur_codec_fw; + + /* FIXME: make sure the topaz_mtx_data_mem is allocated */ + if (dev_priv->topaz_mtx_data_mem == NULL) { + DRM_ERROR("TOPAZ: try to save context without space " + "allocated\n"); + return -1; + } + + topaz_wait_for_register(dev_priv, + MTX_START + MTX_CORE_CR_MTX_TXRPT_OFFSET, + TXRPT_WAITONKICK_VALUE, + 0xffffffff); + + /* stop mtx */ + MTX_WRITE32(MTX_CORE_CR_MTX_ENABLE_OFFSET, + MTX_CORE_CR_MTX_ENABLE_MTX_TOFF_MASK); + + mtx_reg_state = dev_priv->topaz_mtx_reg_state; + + /* FIXME: conside to put read/write into one function */ + /* Saves 8 Registers of D0 Bank */ + /* DoRe0, D0Ar6, D0Ar4, D0Ar2, D0FrT, D0.5, D0.6 and D0.7 */ + for (i = 0; i < 8; i++) { + topaz_read_core_reg(dev_priv, 0x1 | (i<<4), + mtx_reg_state); + mtx_reg_state++; + } + /* Saves 8 Registers of D1 Bank */ + /* D1Re0, D1Ar5, D1Ar3, D1Ar1, D1RtP, D1.5, D1.6 and D1.7 */ + for (i = 0; i < 8; i++) { + topaz_read_core_reg(dev_priv, 0x2 | (i<<4), + mtx_reg_state); + mtx_reg_state++; + } + /* Saves 4 Registers of A0 Bank */ + /* A0StP, A0FrP, A0.2 and A0.3 */ + for (i = 0; i < 4; i++) { + topaz_read_core_reg(dev_priv, 0x3 | (i<<4), + mtx_reg_state); + mtx_reg_state++; + } + /* Saves 4 Registers of A1 Bank */ + /* A1GbP, A1LbP, A1.2 and A1.3 */ + for (i = 0; i < 4; i++) { + topaz_read_core_reg(dev_priv, 0x4 | (i<<4), + mtx_reg_state); + mtx_reg_state++; + } + /* Saves PC and PCX */ + for (i = 0; i < 2; i++) { + topaz_read_core_reg(dev_priv, 0x5 | (i<<4), + mtx_reg_state); + mtx_reg_state++; + } + /* Saves 8 Control Registers */ + /* TXSTAT, TXMASK, TXSTATI, TXMASKI, TXPOLL, TXGPIOI, TXPOLLI, + * TXGPIOO */ + for (i = 0; i < 8; i++) { + topaz_read_core_reg(dev_priv, 0x7 | (i<<4), + mtx_reg_state); + mtx_reg_state++; + } + + /* save mtx data memory */ + cur_codec_fw = &topaz_fw[dev_priv->topaz_cur_codec]; + + mtx_dma_read(dev, cur_codec_fw->data_location + 0x80900000 - 0x82880000, + dev_priv->cur_mtx_data_size); + + /* turn off mtx clocks */ + MTX_WRITE32(TOPAZ_CR_TOPAZ_MAN_CLK_GATE, + MASK_TOPAZ_CR_TOPAZ_MTX_MAN_CLK_GATE); + + return 0; +} + +void mtx_dma_read(struct drm_device *dev, uint32_t source_addr, uint32_t size) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *)dev->dev_private; + struct ttm_buffer_object *target; + + /* setup mtx DMAC registers to do transfer */ + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAA, source_addr); + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAC, + F_ENCODE(2, MTX_BURSTSIZE) | + F_ENCODE(1, MTX_RNW) | + F_ENCODE(1, MTX_ENABLE) | + F_ENCODE(size, MTX_LENGTH)); + + /* give the DMAC access to the host memory via BIF */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 1); + + target = dev_priv->topaz_mtx_data_mem; + /* transfert the data */ + /* FIXME: size is meaured by bytes? */ + topaz_dma_transfer(dev_priv, 0, target->offset, 0, + MTX_CR_MTX_SYSC_CDMAT, + size, 0, 1); + + /* wait for it transfer */ + topaz_wait_for_register(dev_priv, IMG_SOC_DMAC_IRQ_STAT(0) + DMAC_START, + F_ENCODE(1, IMG_SOC_TRANSFER_FIN), + F_ENCODE(1, IMG_SOC_TRANSFER_FIN)); + /* clear interrupt */ + DMAC_WRITE32(IMG_SOC_DMAC_IRQ_STAT(0), 0); + /* give access back to topaz core */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 0); +} + +void dmac_transfer(struct drm_device *dev, uint32_t channel, uint32_t dst_addr, + uint32_t soc_addr, uint32_t bytes_num, + int increment, int rnw) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *)dev->dev_private; + uint32_t count_reg; + uint32_t irq_state; + + /* check no transfer is in progress */ + DMAC_READ32(IMG_SOC_DMAC_COUNT(channel), &count_reg); + if (0 != (count_reg & (MASK_IMG_SOC_EN | MASK_IMG_SOC_LIST_EN))) { + DRM_ERROR("TOPAZ: there's transfer in progress when wanna " + "save mtx data\n"); + /* FIXME: how to handle this error */ + return; + } + + /* no hold off period */ + DMAC_WRITE32(IMG_SOC_DMAC_PER_HOLD(channel), 0); + /* cleare irq state */ + DMAC_WRITE32(IMG_SOC_DMAC_IRQ_STAT(channel), 0); + DMAC_READ32(IMG_SOC_DMAC_IRQ_STAT(channel), &irq_state); + if (0 != irq_state) { + DRM_ERROR("TOPAZ: there's irq cann't clear\n"); + return; + } + + DMAC_WRITE32(IMG_SOC_DMAC_SETUP(channel), dst_addr); + count_reg = DMAC_VALUE_COUNT(DMAC_BSWAP_NO_SWAP, + DMAC_PWIDTH_32_BIT, rnw, + DMAC_PWIDTH_32_BIT, bytes_num); + /* generate an interrupt at end of transfer */ + count_reg |= MASK_IMG_SOC_TRANSFER_IEN; + count_reg |= F_ENCODE(rnw, IMG_SOC_DIR); + DMAC_WRITE32(IMG_SOC_DMAC_COUNT(channel), count_reg); + + DMAC_WRITE32(IMG_SOC_DMAC_PERIPH(channel), + DMAC_VALUE_PERIPH_PARAM(DMAC_ACC_DEL_0, increment, + DMAC_BURST_2)); + DMAC_WRITE32(IMG_SOC_DMAC_PERIPHERAL_ADDR(channel), soc_addr); + + /* Finally, rewrite the count register with the enable + * bit set to kick off the transfer */ + DMAC_WRITE32(IMG_SOC_DMAC_COUNT(channel), + count_reg | MASK_IMG_SOC_EN); +} + +void mtx_dma_write(struct drm_device *dev) +{ + struct topaz_codec_fw *cur_codec_fw; + struct drm_psb_private *dev_priv = + (struct drm_psb_private *)dev->dev_private; + + cur_codec_fw = &topaz_fw[dev_priv->topaz_cur_codec]; + + /* upload code */ + /* setup mtx DMAC registers to recieve transfer */ + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAA, 0x80900000); + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAC, + F_ENCODE(2, MTX_BURSTSIZE) | + F_ENCODE(0, MTX_RNW) | + F_ENCODE(1, MTX_ENABLE) | + F_ENCODE(cur_codec_fw->text_size / 4, MTX_LENGTH)); + + /* give DMAC access to host memory */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 1); + + /* transfer code */ + topaz_dma_transfer(dev_priv, 0, cur_codec_fw->text->offset, 0, + MTX_CR_MTX_SYSC_CDMAT, cur_codec_fw->text_size / 4, + 0, 0); + /* wait finished */ + topaz_wait_for_register(dev_priv, IMG_SOC_DMAC_IRQ_STAT(0) + DMAC_START, + F_ENCODE(1, IMG_SOC_TRANSFER_FIN), + F_ENCODE(1, IMG_SOC_TRANSFER_FIN)); + /* clear interrupt */ + DMAC_WRITE32(IMG_SOC_DMAC_IRQ_STAT(0), 0); + + /* setup mtx start recieving data */ + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAA, 0x80900000 + + (cur_codec_fw->data_location) - 0x82880000); + + MTX_WRITE32(MTX_CR_MTX_SYSC_CDMAC, + F_ENCODE(2, MTX_BURSTSIZE) | + F_ENCODE(0, MTX_RNW) | + F_ENCODE(1, MTX_ENABLE) | + F_ENCODE(dev_priv->cur_mtx_data_size, MTX_LENGTH)); + + /* give DMAC access to host memory */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 1); + + /* transfer data */ + topaz_dma_transfer(dev_priv, 0, dev_priv->topaz_mtx_data_mem->offset, + 0, MTX_CR_MTX_SYSC_CDMAT, + dev_priv->cur_mtx_data_size, + 0, 0); + /* wait finished */ + topaz_wait_for_register(dev_priv, IMG_SOC_DMAC_IRQ_STAT(0) + DMAC_START, + F_ENCODE(1, IMG_SOC_TRANSFER_FIN), + F_ENCODE(1, IMG_SOC_TRANSFER_FIN)); + /* clear interrupt */ + DMAC_WRITE32(IMG_SOC_DMAC_IRQ_STAT(0), 0); + + /* give access back to Topaz Core */ + TOPAZ_WRITE32(TOPAZ_CR_IMG_TOPAZ_DMAC_MODE, 0); +} + +#if 0 +void topaz_save_default_regs(struct drm_psb_private *dev_priv, uint32_t *data) +{ + int n; + int count; + + count = sizeof(topaz_default_regs) / (sizeof(unsigned long) * 3); + for (n = 0; n < count; n++, ++data) + MM_READ32(topaz_default_regs[n][0], + topaz_default_regs[n][1], + data); + +} + +void topaz_restore_default_regs(struct drm_psb_private *dev_priv, + uint32_t *data) +{ + int n; + int count; + + count = sizeof(topaz_default_regs) / (sizeof(unsigned long) * 3); + for (n = 0; n < count; n++, ++data) + MM_WRITE32(topaz_default_regs[n][0], + topaz_default_regs[n][1], + *data); + +} +#endif --- /dev/null +++ b/drivers/staging/psb/Makefile @@ -0,0 +1,36 @@ +obj-$(CONFIG_DRM_PSB) += psb.o + +ccflags-y := -Idrivers/gpu/drm -Idrivers/gpu/drm/ttm -I$(PWD) + +psb-objs := \ + psb_drv.o \ + psb_mmu.o \ + psb_sgx.o \ + psb_irq.o \ + psb_fence.o \ + psb_buffer.o \ + psb_gtt.o \ + psb_schedule.o \ + psb_scene.o \ + psb_reset.o \ + psb_xhw.o \ + psb_msvdx.o \ + lnc_topaz.o \ + lnc_topazinit.o \ + psb_msvdxinit.o \ + psb_ttm_glue.o \ + psb_fb.o \ + psb_setup.o \ + ttm/ttm_object.o \ + ttm/ttm_lock.o \ + ttm/ttm_fence_user.o \ + ttm/ttm_fence.o \ + ttm/ttm_tt.o \ + ttm/ttm_execbuf_util.o \ + ttm/ttm_bo.o \ + ttm/ttm_bo_util.o \ + ttm/ttm_placement_user.o \ + ttm/ttm_bo_vm.o \ + ttm/ttm_pat_compat.o \ + ttm/ttm_agp_backend.o \ + ttm/ttm_memory.o --- /dev/null +++ b/drivers/staging/psb/psb_buffer.c @@ -0,0 +1,504 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + * develop this driver. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include "psb_drv.h" +#include "psb_schedule.h" +#include "ttm/ttm_placement_common.h" +#include "ttm/ttm_execbuf_util.h" +#include "ttm/ttm_fence_api.h" + +#define DRM_MEM_TTM 26 + +struct drm_psb_ttm_backend { + struct ttm_backend base; + struct page **pages; + unsigned int desired_tile_stride; + unsigned int hw_tile_stride; + int mem_type; + unsigned long offset; + unsigned long num_pages; +}; + +/* + * Poulsbo GPU virtual space looks like this + * (We currently use only one MMU context). + * + * gatt_start = Start of GATT aperture in bus space. + * stolen_end = End of GATT populated by stolen memory in bus space. + * gatt_end = End of GATT + * twod_end = MIN(gatt_start + 256_MEM, gatt_end) + * + * 0x00000000 -> 0x10000000 Temporary mapping space for tiling- + * and copy operations. + * This space is not managed and is protected by the + * temp_mem mutex. + * + * 0x10000000 -> 0x20000000 DRM_PSB_MEM_KERNEL For kernel buffers. + * + * 0x20000000 -> gatt_start DRM_PSB_MEM_MMU For generic MMU-only use. + * + * gatt_start -> stolen_end TTM_PL_VRAM Pre-populated GATT pages. + * + * stolen_end -> twod_end TTM_PL_TT GATT memory usable by 2D engine. + * + * twod_end -> gatt_end DRM_BO_MEM_APER GATT memory not + * usable by 2D engine. + * + * gatt_end -> 0xffffffff Currently unused. + */ + +static int psb_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, + struct ttm_mem_type_manager *man) +{ + + struct drm_psb_private *dev_priv = + container_of(bdev, struct drm_psb_private, bdev); + struct psb_gtt *pg = dev_priv->pg; + + switch (type) { + case TTM_PL_SYSTEM: + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; + man->available_caching = TTM_PL_FLAG_CACHED | + TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_CACHED; + break; + case DRM_PSB_MEM_KERNEL: + man->io_offset = 0x00000000; + man->io_size = 0x00000000; + man->io_addr = NULL; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_CMA; + man->gpu_offset = PSB_MEM_KERNEL_START; + man->available_caching = TTM_PL_FLAG_CACHED | + TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + break; + case DRM_PSB_MEM_MMU: + man->io_offset = 0x00000000; + man->io_size = 0x00000000; + man->io_addr = NULL; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_CMA; + man->gpu_offset = PSB_MEM_MMU_START; + man->available_caching = TTM_PL_FLAG_CACHED | + TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + break; + case DRM_PSB_MEM_PDS: + man->io_offset = 0x00000000; + man->io_size = 0x00000000; + man->io_addr = NULL; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_CMA; + man->gpu_offset = PSB_MEM_PDS_START; + man->available_caching = TTM_PL_FLAG_CACHED | + TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + break; + case DRM_PSB_MEM_RASTGEOM: + man->io_offset = 0x00000000; + man->io_size = 0x00000000; + man->io_addr = NULL; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_CMA; + man->gpu_offset = PSB_MEM_RASTGEOM_START; + man->available_caching = TTM_PL_FLAG_CACHED | + TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + break; + case TTM_PL_VRAM: + man->io_addr = NULL; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_FIXED | + TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; +#ifdef PSB_WORKING_HOST_MMU_ACCESS + man->io_offset = pg->gatt_start; + man->io_size = pg->gatt_pages << PAGE_SHIFT; +#else + man->io_offset = pg->stolen_base; + man->io_size = pg->vram_stolen_size; +#endif + man->gpu_offset = pg->gatt_start; + man->available_caching = TTM_PL_FLAG_UNCACHED | + TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + break; + case TTM_PL_CI: + man->io_addr = NULL; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_FIXED | + TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; + man->io_offset = dev_priv->ci_region_start; + man->io_size = pg->ci_stolen_size; + man->gpu_offset = pg->gatt_start - pg->ci_stolen_size; + man->available_caching = TTM_PL_FLAG_UNCACHED; + man->default_caching = TTM_PL_FLAG_UNCACHED; + break; + case TTM_PL_TT: /* Mappable GATT memory */ + man->io_offset = pg->gatt_start; + man->io_size = pg->gatt_pages << PAGE_SHIFT; + man->io_addr = NULL; +#ifdef PSB_WORKING_HOST_MMU_ACCESS + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; +#else + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_CMA; +#endif + man->available_caching = TTM_PL_FLAG_CACHED | + TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + man->gpu_offset = pg->gatt_start; + break; + case DRM_PSB_MEM_APER: /*MMU memory. Mappable. Not usable for 2D. */ + man->io_offset = pg->gatt_start; + man->io_size = pg->gatt_pages << PAGE_SHIFT; + man->io_addr = NULL; +#ifdef PSB_WORKING_HOST_MMU_ACCESS + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; +#else + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | + TTM_MEMTYPE_FLAG_CMA; +#endif + man->gpu_offset = pg->gatt_start; + man->available_caching = TTM_PL_FLAG_CACHED | + TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; + man->default_caching = TTM_PL_FLAG_WC; + break; + default: + DRM_ERROR("Unsupported memory type %u\n", (unsigned) type); + return -EINVAL; + } + return 0; +} + +static uint32_t psb_evict_mask(struct ttm_buffer_object *bo) +{ + uint32_t cur_placement = bo->mem.flags & ~TTM_PL_MASK_MEM; + + + switch (bo->mem.mem_type) { + case TTM_PL_VRAM: + if (bo->mem.proposed_flags & TTM_PL_FLAG_TT) + return cur_placement | TTM_PL_FLAG_TT; + else + return cur_placement | TTM_PL_FLAG_SYSTEM; + default: + return cur_placement | TTM_PL_FLAG_SYSTEM; + } +} + +static int psb_invalidate_caches(struct ttm_bo_device *bdev, + uint32_t placement) +{ + return 0; +} + +static int psb_move_blit(struct ttm_buffer_object *bo, + bool evict, bool no_wait, + struct ttm_mem_reg *new_mem) +{ + struct drm_psb_private *dev_priv = + container_of(bo->bdev, struct drm_psb_private, bdev); + struct drm_device *dev = dev_priv->dev; + struct ttm_mem_reg *old_mem = &bo->mem; + struct ttm_fence_object *fence; + int dir = 0; + int ret; + + if ((old_mem->mem_type == new_mem->mem_type) && + (new_mem->mm_node->start < + old_mem->mm_node->start + old_mem->mm_node->size)) { + dir = 1; + } + + psb_emit_2d_copy_blit(dev, + old_mem->mm_node->start << PAGE_SHIFT, + new_mem->mm_node->start << PAGE_SHIFT, + new_mem->num_pages, dir); + + ret = ttm_fence_object_create(&dev_priv->fdev, 0, + _PSB_FENCE_TYPE_EXE, + TTM_FENCE_FLAG_EMIT, + &fence); + if (unlikely(ret != 0)) { + psb_idle_2d(dev); + if (fence) + ttm_fence_object_unref(&fence); + } + + ret = ttm_bo_move_accel_cleanup(bo, (void *) fence, + (void *) (unsigned long) + _PSB_FENCE_TYPE_EXE, + evict, no_wait, new_mem); + if (fence) + ttm_fence_object_unref(&fence); + return ret; +} + +/* + * Flip destination ttm into GATT, + * then blit and subsequently move out again. + */ + +static int psb_move_flip(struct ttm_buffer_object *bo, + bool evict, bool interruptible, bool no_wait, + struct ttm_mem_reg *new_mem) +{ + struct ttm_bo_device *bdev = bo->bdev; + struct ttm_mem_reg tmp_mem; + int ret; + + tmp_mem = *new_mem; + tmp_mem.mm_node = NULL; + tmp_mem.proposed_flags = TTM_PL_FLAG_TT; + + ret = ttm_bo_mem_space(bo, &tmp_mem, interruptible, no_wait); + if (ret) + return ret; + ret = ttm_tt_bind(bo->ttm, &tmp_mem); + if (ret) + goto out_cleanup; + ret = psb_move_blit(bo, true, no_wait, &tmp_mem); + if (ret) + goto out_cleanup; + + ret = ttm_bo_move_ttm(bo, evict, no_wait, new_mem); +out_cleanup: + if (tmp_mem.mm_node) { + spin_lock(&bdev->lru_lock); + drm_mm_put_block(tmp_mem.mm_node); + tmp_mem.mm_node = NULL; + spin_unlock(&bdev->lru_lock); + } + return ret; +} + +static int psb_move(struct ttm_buffer_object *bo, + bool evict, bool interruptible, + bool no_wait, struct ttm_mem_reg *new_mem) +{ + struct ttm_mem_reg *old_mem = &bo->mem; + + if (old_mem->mem_type == TTM_PL_SYSTEM) { + return ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); + } else if (new_mem->mem_type == TTM_PL_SYSTEM) { + int ret = psb_move_flip(bo, evict, interruptible, + no_wait, new_mem); + if (unlikely(ret != 0)) { + if (ret == -ERESTART) + return ret; + else + return ttm_bo_move_memcpy(bo, evict, no_wait, + new_mem); + } + } else { + if (psb_move_blit(bo, evict, no_wait, new_mem)) + return ttm_bo_move_memcpy(bo, evict, no_wait, + new_mem); + } + return 0; +} + +static int drm_psb_tbe_populate(struct ttm_backend *backend, + unsigned long num_pages, + struct page **pages, + struct page *dummy_read_page) +{ + struct drm_psb_ttm_backend *psb_be = + container_of(backend, struct drm_psb_ttm_backend, base); + + psb_be->pages = pages; + return 0; +} + +static int drm_psb_tbe_unbind(struct ttm_backend *backend) +{ + struct ttm_bo_device *bdev = backend->bdev; + struct drm_psb_private *dev_priv = + container_of(bdev, struct drm_psb_private, bdev); + struct drm_psb_ttm_backend *psb_be = + container_of(backend, struct drm_psb_ttm_backend, base); + struct psb_mmu_pd *pd = psb_mmu_get_default_pd(dev_priv->mmu); + struct ttm_mem_type_manager *man = &bdev->man[psb_be->mem_type]; + + PSB_DEBUG_RENDER("MMU unbind.\n"); + + if (psb_be->mem_type == TTM_PL_TT) { + uint32_t gatt_p_offset = + (psb_be->offset - man->gpu_offset) >> PAGE_SHIFT; + + (void) psb_gtt_remove_pages(dev_priv->pg, gatt_p_offset, + psb_be->num_pages, + psb_be->desired_tile_stride, + psb_be->hw_tile_stride); + } + + psb_mmu_remove_pages(pd, psb_be->offset, + psb_be->num_pages, + psb_be->desired_tile_stride, + psb_be->hw_tile_stride); + + return 0; +} + +static int drm_psb_tbe_bind(struct ttm_backend *backend, + struct ttm_mem_reg *bo_mem) +{ + struct ttm_bo_device *bdev = backend->bdev; + struct drm_psb_private *dev_priv = + container_of(bdev, struct drm_psb_private, bdev); + struct drm_psb_ttm_backend *psb_be = + container_of(backend, struct drm_psb_ttm_backend, base); + struct psb_mmu_pd *pd = psb_mmu_get_default_pd(dev_priv->mmu); + struct ttm_mem_type_manager *man = &bdev->man[bo_mem->mem_type]; + int type; + int ret = 0; + + psb_be->mem_type = bo_mem->mem_type; + psb_be->num_pages = bo_mem->num_pages; + psb_be->desired_tile_stride = 0; + psb_be->hw_tile_stride = 0; + psb_be->offset = (bo_mem->mm_node->start << PAGE_SHIFT) + + man->gpu_offset; + + type = + (bo_mem-> + flags & TTM_PL_FLAG_CACHED) ? PSB_MMU_CACHED_MEMORY : 0; + + PSB_DEBUG_RENDER("MMU bind.\n"); + if (psb_be->mem_type == TTM_PL_TT) { + uint32_t gatt_p_offset = + (psb_be->offset - man->gpu_offset) >> PAGE_SHIFT; + + ret = psb_gtt_insert_pages(dev_priv->pg, psb_be->pages, + gatt_p_offset, + psb_be->num_pages, + psb_be->desired_tile_stride, + psb_be->hw_tile_stride, type); + } + + ret = psb_mmu_insert_pages(pd, psb_be->pages, + psb_be->offset, psb_be->num_pages, + psb_be->desired_tile_stride, + psb_be->hw_tile_stride, type); + if (ret) + goto out_err; + + return 0; +out_err: + drm_psb_tbe_unbind(backend); + return ret; + +} + +static void drm_psb_tbe_clear(struct ttm_backend *backend) +{ + struct drm_psb_ttm_backend *psb_be = + container_of(backend, struct drm_psb_ttm_backend, base); + + psb_be->pages = NULL; + return; +} + +static void drm_psb_tbe_destroy(struct ttm_backend *backend) +{ + struct drm_psb_ttm_backend *psb_be = + container_of(backend, struct drm_psb_ttm_backend, base); + + if (backend) + drm_free(psb_be, sizeof(*psb_be), DRM_MEM_TTM); +} + +static struct ttm_backend_func psb_ttm_backend = { + .populate = drm_psb_tbe_populate, + .clear = drm_psb_tbe_clear, + .bind = drm_psb_tbe_bind, + .unbind = drm_psb_tbe_unbind, + .destroy = drm_psb_tbe_destroy, +}; + +static struct ttm_backend *drm_psb_tbe_init(struct ttm_bo_device *bdev) +{ + struct drm_psb_ttm_backend *psb_be; + + psb_be = drm_calloc(1, sizeof(*psb_be), DRM_MEM_TTM); + if (!psb_be) + return NULL; + psb_be->pages = NULL; + psb_be->base.func = &psb_ttm_backend; + psb_be->base.bdev = bdev; + return &psb_be->base; +} + +/* + * Use this memory type priority if no eviction is needed. + */ +static uint32_t psb_mem_prios[] = { + TTM_PL_CI, + TTM_PL_VRAM, + TTM_PL_TT, + DRM_PSB_MEM_KERNEL, + DRM_PSB_MEM_MMU, + DRM_PSB_MEM_RASTGEOM, + DRM_PSB_MEM_PDS, + DRM_PSB_MEM_APER, + TTM_PL_SYSTEM +}; + +/* + * Use this memory type priority if need to evict. + */ +static uint32_t psb_busy_prios[] = { + TTM_PL_TT, + TTM_PL_VRAM, + TTM_PL_CI, + DRM_PSB_MEM_KERNEL, + DRM_PSB_MEM_MMU, + DRM_PSB_MEM_RASTGEOM, + DRM_PSB_MEM_PDS, + DRM_PSB_MEM_APER, + TTM_PL_SYSTEM +}; + + +struct ttm_bo_driver psb_ttm_bo_driver = { + .mem_type_prio = psb_mem_prios, + .mem_busy_prio = psb_busy_prios, + .num_mem_type_prio = ARRAY_SIZE(psb_mem_prios), + .num_mem_busy_prio = ARRAY_SIZE(psb_busy_prios), + .create_ttm_backend_entry = &drm_psb_tbe_init, + .invalidate_caches = &psb_invalidate_caches, + .init_mem_type = &psb_init_mem_type, + .evict_flags = &psb_evict_mask, + .move = &psb_move, + .verify_access = &psb_verify_access, + .sync_obj_signaled = &ttm_fence_sync_obj_signaled, + .sync_obj_wait = &ttm_fence_sync_obj_wait, + .sync_obj_flush = &ttm_fence_sync_obj_flush, + .sync_obj_unref = &ttm_fence_sync_obj_unref, + .sync_obj_ref = &ttm_fence_sync_obj_ref +}; --- /dev/null +++ b/drivers/staging/psb/psb_drm.h @@ -0,0 +1,444 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + * develop this driver. + * + **************************************************************************/ +/* + */ + +#ifndef _PSB_DRM_H_ +#define _PSB_DRM_H_ + +#if defined(__linux__) && !defined(__KERNEL__) +#include +#endif + +#include "ttm/ttm_fence_user.h" +#include "ttm/ttm_placement_user.h" + +#define DRM_PSB_SAREA_MAJOR 0 +#define DRM_PSB_SAREA_MINOR 2 +#define PSB_FIXED_SHIFT 16 + +#define DRM_PSB_FIRST_TA_USE_REG 3 +#define DRM_PSB_NUM_TA_USE_REG 6 +#define DRM_PSB_FIRST_RASTER_USE_REG 8 +#define DRM_PSB_NUM_RASTER_USE_REG 7 + +/* + * Public memory types. + */ + +#define DRM_PSB_MEM_MMU TTM_PL_PRIV1 +#define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1 +#define DRM_PSB_MEM_PDS TTM_PL_PRIV2 +#define DRM_PSB_FLAG_MEM_PDS TTM_PL_FLAG_PRIV2 +#define DRM_PSB_MEM_APER TTM_PL_PRIV3 +#define DRM_PSB_FLAG_MEM_APER TTM_PL_FLAG_PRIV3 +#define DRM_PSB_MEM_RASTGEOM TTM_PL_PRIV4 +#define DRM_PSB_FLAG_MEM_RASTGEOM TTM_PL_FLAG_PRIV4 +#define PSB_MEM_RASTGEOM_START 0x30000000 + +typedef int32_t psb_fixed; +typedef uint32_t psb_ufixed; + +static inline int32_t psb_int_to_fixed(int a) +{ + return a * (1 << PSB_FIXED_SHIFT); +} + +static inline uint32_t psb_unsigned_to_ufixed(unsigned int a) +{ + return a << PSB_FIXED_SHIFT; +} + +/*Status of the command sent to the gfx device.*/ +typedef enum { + DRM_CMD_SUCCESS, + DRM_CMD_FAILED, + DRM_CMD_HANG +} drm_cmd_status_t; + +struct drm_psb_scanout { + uint32_t buffer_id; /* DRM buffer object ID */ + uint32_t rotation; /* Rotation as in RR_rotation definitions */ + uint32_t stride; /* Buffer stride in bytes */ + uint32_t depth; /* Buffer depth in bits (NOT) bpp */ + uint32_t width; /* Buffer width in pixels */ + uint32_t height; /* Buffer height in lines */ + int32_t transform[3][3]; /* Buffer composite transform */ + /* (scaling, rot, reflect) */ +}; + +#define DRM_PSB_SAREA_OWNERS 16 +#define DRM_PSB_SAREA_OWNER_2D 0 +#define DRM_PSB_SAREA_OWNER_3D 1 + +#define DRM_PSB_SAREA_SCANOUTS 3 + +struct drm_psb_sarea { + /* Track changes of this data structure */ + + uint32_t major; + uint32_t minor; + + /* Last context to touch part of hw */ + uint32_t ctx_owners[DRM_PSB_SAREA_OWNERS]; + + /* Definition of front- and rotated buffers */ + uint32_t num_scanouts; + struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS]; + + int planeA_x; + int planeA_y; + int planeA_w; + int planeA_h; + int planeB_x; + int planeB_y; + int planeB_w; + int planeB_h; + /* Number of active scanouts */ + uint32_t num_active_scanouts; +}; + +#define PSB_RELOC_MAGIC 0x67676767 +#define PSB_RELOC_SHIFT_MASK 0x0000FFFF +#define PSB_RELOC_SHIFT_SHIFT 0 +#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000 +#define PSB_RELOC_ALSHIFT_SHIFT 16 + +#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated + * buffer + */ +#define PSB_RELOC_OP_2D_OFFSET 1 /* Offset of the indicated + * buffer, relative to 2D + * base address + */ +#define PSB_RELOC_OP_PDS_OFFSET 2 /* Offset of the indicated buffer, + * relative to PDS base address + */ +#define PSB_RELOC_OP_STRIDE 3 /* Stride of the indicated + * buffer (for tiling) + */ +#define PSB_RELOC_OP_USE_OFFSET 4 /* Offset of USE buffer + * relative to base reg + */ +#define PSB_RELOC_OP_USE_REG 5 /* Base reg of USE buffer */ + +struct drm_psb_reloc { + uint32_t reloc_op; + uint32_t where; /* offset in destination buffer */ + uint32_t buffer; /* Buffer reloc applies to */ + uint32_t mask; /* Destination format: */ + uint32_t shift; /* Destination format: */ + uint32_t pre_add; /* Destination format: */ + uint32_t background; /* Destination add */ + uint32_t dst_buffer; /* Destination buffer. Index into buffer_list */ + uint32_t arg0; /* Reloc-op dependant */ + uint32_t arg1; +}; + + +#define PSB_GPU_ACCESS_READ (1ULL << 32) +#define PSB_GPU_ACCESS_WRITE (1ULL << 33) +#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE) + +#define PSB_BO_FLAG_TA (1ULL << 48) +#define PSB_BO_FLAG_SCENE (1ULL << 49) +#define PSB_BO_FLAG_FEEDBACK (1ULL << 50) +#define PSB_BO_FLAG_USSE (1ULL << 51) +#define PSB_BO_FLAG_COMMAND (1ULL << 52) + +#define PSB_ENGINE_2D 0 +#define PSB_ENGINE_VIDEO 1 +#define PSB_ENGINE_RASTERIZER 2 +#define PSB_ENGINE_TA 3 +#define PSB_ENGINE_HPRAST 4 +#define LNC_ENGINE_ENCODE 5 + +#define PSB_DEVICE_SGX 0x1 +#define PSB_DEVICE_DISLAY 0x2 +#define PSB_DEVICE_MSVDX 0x4 +#define PSB_DEVICE_TOPAZ 0x8 + +/* + * For this fence class we have a couple of + * fence types. + */ + +#define _PSB_FENCE_EXE_SHIFT 0 +#define _PSB_FENCE_TA_DONE_SHIFT 1 +#define _PSB_FENCE_RASTER_DONE_SHIFT 2 +#define _PSB_FENCE_SCENE_DONE_SHIFT 3 +#define _PSB_FENCE_FEEDBACK_SHIFT 4 + +#define _PSB_ENGINE_TA_FENCE_TYPES 5 +#define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT) +#define _PSB_FENCE_TYPE_TA_DONE (1 << _PSB_FENCE_TA_DONE_SHIFT) +#define _PSB_FENCE_TYPE_RASTER_DONE (1 << _PSB_FENCE_RASTER_DONE_SHIFT) +#define _PSB_FENCE_TYPE_SCENE_DONE (1 << _PSB_FENCE_SCENE_DONE_SHIFT) +#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT) + +#define PSB_ENGINE_HPRAST 4 +#define PSB_NUM_ENGINES 6 + +#define PSB_TA_FLAG_FIRSTPASS (1 << 0) +#define PSB_TA_FLAG_LASTPASS (1 << 1) + +#define PSB_FEEDBACK_OP_VISTEST (1 << 0) + +struct drm_psb_extension_rep { + int32_t exists; + uint32_t driver_ioctl_offset; + uint32_t sarea_offset; + uint32_t major; + uint32_t minor; + uint32_t pl; +}; + +#define DRM_PSB_EXT_NAME_LEN 128 + +union drm_psb_extension_arg { + char extension[DRM_PSB_EXT_NAME_LEN]; + struct drm_psb_extension_rep rep; +}; + +struct psb_validate_req { + uint64_t set_flags; + uint64_t clear_flags; + uint64_t next; + uint64_t presumed_gpu_offset; + uint32_t buffer_handle; + uint32_t presumed_flags; + uint32_t group; + uint32_t pad64; +}; + +struct psb_validate_rep { + uint64_t gpu_offset; + uint32_t placement; + uint32_t fence_type_mask; +}; + +#define PSB_USE_PRESUMED (1 << 0) + +struct psb_validate_arg { + int handled; + int ret; + union { + struct psb_validate_req req; + struct psb_validate_rep rep; + } d; +}; + +struct drm_psb_scene { + int handle_valid; + uint32_t handle; + uint32_t w; /* also contains msaa info */ + uint32_t h; + uint32_t num_buffers; +}; + +#define DRM_PSB_FENCE_NO_USER (1 << 0) + +struct psb_ttm_fence_rep { + uint32_t handle; + uint32_t fence_class; + uint32_t fence_type; + uint32_t signaled_types; + uint32_t error; +}; + +typedef struct drm_psb_cmdbuf_arg { + uint64_t buffer_list; /* List of buffers to validate */ + uint64_t clip_rects; /* See i915 counterpart */ + uint64_t scene_arg; + uint64_t fence_arg; + + uint32_t ta_flags; + + uint32_t ta_handle; /* TA reg-value pairs */ + uint32_t ta_offset; + uint32_t ta_size; + + uint32_t oom_handle; + uint32_t oom_offset; + uint32_t oom_size; + + uint32_t cmdbuf_handle; /* 2D Command buffer object or, */ + uint32_t cmdbuf_offset; /* rasterizer reg-value pairs */ + uint32_t cmdbuf_size; + + uint32_t reloc_handle; /* Reloc buffer object */ + uint32_t reloc_offset; + uint32_t num_relocs; + + int32_t damage; /* Damage front buffer with cliprects */ + /* Not implemented yet */ + uint32_t fence_flags; + uint32_t engine; + + /* + * Feedback; + */ + + uint32_t feedback_ops; + uint32_t feedback_handle; + uint32_t feedback_offset; + uint32_t feedback_breakpoints; + uint32_t feedback_size; +}drm_psb_cmdbuf_arg_t; + +struct drm_psb_xhw_init_arg { + uint32_t operation; + uint32_t buffer_handle; +}; + +/* + * Feedback components: + */ + +/* + * Vistest component. The number of these in the feedback buffer + * equals the number of vistest breakpoints + 1. + * This is currently the only feedback component. + */ + +struct drm_psb_vistest { + uint32_t vt[8]; +}; + +#define PSB_HW_COOKIE_SIZE 16 +#define PSB_HW_FEEDBACK_SIZE 8 +#define PSB_HW_OOM_CMD_SIZE (6 + DRM_PSB_NUM_RASTER_USE_REG * 2) + +struct drm_psb_xhw_arg { + uint32_t op; + int ret; + uint32_t irq_op; + uint32_t issue_irq; + uint32_t cookie[PSB_HW_COOKIE_SIZE]; + union { + struct { + uint32_t w; /* also contains msaa info */ + uint32_t h; + uint32_t size; + uint32_t clear_p_start; + uint32_t clear_num_pages; + } si; + struct { + uint32_t fire_flags; + uint32_t hw_context; + uint32_t offset; + uint32_t engine; + uint32_t flags; + uint32_t rca; + uint32_t num_oom_cmds; + uint32_t oom_cmds[PSB_HW_OOM_CMD_SIZE]; + } sb; + struct { + uint32_t pages; + uint32_t size; + uint32_t ta_min_size; + } bi; + struct { + uint32_t bca; + uint32_t rca; + uint32_t flags; + } oom; + struct { + uint32_t pt_offset; + uint32_t param_offset; + uint32_t flags; + } bl; + struct { + uint32_t value; + } cl; + uint32_t feedback[PSB_HW_FEEDBACK_SIZE]; + } arg; +}; + +/* Controlling the kernel modesetting buffers */ + +#define DRM_PSB_KMS_OFF 0x00 +#define DRM_PSB_KMS_ON 0x01 +#define DRM_PSB_VT_LEAVE 0x02 +#define DRM_PSB_VT_ENTER 0x03 +#define DRM_PSB_XHW_INIT 0x04 +#define DRM_PSB_XHW 0x05 +#define DRM_PSB_EXTENSION 0x06 + +/* + * Xhw commands. + */ + +#define PSB_XHW_INIT 0x00 +#define PSB_XHW_TAKEDOWN 0x01 + +#define PSB_XHW_FIRE_RASTER 0x00 +#define PSB_XHW_SCENE_INFO 0x01 +#define PSB_XHW_SCENE_BIND_FIRE 0x02 +#define PSB_XHW_TA_MEM_INFO 0x03 +#define PSB_XHW_RESET_DPM 0x04 +#define PSB_XHW_OOM 0x05 +#define PSB_XHW_TERMINATE 0x06 +#define PSB_XHW_VISTEST 0x07 +#define PSB_XHW_RESUME 0x08 +#define PSB_XHW_TA_MEM_LOAD 0x09 +#define PSB_XHW_CHECK_LOCKUP 0x0a + +#define PSB_SCENE_FLAG_DIRTY (1 << 0) +#define PSB_SCENE_FLAG_COMPLETE (1 << 1) +#define PSB_SCENE_FLAG_SETUP (1 << 2) +#define PSB_SCENE_FLAG_SETUP_ONLY (1 << 3) +#define PSB_SCENE_FLAG_CLEARED (1 << 4) + +#define PSB_TA_MEM_FLAG_TA (1 << 0) +#define PSB_TA_MEM_FLAG_RASTER (1 << 1) +#define PSB_TA_MEM_FLAG_HOSTA (1 << 2) +#define PSB_TA_MEM_FLAG_HOSTD (1 << 3) +#define PSB_TA_MEM_FLAG_INIT (1 << 4) +#define PSB_TA_MEM_FLAG_NEW_PT_OFFSET (1 << 5) + +/*Raster fire will deallocate memory */ +#define PSB_FIRE_FLAG_RASTER_DEALLOC (1 << 0) +/*Isp reset needed due to change in ZLS format */ +#define PSB_FIRE_FLAG_NEEDS_ISP_RESET (1 << 1) +/*These are set by Xpsb. */ +#define PSB_FIRE_FLAG_XHW_MASK 0xff000000 +/*The task has had at least one OOM and Xpsb will + send back messages on each fire. */ +#define PSB_FIRE_FLAG_XHW_OOM (1 << 24) + +#define PSB_SCENE_ENGINE_TA 0 +#define PSB_SCENE_ENGINE_RASTER 1 +#define PSB_SCENE_NUM_ENGINES 2 + +#define PSB_LOCKUP_RASTER (1 << 0) +#define PSB_LOCKUP_TA (1 << 1) + +struct drm_psb_dev_info_arg { + uint32_t num_use_attribute_registers; +}; +#define DRM_PSB_DEVINFO 0x01 + + +#endif --- /dev/null +++ b/drivers/staging/psb/psb_drv.c @@ -0,0 +1,1447 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + * develop this driver. + * + **************************************************************************/ +/* + */ + +#include +#include +#include "psb_drm.h" +#include "psb_drv.h" +#include "psb_reg.h" +#include "intel_reg.h" +#include "psb_msvdx.h" +#include "lnc_topaz.h" +#include +#include "psb_scene.h" + +#include +#include +#include + +int drm_psb_debug; +EXPORT_SYMBOL(drm_psb_debug); +static int drm_psb_trap_pagefaults; +static int drm_psb_clock_gating; +static int drm_psb_ta_mem_size = 32 * 1024; + +int drm_psb_disable_vsync; +int drm_psb_no_fb; +int drm_psb_force_pipeb; +int drm_idle_check_interval = 5; +int drm_psb_ospm; + +MODULE_PARM_DESC(debug, "Enable debug output"); +MODULE_PARM_DESC(clock_gating, "clock gating"); +MODULE_PARM_DESC(no_fb, "Disable FBdev"); +MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults"); +MODULE_PARM_DESC(disable_vsync, "Disable vsync interrupts"); +MODULE_PARM_DESC(force_pipeb, "Forces PIPEB to become primary fb"); +MODULE_PARM_DESC(ta_mem_size, "TA memory size in kiB"); +MODULE_PARM_DESC(ospm, "switch for ospm support"); +module_param_named(debug, drm_psb_debug, int, 0600); +module_param_named(clock_gating, drm_psb_clock_gating, int, 0600); +module_param_named(no_fb, drm_psb_no_fb, int, 0600); +module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600); +module_param_named(disable_vsync, drm_psb_disable_vsync, int, 0600); +module_param_named(force_pipeb, drm_psb_force_pipeb, int, 0600); +module_param_named(ta_mem_size, drm_psb_ta_mem_size, int, 0600); +module_param_named(ospm, drm_psb_ospm, int, 0600); + +#ifndef CONFIG_X86_PAT +#warning "Don't build this driver without PAT support!!!" +#endif + +#define psb_PCI_IDS \ + {0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108}, \ + {0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109}, \ + {0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, \ + {0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, \ + {0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, \ + {0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, \ + {0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, \ + {0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, \ + {0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, \ + {0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100}, \ + {0, 0, 0} + +static struct pci_device_id pciidlist[] = { + psb_PCI_IDS +}; + +/* + * Standard IOCTLs. + */ + +#define DRM_IOCTL_PSB_KMS_OFF DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE) +#define DRM_IOCTL_PSB_KMS_ON DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE) +#define DRM_IOCTL_PSB_VT_LEAVE DRM_IO(DRM_PSB_VT_LEAVE + DRM_COMMAND_BASE) +#define DRM_IOCTL_PSB_VT_ENTER DRM_IO(DRM_PSB_VT_ENTER + DRM_COMMAND_BASE) +#define DRM_IOCTL_PSB_XHW_INIT DRM_IOW(DRM_PSB_XHW_INIT + DRM_COMMAND_BASE, \ + struct drm_psb_xhw_init_arg) +#define DRM_IOCTL_PSB_XHW DRM_IO(DRM_PSB_XHW + DRM_COMMAND_BASE) +#define DRM_IOCTL_PSB_EXTENSION DRM_IOWR(DRM_PSB_EXTENSION + DRM_COMMAND_BASE, \ + union drm_psb_extension_arg) +/* + * TTM execbuf extension. + */ + +#define DRM_PSB_CMDBUF (DRM_PSB_EXTENSION + 1) +#define DRM_PSB_SCENE_UNREF (DRM_PSB_CMDBUF + 1) +#define DRM_IOCTL_PSB_CMDBUF DRM_IOW(DRM_PSB_CMDBUF + DRM_COMMAND_BASE, \ + struct drm_psb_cmdbuf_arg) +#define DRM_IOCTL_PSB_SCENE_UNREF DRM_IOW(DRM_PSB_SCENE_UNREF + DRM_COMMAND_BASE, \ + struct drm_psb_scene) +#define DRM_IOCTL_PSB_KMS_OFF DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE) +#define DRM_IOCTL_PSB_KMS_ON DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE) +#define DRM_IOCTL_PSB_EXTENSION DRM_IOWR(DRM_PSB_EXTENSION + DRM_COMMAND_BASE, \ + union drm_psb_extension_arg) +/* + * TTM placement user extension. + */ + +#define DRM_PSB_PLACEMENT_OFFSET (DRM_PSB_SCENE_UNREF + 1) + +#define DRM_PSB_TTM_PL_CREATE (TTM_PL_CREATE + DRM_PSB_PLACEMENT_OFFSET) +#define DRM_PSB_TTM_PL_REFERENCE (TTM_PL_REFERENCE + DRM_PSB_PLACEMENT_OFFSET) +#define DRM_PSB_TTM_PL_UNREF (TTM_PL_UNREF + DRM_PSB_PLACEMENT_OFFSET) +#define DRM_PSB_TTM_PL_SYNCCPU (TTM_PL_SYNCCPU + DRM_PSB_PLACEMENT_OFFSET) +#define DRM_PSB_TTM_PL_WAITIDLE (TTM_PL_WAITIDLE + DRM_PSB_PLACEMENT_OFFSET) +#define DRM_PSB_TTM_PL_SETSTATUS (TTM_PL_SETSTATUS + DRM_PSB_PLACEMENT_OFFSET) + +/* + * TTM fence extension. + */ + +#define DRM_PSB_FENCE_OFFSET (DRM_PSB_TTM_PL_SETSTATUS + 1) +#define DRM_PSB_TTM_FENCE_SIGNALED (TTM_FENCE_SIGNALED + DRM_PSB_FENCE_OFFSET) +#define DRM_PSB_TTM_FENCE_FINISH (TTM_FENCE_FINISH + DRM_PSB_FENCE_OFFSET) +#define DRM_PSB_TTM_FENCE_UNREF (TTM_FENCE_UNREF + DRM_PSB_FENCE_OFFSET) + +#define DRM_IOCTL_PSB_TTM_PL_CREATE \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_CREATE,\ + union ttm_pl_create_arg) +#define DRM_IOCTL_PSB_TTM_PL_REFERENCE \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_REFERENCE,\ + union ttm_pl_reference_arg) +#define DRM_IOCTL_PSB_TTM_PL_UNREF \ + DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_UNREF,\ + struct ttm_pl_reference_req) +#define DRM_IOCTL_PSB_TTM_PL_SYNCCPU \ + DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_SYNCCPU,\ + struct ttm_pl_synccpu_arg) +#define DRM_IOCTL_PSB_TTM_PL_WAITIDLE \ + DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_WAITIDLE,\ + struct ttm_pl_waitidle_arg) +#define DRM_IOCTL_PSB_TTM_PL_SETSTATUS \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_SETSTATUS,\ + union ttm_pl_setstatus_arg) +#define DRM_IOCTL_PSB_TTM_FENCE_SIGNALED \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_SIGNALED, \ + union ttm_fence_signaled_arg) +#define DRM_IOCTL_PSB_TTM_FENCE_FINISH \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_FINISH, \ + union ttm_fence_finish_arg) +#define DRM_IOCTL_PSB_TTM_FENCE_UNREF \ + DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_UNREF, \ + struct ttm_fence_unref_arg) + +static int psb_vt_leave_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +static int psb_vt_enter_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); + +#define PSB_IOCTL_DEF(ioctl, func, flags) \ + [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, func, flags} + +static struct drm_ioctl_desc psb_ioctls[] = { + PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl, + DRM_ROOT_ONLY), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON, psbfb_kms_on_ioctl, DRM_ROOT_ONLY), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_LEAVE, psb_vt_leave_ioctl, + DRM_ROOT_ONLY), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_ENTER, psb_vt_enter_ioctl, DRM_ROOT_ONLY), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_XHW_INIT, psb_xhw_init_ioctl, + DRM_ROOT_ONLY), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_XHW, psb_xhw_ioctl, DRM_ROOT_ONLY), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_EXTENSION, psb_extension_ioctl, DRM_AUTH), + + PSB_IOCTL_DEF(DRM_IOCTL_PSB_CMDBUF, psb_cmdbuf_ioctl, DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_SCENE_UNREF, drm_psb_scene_unref_ioctl, + DRM_AUTH), + + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_CREATE, psb_pl_create_ioctl, + DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_REFERENCE, psb_pl_reference_ioctl, + DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_UNREF, psb_pl_unref_ioctl, + DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_SYNCCPU, psb_pl_synccpu_ioctl, + DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_WAITIDLE, psb_pl_waitidle_ioctl, + DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_SETSTATUS, psb_pl_setstatus_ioctl, + DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_SIGNALED, + psb_fence_signaled_ioctl, DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_FINISH, psb_fence_finish_ioctl, + DRM_AUTH), + PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_UNREF, psb_fence_unref_ioctl, + DRM_AUTH) +}; + +static int psb_max_ioctl = DRM_ARRAY_SIZE(psb_ioctls); + +static void get_ci_info(struct drm_psb_private *dev_priv) +{ + struct pci_dev *pdev; + + pdev = pci_get_subsys(0x8086, 0x080b, 0, 0, NULL); + if (pdev == NULL) { + /* IF no pci_device we set size & addr to 0, no ci + * share buffer can be created */ + dev_priv->ci_region_start = 0; + dev_priv->ci_region_size = 0; + printk(KERN_ERR "can't find CI device, no ci share buffer\n"); + return; + } + + dev_priv->ci_region_start = pci_resource_start(pdev, 1); + dev_priv->ci_region_size = pci_resource_len(pdev, 1); + + printk(KERN_INFO "ci_region_start %x ci_region_size %d\n", + dev_priv->ci_region_start, dev_priv->ci_region_size); + + pci_dev_put(pdev); + + return; +} + +static int dri_library_name(struct drm_device *dev, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "psb\n"); +} + +static void psb_set_uopt(struct drm_psb_uopt *uopt) +{ + uopt->clock_gating = drm_psb_clock_gating; +} + +static void psb_lastclose(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + + if (!dev->dev_private) + return; + + if (dev_priv->ta_mem) + psb_ta_mem_unref(&dev_priv->ta_mem); + mutex_lock(&dev_priv->cmdbuf_mutex); + if (dev_priv->context.buffers) { + vfree(dev_priv->context.buffers); + dev_priv->context.buffers = NULL; + } + mutex_unlock(&dev_priv->cmdbuf_mutex); +} + +static void psb_do_takedown(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + struct ttm_bo_device *bdev = &dev_priv->bdev; + + + if (dev_priv->have_mem_rastgeom) { + ttm_bo_clean_mm(bdev, DRM_PSB_MEM_RASTGEOM); + dev_priv->have_mem_rastgeom = 0; + } + if (dev_priv->have_mem_mmu) { + ttm_bo_clean_mm(bdev, DRM_PSB_MEM_MMU); + dev_priv->have_mem_mmu = 0; + } + if (dev_priv->have_mem_aper) { + ttm_bo_clean_mm(bdev, DRM_PSB_MEM_APER); + dev_priv->have_mem_aper = 0; + } + if (dev_priv->have_tt) { + ttm_bo_clean_mm(bdev, TTM_PL_TT); + dev_priv->have_tt = 0; + } + if (dev_priv->have_vram) { + ttm_bo_clean_mm(bdev, TTM_PL_VRAM); + dev_priv->have_vram = 0; + } + if (dev_priv->have_camera) { + ttm_bo_clean_mm(bdev, TTM_PL_CI); + dev_priv->have_camera = 0; + } + + if (dev_priv->has_msvdx) + psb_msvdx_uninit(dev); + + if (IS_MRST(dev)) { + if (dev_priv->has_topaz) + lnc_topaz_uninit(dev); + } + + if (dev_priv->comm) { + kunmap(dev_priv->comm_page); + dev_priv->comm = NULL; + } + if (dev_priv->comm_page) { + __free_page(dev_priv->comm_page); + dev_priv->comm_page = NULL; + } +} + +void psb_clockgating(struct drm_psb_private *dev_priv) +{ + uint32_t clock_gating; + + if (dev_priv->uopt.clock_gating == 1) { + PSB_DEBUG_INIT("Disabling clock gating.\n"); + + clock_gating = (_PSB_C_CLKGATECTL_CLKG_DISABLED << + _PSB_C_CLKGATECTL_2D_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_DISABLED << + _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_DISABLED << + _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_DISABLED << + _PSB_C_CLKGATECTL_TA_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_DISABLED << + _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_DISABLED << + _PSB_C_CLKGATECTL_USE_CLKG_SHIFT); + + } else if (dev_priv->uopt.clock_gating == 2) { + PSB_DEBUG_INIT("Enabling clock gating.\n"); + + clock_gating = (_PSB_C_CLKGATECTL_CLKG_AUTO << + _PSB_C_CLKGATECTL_2D_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_AUTO << + _PSB_C_CLKGATECTL_ISP_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_AUTO << + _PSB_C_CLKGATECTL_TSP_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_AUTO << + _PSB_C_CLKGATECTL_TA_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_AUTO << + _PSB_C_CLKGATECTL_DPM_CLKG_SHIFT) | + (_PSB_C_CLKGATECTL_CLKG_AUTO << + _PSB_C_CLKGATECTL_USE_CLKG_SHIFT); + } else + clock_gating = PSB_RSGX32(PSB_CR_CLKGATECTL); + +#ifdef FIX_TG_2D_CLOCKGATE + clock_gating &= ~_PSB_C_CLKGATECTL_2D_CLKG_MASK; + clock_gating |= (_PSB_C_CLKGATECTL_CLKG_DISABLED << + _PSB_C_CLKGATECTL_2D_CLKG_SHIFT); +#endif + PSB_WSGX32(clock_gating, PSB_CR_CLKGATECTL); + (void) PSB_RSGX32(PSB_CR_CLKGATECTL); +} + +#define FB_REG06 0xD0810600 +#define FB_MIPI_DISABLE BIT11 +#define FB_REG09 0xD0810900 +#define FB_SKU_MASK (BIT12|BIT13|BIT14) +#define FB_SKU_SHIFT 12 +#define FB_SKU_100 0 +#define FB_SKU_100L 1 +#define FB_SKU_83 2 +#if 1 /* FIXME remove it after PO */ +#define FB_GFX_CLK_DIVIDE_MASK (BIT20|BIT21|BIT22) +#define FB_GFX_CLK_DIVIDE_SHIFT 20 +#define FB_VED_CLK_DIVIDE_MASK (BIT23|BIT24) +#define FB_VED_CLK_DIVIDE_SHIFT 23 +#define FB_VEC_CLK_DIVIDE_MASK (BIT25|BIT26) +#define FB_VEC_CLK_DIVIDE_SHIFT 25 +#endif /* FIXME remove it after PO */ + + +void mrst_get_fuse_settings(struct drm_psb_private *dev_priv) +{ + struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0); + uint32_t fuse_value = 0; + uint32_t fuse_value_tmp = 0; + + pci_write_config_dword(pci_root, 0xD0, FB_REG06); + pci_read_config_dword(pci_root, 0xD4, &fuse_value); + + dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE; + + DRM_INFO("internal display is %s\n", + dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display"); + + pci_write_config_dword(pci_root, 0xD0, FB_REG09); + pci_read_config_dword(pci_root, 0xD4, &fuse_value); + + DRM_INFO("SKU values is 0x%x. \n", fuse_value); + fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT; + + switch (fuse_value_tmp) { + case FB_SKU_100: + DRM_INFO("SKU values is SKU_100. LNC core clock is 200MHz. \n"); + dev_priv->sku_100 = true; + break; + case FB_SKU_100L: + DRM_INFO("SKU values is SKU_100L. LNC core clock is 100MHz. \n"); + dev_priv->sku_100L = true; + break; + case FB_SKU_83: + DRM_INFO("SKU values is SKU_83. LNC core clock is 166MHz. \n"); + dev_priv->sku_83 = true; + break; + default: + DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", + fuse_value_tmp); + } + +#if 1 /* FIXME remove it after PO */ + fuse_value_tmp = (fuse_value & FB_GFX_CLK_DIVIDE_MASK) >> FB_GFX_CLK_DIVIDE_SHIFT; + + switch (fuse_value_tmp) { + case 0: + DRM_INFO("Gfx clk : core clk = 1:1. \n"); + break; + case 1: + DRM_INFO("Gfx clk : core clk = 4:3. \n"); + break; + case 2: + DRM_INFO("Gfx clk : core clk = 8:5. \n"); + break; + case 3: + DRM_INFO("Gfx clk : core clk = 2:1. \n"); + break; + case 5: + DRM_INFO("Gfx clk : core clk = 8:3. \n"); + break; + case 6: + DRM_INFO("Gfx clk : core clk = 16:5. \n"); + break; + default: + DRM_ERROR("Invalid GFX CLK DIVIDE values, value = 0x%08x\n", + fuse_value_tmp); + } + + fuse_value_tmp = (fuse_value & FB_VED_CLK_DIVIDE_MASK) >> FB_VED_CLK_DIVIDE_SHIFT; + + switch (fuse_value_tmp) { + case 0: + DRM_INFO("Ved clk : core clk = 1:1. \n"); + break; + case 1: + DRM_INFO("Ved clk : core clk = 4:3. \n"); + break; + case 2: + DRM_INFO("Ved clk : core clk = 8:5. \n"); + break; + case 3: + DRM_INFO("Ved clk : core clk = 2:1. \n"); + break; + default: + DRM_ERROR("Invalid VED CLK DIVIDE values, value = 0x%08x\n", + fuse_value_tmp); + } + + fuse_value_tmp = (fuse_value & FB_VEC_CLK_DIVIDE_MASK) >> FB_VEC_CLK_DIVIDE_SHIFT; + + switch (fuse_value_tmp) { + case 0: + DRM_INFO("Vec clk : core clk = 1:1. \n"); + break; + case 1: + DRM_INFO("Vec clk : core clk = 4:3. \n"); + break; + case 2: + DRM_INFO("Vec clk : core clk = 8:5. \n"); + break; + case 3: + DRM_INFO("Vec clk : core clk = 2:1. \n"); + break; + default: + DRM_ERROR("Invalid VEC CLK DIVIDE values, value = 0x%08x\n", + fuse_value_tmp); + } +#endif /* FIXME remove it after PO */ + + return; +} + +static int psb_do_init(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + struct ttm_bo_device *bdev = &dev_priv->bdev; + struct psb_gtt *pg = dev_priv->pg; + + uint32_t stolen_gtt; + uint32_t tt_start; + uint32_t tt_pages; + + int ret = -ENOMEM; + + dev_priv->ta_mem_pages = + PSB_ALIGN_TO(drm_psb_ta_mem_size * 1024, + PAGE_SIZE) >> PAGE_SHIFT; + dev_priv->comm_page = alloc_page(GFP_KERNEL); + if (!dev_priv->comm_page) + goto out_err; + + dev_priv->comm = kmap(dev_priv->comm_page); + memset((void *) dev_priv->comm, 0, PAGE_SIZE); + + set_pages_uc(dev_priv->comm_page, 1); + + /* + * Initialize sequence numbers for the different command + * submission mechanisms. + */ + + dev_priv->sequence[PSB_ENGINE_2D] = 0; + dev_priv->sequence[PSB_ENGINE_RASTERIZER] = 0; + dev_priv->sequence[PSB_ENGINE_TA] = 0; + dev_priv->sequence[PSB_ENGINE_HPRAST] = 0; + + if (pg->gatt_start & 0x0FFFFFFF) { + DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n"); + ret = -EINVAL; + goto out_err; + } + + stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4; + stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT; + stolen_gtt = + (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages; + + dev_priv->gatt_free_offset = pg->gatt_start + + (stolen_gtt << PAGE_SHIFT) * 1024; + + /* + * Insert a cache-coherent communications page in mmu space + * just after the stolen area. Will be used for fencing etc. + */ + + dev_priv->comm_mmu_offset = dev_priv->gatt_free_offset; + dev_priv->gatt_free_offset += PAGE_SIZE; + + ret = psb_mmu_insert_pages(psb_mmu_get_default_pd(dev_priv->mmu), + &dev_priv->comm_page, + dev_priv->comm_mmu_offset, 1, 0, 0, 0); + + if (ret) + goto out_err; + + if (1 || drm_debug) { + uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID); + uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION); + DRM_INFO("SGX core id = 0x%08x\n", core_id); + DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n", + (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >> + _PSB_CC_REVISION_MAJOR_SHIFT, + (core_rev & _PSB_CC_REVISION_MINOR_MASK) >> + _PSB_CC_REVISION_MINOR_SHIFT); + DRM_INFO + ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n", + (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >> + _PSB_CC_REVISION_MAINTENANCE_SHIFT, + (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >> + _PSB_CC_REVISION_DESIGNER_SHIFT); + } + + spin_lock_init(&dev_priv->irqmask_lock); + dev_priv->fence0_irq_on = 0; + + tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ? + pg->gatt_pages : PSB_TT_PRIV0_PLIMIT; + tt_start = dev_priv->gatt_free_offset - pg->gatt_start; + tt_pages -= tt_start >> PAGE_SHIFT; + + if (!ttm_bo_init_mm(bdev, TTM_PL_VRAM, 0, + pg->vram_stolen_size >> PAGE_SHIFT)) { + dev_priv->have_vram = 1; + } + + if (!ttm_bo_init_mm(bdev, TTM_PL_CI, 0, + dev_priv->ci_region_size >> PAGE_SHIFT)) { + dev_priv->have_camera = 1; + } + + if (!ttm_bo_init_mm(bdev, TTM_PL_TT, tt_start >> PAGE_SHIFT, + tt_pages)) { + dev_priv->have_tt = 1; + } + + if (!ttm_bo_init_mm(bdev, DRM_PSB_MEM_MMU, 0x00000000, + (pg->gatt_start - PSB_MEM_MMU_START - + pg->ci_stolen_size) >> PAGE_SHIFT)) { + dev_priv->have_mem_mmu = 1; + } + + if (!ttm_bo_init_mm(bdev, DRM_PSB_MEM_RASTGEOM, 0x00000000, + (PSB_MEM_MMU_START - + PSB_MEM_RASTGEOM_START) >> PAGE_SHIFT)) { + dev_priv->have_mem_rastgeom = 1; + } +#if 0 + if (pg->gatt_pages > PSB_TT_PRIV0_PLIMIT) { + if (!ttm_bo_init_mm + (bdev, DRM_PSB_MEM_APER, PSB_TT_PRIV0_PLIMIT, + pg->gatt_pages - PSB_TT_PRIV0_PLIMIT, 1)) { + dev_priv->have_mem_aper = 1; + } + } +#endif + + PSB_DEBUG_INIT("Init MSVDX\n"); + dev_priv->has_msvdx = 1; + if (psb_msvdx_init(dev)) + dev_priv->has_msvdx = 0; + + if (IS_MRST(dev)) { + PSB_DEBUG_INIT("Init Topaz\n"); + dev_priv->has_topaz = 1; + if (lnc_topaz_init(dev)) + dev_priv->has_topaz = 0; + } + return 0; +out_err: + psb_do_takedown(dev); + return ret; +} + +static int psb_driver_unload(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + + if (drm_psb_no_fb == 0) + psb_modeset_cleanup(dev); + + if (dev_priv) { + struct ttm_bo_device *bdev = &dev_priv->bdev; + + psb_watchdog_takedown(dev_priv); + psb_do_takedown(dev); + psb_xhw_takedown(dev_priv); + psb_scheduler_takedown(&dev_priv->scheduler); + + if (dev_priv->have_mem_pds) { + ttm_bo_clean_mm(bdev, DRM_PSB_MEM_PDS); + dev_priv->have_mem_pds = 0; + } + if (dev_priv->have_mem_kernel) { + ttm_bo_clean_mm(bdev, DRM_PSB_MEM_KERNEL); + dev_priv->have_mem_kernel = 0; + } + + if (dev_priv->pf_pd) { + psb_mmu_free_pagedir(dev_priv->pf_pd); + dev_priv->pf_pd = NULL; + } + if (dev_priv->mmu) { + struct psb_gtt *pg = dev_priv->pg; + + down_read(&pg->sem); + psb_mmu_remove_pfn_sequence(psb_mmu_get_default_pd + (dev_priv->mmu), + pg->gatt_start, + pg->vram_stolen_size >> + PAGE_SHIFT); + psb_mmu_remove_pfn_sequence(psb_mmu_get_default_pd + (dev_priv->mmu), + pg->gatt_start - pg->ci_stolen_size, + pg->ci_stolen_size >> + PAGE_SHIFT); + up_read(&pg->sem); + psb_mmu_driver_takedown(dev_priv->mmu); + dev_priv->mmu = NULL; + } + psb_gtt_takedown(dev_priv->pg, 1); + if (dev_priv->scratch_page) { + __free_page(dev_priv->scratch_page); + dev_priv->scratch_page = NULL; + } + if (dev_priv->has_bo_device) { + ttm_bo_device_release(&dev_priv->bdev); + dev_priv->has_bo_device = 0; + } + if (dev_priv->has_fence_device) { + ttm_fence_device_release(&dev_priv->fdev); + dev_priv->has_fence_device = 0; + } + if (dev_priv->vdc_reg) { + iounmap(dev_priv->vdc_reg); + dev_priv->vdc_reg = NULL; + } + if (dev_priv->sgx_reg) { + iounmap(dev_priv->sgx_reg); + dev_priv->sgx_reg = NULL; + } + if (dev_priv->msvdx_reg) { + iounmap(dev_priv->msvdx_reg); + dev_priv->msvdx_reg = NULL; + } + + if (IS_MRST(dev)) { + if (dev_priv->topaz_reg) { + iounmap(dev_priv->topaz_reg); + dev_priv->topaz_reg = NULL; + } + } + + if (dev_priv->tdev) + ttm_object_device_release(&dev_priv->tdev); + + if (dev_priv->has_global) + psb_ttm_global_release(dev_priv); + + drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); + dev->dev_private = NULL; + } + return 0; +} + + +static int psb_driver_load(struct drm_device *dev, unsigned long chipset) +{ + struct drm_psb_private *dev_priv; + struct ttm_bo_device *bdev; + unsigned long resource_start; + struct psb_gtt *pg; + int ret = -ENOMEM; + + if (IS_MRST(dev)) + DRM_INFO("Run drivers on Moorestown platform!\n"); + else + DRM_INFO("Run drivers on Poulsbo platform!\n"); + + dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER); + if (dev_priv == NULL) + return -ENOMEM; + + dev_priv->dev = dev; + bdev = &dev_priv->bdev; + + ret = psb_ttm_global_init(dev_priv); + if (unlikely(ret != 0)) + goto out_err; + dev_priv->has_global = 1; + + dev_priv->tdev = ttm_object_device_init + (dev_priv->mem_global_ref.object, PSB_OBJECT_HASH_ORDER); + if (unlikely(dev_priv->tdev == NULL)) + goto out_err; + + mutex_init(&dev_priv->temp_mem); + mutex_init(&dev_priv->cmdbuf_mutex); + mutex_init(&dev_priv->reset_mutex); + INIT_LIST_HEAD(&dev_priv->context.validate_list); + INIT_LIST_HEAD(&dev_priv->context.kern_validate_list); + psb_init_disallowed(); + +#ifdef FIX_TG_16 + atomic_set(&dev_priv->lock_2d, 0); + atomic_set(&dev_priv->ta_wait_2d, 0); + atomic_set(&dev_priv->ta_wait_2d_irq, 0); + atomic_set(&dev_priv->waiters_2d, 0);; + DRM_INIT_WAITQUEUE(&dev_priv->queue_2d); +#else + mutex_init(&dev_priv->mutex_2d); +#endif + + spin_lock_init(&dev_priv->reloc_lock); + + DRM_INIT_WAITQUEUE(&dev_priv->rel_mapped_queue); + DRM_INIT_WAITQUEUE(&dev_priv->event_2d_queue); + + dev->dev_private = (void *) dev_priv; + dev_priv->chipset = chipset; + psb_set_uopt(&dev_priv->uopt); + + PSB_DEBUG_GENERAL("Init watchdog and scheduler\n"); + psb_watchdog_init(dev_priv); + psb_scheduler_init(dev, &dev_priv->scheduler); + + + PSB_DEBUG_INIT("Mapping MMIO\n"); + resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE); + + if (IS_MRST(dev)) + dev_priv->msvdx_reg = + ioremap(resource_start + MRST_MSVDX_OFFSET, + PSB_MSVDX_SIZE); + else + dev_priv->msvdx_reg = + ioremap(resource_start + PSB_MSVDX_OFFSET, + PSB_MSVDX_SIZE); + + if (!dev_priv->msvdx_reg) + goto out_err; + + if (IS_MRST(dev)) { + dev_priv->topaz_reg = + ioremap(resource_start + LNC_TOPAZ_OFFSET, + LNC_TOPAZ_SIZE); + if (!dev_priv->topaz_reg) + goto out_err; + } + + dev_priv->vdc_reg = + ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE); + if (!dev_priv->vdc_reg) + goto out_err; + + if (IS_MRST(dev)) + dev_priv->sgx_reg = + ioremap(resource_start + MRST_SGX_OFFSET, + PSB_SGX_SIZE); + else + dev_priv->sgx_reg = + ioremap(resource_start + PSB_SGX_OFFSET, PSB_SGX_SIZE); + + if (!dev_priv->sgx_reg) + goto out_err; + + if (IS_MRST(dev)) + mrst_get_fuse_settings(dev_priv); + + PSB_DEBUG_INIT("Init TTM fence and BO driver\n"); + + get_ci_info(dev_priv); + + psb_clockgating(dev_priv); + + ret = psb_ttm_fence_device_init(&dev_priv->fdev); + if (unlikely(ret != 0)) + goto out_err; + + dev_priv->has_fence_device = 1; + ret = ttm_bo_device_init(bdev, + dev_priv->mem_global_ref.object, + &psb_ttm_bo_driver, + DRM_PSB_FILE_PAGE_OFFSET); + if (unlikely(ret != 0)) + goto out_err; + dev_priv->has_bo_device = 1; + ttm_lock_init(&dev_priv->ttm_lock); + + ret = -ENOMEM; + + dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO); + if (!dev_priv->scratch_page) + goto out_err; + + set_pages_uc(dev_priv->scratch_page, 1); + + dev_priv->pg = psb_gtt_alloc(dev); + if (!dev_priv->pg) + goto out_err; + + ret = psb_gtt_init(dev_priv->pg, 0); + if (ret) + goto out_err; + + dev_priv->mmu = psb_mmu_driver_init(dev_priv->sgx_reg, + drm_psb_trap_pagefaults, 0, + dev_priv); + if (!dev_priv->mmu) + goto out_err; + + pg = dev_priv->pg; + + /* + * Make sgx MMU aware of the stolen memory area we call VRAM. + */ + + down_read(&pg->sem); + ret = + psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd + (dev_priv->mmu), + pg->stolen_base >> PAGE_SHIFT, + pg->gatt_start, + pg->vram_stolen_size >> PAGE_SHIFT, 0); + up_read(&pg->sem); + if (ret) + goto out_err; + + /* + * Make sgx MMU aware of the stolen memory area we call VRAM. + */ + + down_read(&pg->sem); + ret = + psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd + (dev_priv->mmu), + dev_priv->ci_region_start >> PAGE_SHIFT, + pg->gatt_start - pg->ci_stolen_size, + pg->ci_stolen_size >> PAGE_SHIFT, 0); + up_read(&pg->sem); + if (ret) + goto out_err; + + dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0); + if (!dev_priv->pf_pd) + goto out_err; + + /* + * Make all presumably unused requestors page-fault by making them + * use context 1 which does not have any valid mappings. + */ + + PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0); + PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1); + PSB_RSGX32(PSB_CR_BIF_BANK1); + + psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0); + psb_mmu_set_pd_context(dev_priv->pf_pd, 1); + psb_mmu_enable_requestor(dev_priv->mmu, _PSB_MMU_ER_MASK); + + psb_init_2d(dev_priv); + + ret = ttm_bo_init_mm(bdev, DRM_PSB_MEM_KERNEL, 0x00000000, + (PSB_MEM_PDS_START - PSB_MEM_KERNEL_START) + >> PAGE_SHIFT); + if (ret) + goto out_err; + dev_priv->have_mem_kernel = 1; + + ret = ttm_bo_init_mm(bdev, DRM_PSB_MEM_PDS, 0x00000000, + (PSB_MEM_RASTGEOM_START - PSB_MEM_PDS_START) + >> PAGE_SHIFT); + if (ret) + goto out_err; + dev_priv->have_mem_pds = 1; + + PSB_DEBUG_INIT("Begin to init SGX/MSVDX/Topaz\n"); + + ret = psb_do_init(dev); + if (ret) + return ret; + + ret = psb_xhw_init(dev); + if (ret) + return ret; + + PSB_WSGX32(PSB_MEM_PDS_START, PSB_CR_PDS_EXEC_BASE); + PSB_WSGX32(PSB_MEM_RASTGEOM_START, PSB_CR_BIF_3D_REQ_BASE); + + psb_init_ospm(dev_priv); + + if (drm_psb_no_fb == 0) { + psb_modeset_init(dev); + drm_helper_initial_config(dev, false); + } + /*set SGX in low power mode*/ + if (drm_psb_ospm && IS_MRST(dev)) + if (psb_try_power_down_sgx(dev)) + PSB_DEBUG_PM("initialize SGX to low power failed\n"); + return 0; +out_err: + psb_driver_unload(dev); + return ret; +} + +int psb_driver_device_is_agp(struct drm_device *dev) +{ + return 0; +} + +static int psb_prepare_msvdx_suspend(struct drm_device *dev) +{ +#ifdef PSB_FIXME + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + struct ttm_fence_device *fdev = &dev_priv->fdev; + struct ttm_fence_class_manager *fc = + &fdev->fence_class[PSB_ENGINE_VIDEO]; + struct ttm_fence_object *fence; + int ret = 0; + int signaled = 0; + int count = 0; + unsigned long _end = jiffies + 3 * DRM_HZ; + + PSB_DEBUG_GENERAL + ("MSVDXACPI Entering psb_prepare_msvdx_suspend....\n"); + + /*set the msvdx-reset flag here.. */ + dev_priv->msvdx_needs_reset = 1; + + /*Ensure that all pending IRQs are serviced, */ + + /* + * Save the last MSVDX fence in dev_priv instead!!! + * Need to be fc->write_locked while accessing a fence from the ring. + */ + + list_for_each_entry(fence, &fc->ring, ring) { + count++; + do { + DRM_WAIT_ON(ret, fc->fence_queue, 3 * DRM_HZ, + (signaled = + ttm_fence_object_signaled(fence, + DRM_FENCE_TYPE_EXE))); + if (signaled) + break; + if (time_after_eq(jiffies, _end)) + PSB_DEBUG_GENERAL + ("MSVDXACPI: fence 0x%x didn't get" + " signaled for 3 secs; " + "we will suspend anyways\n", + (unsigned int) fence); + } while (ret == -EINTR); + + } + PSB_DEBUG_GENERAL("MSVDXACPI: All MSVDX IRQs (%d) serviced...\n", + count); +#endif + return 0; +} + +static int psb_suspend(struct pci_dev *pdev, pm_message_t state) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + + if (!down_write_trylock(&dev_priv->sgx_sem)) + return -EBUSY; + if (dev_priv->graphics_state != PSB_PWR_STATE_D0i0); + PSB_DEBUG_PM("Not suspending from D0i0\n"); + if (dev_priv->graphics_state == PSB_PWR_STATE_D3) + goto exit; + if (drm_psb_no_fb == 0) + psbfb_suspend(dev); + + dev_priv->saveCLOCKGATING = PSB_RSGX32(PSB_CR_CLKGATECTL); + (void) psb_idle_3d(dev); + (void) psb_idle_2d(dev); + flush_scheduled_work(); + + if (dev_priv->has_msvdx) + psb_prepare_msvdx_suspend(dev); + + if (dev_priv->has_topaz) + lnc_prepare_topaz_suspend(dev); + +#ifdef OSPM_STAT + if (dev_priv->graphics_state == PSB_PWR_STATE_D0i0) + dev_priv->gfx_d0i0_time += jiffies - dev_priv->gfx_last_mode_change; + else if (dev_priv->graphics_state == PSB_PWR_STATE_D0i3) + dev_priv->gfx_d0i3_time += jiffies - dev_priv->gfx_last_mode_change; + else + PSB_DEBUG_PM("suspend: illegal previous power state\n"); + dev_priv->gfx_last_mode_change = jiffies; + dev_priv->gfx_d3_cnt++; +#endif + + dev_priv->graphics_state = PSB_PWR_STATE_D3; + dev_priv->msvdx_state = PSB_PWR_STATE_D3; + dev_priv->topaz_power_state = LNC_TOPAZ_POWEROFF; + pci_save_state(pdev); + pci_disable_device(pdev); + pci_set_power_state(pdev, PCI_D3hot); + psb_down_island_power(dev, PSB_GRAPHICS_ISLAND | PSB_VIDEO_ENC_ISLAND + | PSB_VIDEO_DEC_ISLAND); +exit: + up_write(&dev_priv->sgx_sem); + return 0; +} + +static int psb_resume(struct pci_dev *pdev) +{ + struct drm_device *dev = pci_get_drvdata(pdev); + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + struct psb_gtt *pg = dev_priv->pg; + int ret; + if (dev_priv->graphics_state != PSB_PWR_STATE_D3) + return 0; + + psb_up_island_power(dev, PSB_GRAPHICS_ISLAND | PSB_VIDEO_ENC_ISLAND + | PSB_VIDEO_DEC_ISLAND); + pci_set_power_state(pdev, PCI_D0); + pci_restore_state(pdev); + ret = pci_enable_device(pdev); + if (ret) + return ret; + + DRM_ERROR("FIXME: topaz's resume is not ready..\n"); +#ifdef OSPM_STAT + if (dev_priv->graphics_state == PSB_PWR_STATE_D3) + dev_priv->gfx_d3_time += jiffies - dev_priv->gfx_last_mode_change; + else + PSB_DEBUG_PM("resume :illegal previous power state\n"); + dev_priv->gfx_last_mode_change = jiffies; + dev_priv->gfx_d0i0_cnt++; +#endif + dev_priv->graphics_state = PSB_PWR_STATE_D0i0; + dev_priv->msvdx_state = PSB_PWR_STATE_D0i0; + dev_priv->topaz_power_state = LNC_TOPAZ_POWERON; + INIT_LIST_HEAD(&dev_priv->resume_buf.head); + dev_priv->msvdx_needs_reset = 1; + + lnc_prepare_topaz_resume(dev); + + PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); + pci_write_config_word(pdev, PSB_GMCH_CTRL, + pg->gmch_ctrl | _PSB_GMCH_ENABLED); + + /* + * The GTT page tables are probably not saved. + * However, TT and VRAM is empty at this point. + */ + + psb_gtt_init(dev_priv->pg, 1); + + /* + * The SGX loses it's register contents. + * Restore BIF registers. The MMU page tables are + * "normal" pages, so their contents should be kept. + */ + + PSB_WSGX32(dev_priv->saveCLOCKGATING, PSB_CR_CLKGATECTL); + PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0); + PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1); + PSB_RSGX32(PSB_CR_BIF_BANK1); + + psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0); + psb_mmu_set_pd_context(dev_priv->pf_pd, 1); + psb_mmu_enable_requestor(dev_priv->mmu, _PSB_MMU_ER_MASK); + + /* + * 2D Base registers.. + */ + psb_init_2d(dev_priv); + + /* + * Persistant 3D base registers and USSE base registers.. + */ + + PSB_WSGX32(PSB_MEM_PDS_START, PSB_CR_PDS_EXEC_BASE); + PSB_WSGX32(PSB_MEM_RASTGEOM_START, PSB_CR_BIF_3D_REQ_BASE); + PSB_WSGX32(dev_priv->sgx2_irq_mask, PSB_CR_EVENT_HOST_ENABLE2); + PSB_WSGX32(dev_priv->sgx_irq_mask, PSB_CR_EVENT_HOST_ENABLE); + (void)PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); + + /* + * Now, re-initialize the 3D engine. + */ + + psb_xhw_resume(dev_priv, &dev_priv->resume_buf); + + psb_scheduler_ta_mem_check(dev_priv); + if (dev_priv->ta_mem && !dev_priv->force_ta_mem_load) { + psb_xhw_ta_mem_load(dev_priv, &dev_priv->resume_buf, + PSB_TA_MEM_FLAG_TA | + PSB_TA_MEM_FLAG_RASTER | + PSB_TA_MEM_FLAG_HOSTA | + PSB_TA_MEM_FLAG_HOSTD | + PSB_TA_MEM_FLAG_INIT, + dev_priv->ta_mem->ta_memory->offset, + dev_priv->ta_mem->hw_data->offset, + dev_priv->ta_mem->hw_cookie); + } + + if (drm_psb_no_fb == 0) + psbfb_resume(dev); + + return 0; +} + +int psb_extension_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + union drm_psb_extension_arg *arg = data; + struct drm_psb_extension_rep *rep = &arg->rep; + + if (strcmp(arg->extension, "psb_ttm_placement_alphadrop") == 0) { + rep->exists = 1; + rep->driver_ioctl_offset = DRM_PSB_PLACEMENT_OFFSET; + rep->sarea_offset = 0; + rep->major = 1; + rep->minor = 0; + rep->pl = 0; + return 0; + } + if (strcmp(arg->extension, "psb_ttm_fence_alphadrop") == 0) { + rep->exists = 1; + rep->driver_ioctl_offset = DRM_PSB_FENCE_OFFSET; + rep->sarea_offset = 0; + rep->major = 1; + rep->minor = 0; + rep->pl = 0; + return 0; + } + if (strcmp(arg->extension, "psb_ttm_execbuf_alphadrop") == 0) { + rep->exists = 1; + rep->driver_ioctl_offset = DRM_PSB_CMDBUF; + rep->sarea_offset = 0; + rep->major = 1; + rep->minor = 0; + rep->pl = 0; + return 0; + } + + rep->exists = 0; + return 0; +} + +static int psb_vt_leave_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_psb_private *dev_priv = psb_priv(dev); + struct ttm_bo_device *bdev = &dev_priv->bdev; + struct ttm_mem_type_manager *man; + int clean; + int ret; + + ret = ttm_write_lock(&dev_priv->ttm_lock, 1, + psb_fpriv(file_priv)->tfile); + if (unlikely(ret != 0)) + return ret; + + /* + * Clean VRAM and TT for fbdev. + */ + + ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); + if (unlikely(ret != 0)) + goto out_unlock; + + man = &bdev->man[TTM_PL_VRAM]; + spin_lock(&bdev->lru_lock); + clean = drm_mm_clean(&man->manager); + spin_unlock(&bdev->lru_lock); + if (unlikely(!clean)) + DRM_INFO("Notice: VRAM was not clean after VT switch, if you are running fbdev please ignore.\n"); + + ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_TT); + if (unlikely(ret != 0)) + goto out_unlock; + + man = &bdev->man[TTM_PL_TT]; + spin_lock(&bdev->lru_lock); + clean = drm_mm_clean(&man->manager); + spin_unlock(&bdev->lru_lock); + if (unlikely(!clean)) + DRM_INFO("Warning: GATT was not clean after VT switch.\n"); + + ttm_bo_swapout_all(&dev_priv->bdev); + + return 0; +out_unlock: + (void) ttm_write_unlock(&dev_priv->ttm_lock, + psb_fpriv(file_priv)->tfile); + return ret; +} + +static int psb_vt_enter_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_psb_private *dev_priv = psb_priv(dev); + return ttm_write_unlock(&dev_priv->ttm_lock, + psb_fpriv(file_priv)->tfile); +} + +/* always available as we are SIGIO'd */ +static unsigned int psb_poll(struct file *filp, + struct poll_table_struct *wait) +{ + return POLLIN | POLLRDNORM; +} + +int psb_driver_open(struct drm_device *dev, struct drm_file *priv) +{ + /*psb_check_power_state(dev, PSB_DEVICE_SGX);*/ + return 0; +} + +static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd, + unsigned long arg) +{ + struct drm_file *file_priv = filp->private_data; + struct drm_device *dev = file_priv->minor->dev; + unsigned int nr = DRM_IOCTL_NR(cmd); + long ret; + + /* + * The driver private ioctls and TTM ioctls should be + * thread-safe. + */ + + if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) + && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { + struct drm_ioctl_desc *ioctl = &psb_ioctls[nr - DRM_COMMAND_BASE]; + + if (unlikely(ioctl->cmd != cmd)) { + DRM_ERROR("Invalid drm command %d\n", + nr - DRM_COMMAND_BASE); + return -EINVAL; + } + + return drm_unlocked_ioctl(filp, cmd, arg); + } + /* + * Not all old drm ioctls are thread-safe. + */ + + lock_kernel(); + ret = drm_unlocked_ioctl(filp, cmd, arg); + unlock_kernel(); + return ret; +} + +static int psb_ospm_read(char *buf, char **start, off_t offset, int request, + int *eof, void *data) +{ + struct drm_minor *minor = (struct drm_minor *) data; + struct drm_device *dev = minor->dev; + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + int len = 0; + unsigned long d0i0 = 0; + unsigned long d0i3 = 0; + unsigned long d3 = 0; + *start = &buf[offset]; + *eof = 0; + DRM_PROC_PRINT("D0i3:%s ", drm_psb_ospm ? "enabled" : "disabled"); + switch (dev_priv->graphics_state) { + case PSB_PWR_STATE_D0i0: + DRM_PROC_PRINT("GFX:%s\n", "D0i0"); + break; + case PSB_PWR_STATE_D0i3: + DRM_PROC_PRINT("GFX:%s\n", "D0i3"); + break; + case PSB_PWR_STATE_D3: + DRM_PROC_PRINT("GFX:%s\n", "D3"); + break; + default: + DRM_PROC_PRINT("GFX:%s\n", "unkown"); + } +#ifdef OSPM_STAT + d0i0 = dev_priv->gfx_d0i0_time * 1000 / HZ; + d0i3 = dev_priv->gfx_d0i3_time * 1000 / HZ; + d3 = dev_priv->gfx_d3_time * 1000 / HZ; + switch (dev_priv->graphics_state) { + case PSB_PWR_STATE_D0i0: + d0i0 += (jiffies - dev_priv->gfx_last_mode_change) * 1000 / HZ; + break; + case PSB_PWR_STATE_D0i3: + d0i3 += (jiffies - dev_priv->gfx_last_mode_change) * 1000 / HZ; + break; + case PSB_PWR_STATE_D3: + d3 += (jiffies - dev_priv->gfx_last_mode_change) * 1000 / HZ; + break; + } + DRM_PROC_PRINT("GFX(cnt/ms):\n"); + DRM_PROC_PRINT("D0i0:%lu/%lu, D0i3:%lu/%lu, D3:%lu/%lu \n", + dev_priv->gfx_d0i0_cnt, d0i0, dev_priv->gfx_d0i3_cnt, d0i3, + dev_priv->gfx_d3_cnt, d3); +#endif + if (len > request + offset) + return request; + *eof = 1; + return len - offset; +} + +static int psb_proc_init(struct drm_minor *minor) +{ + struct proc_dir_entry *ent; + if (!minor->dev_root) + return 0; + ent = create_proc_read_entry(OSPM_PROC_ENTRY, 0, minor->dev_root, + psb_ospm_read, minor); + if (ent) + return 0; + else + return -1; +} + +static void psb_proc_cleanup(struct drm_minor *minor) +{ + if (!minor->dev_root) + return; + remove_proc_entry(OSPM_PROC_ENTRY, minor->dev_root); + return; +} + +static struct drm_driver driver = { + .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED, + .load = psb_driver_load, + .unload = psb_driver_unload, + .dri_library_name = dri_library_name, + .get_reg_ofs = drm_core_get_reg_ofs, + .ioctls = psb_ioctls, + .device_is_agp = psb_driver_device_is_agp, + .irq_preinstall = psb_irq_preinstall, + .irq_postinstall = psb_irq_postinstall, + .irq_uninstall = psb_irq_uninstall, + .irq_handler = psb_irq_handler, + .firstopen = NULL, + .lastclose = psb_lastclose, + .open = psb_driver_open, + .proc_init = psb_proc_init, + .proc_cleanup = psb_proc_cleanup, + .fops = { + .owner = THIS_MODULE, + .open = psb_open, + .release = psb_release, + .unlocked_ioctl = psb_unlocked_ioctl, + .mmap = psb_mmap, + .poll = psb_poll, + .fasync = drm_fasync, + }, + .pci_driver = { + .name = DRIVER_NAME, + .id_table = pciidlist, + .resume = psb_resume, + .suspend = psb_suspend, + }, + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = PSB_DRM_DRIVER_DATE, + .major = PSB_DRM_DRIVER_MAJOR, + .minor = PSB_DRM_DRIVER_MINOR, + .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL +}; + +static int __init psb_init(void) +{ + driver.num_ioctls = psb_max_ioctl; + + return drm_init(&driver); +} + +static void __exit psb_exit(void) +{ + drm_exit(&driver); +} + +module_init(psb_init); +module_exit(psb_exit); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); --- /dev/null +++ b/drivers/staging/psb/psb_drv.h @@ -0,0 +1,1129 @@ +/************************************************************************** + *Copyright (c) 2007-2008, Intel Corporation. + *All Rights Reserved. + * + *This program is free software; you can redistribute it and/or modify it + *under the terms and conditions of the GNU General Public License, + *version 2, as published by the Free Software Foundation. + * + *This program is distributed in the hope it will be useful, but WITHOUT + *ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + *FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + *more details. + * + *You should have received a copy of the GNU General Public License along with + *this program; if not, write to the Free Software Foundation, Inc., + *51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + *Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + *develop this driver. + * + **************************************************************************/ +/* + */ +#ifndef _PSB_DRV_H_ +#define _PSB_DRV_H_ + +#include +#include "psb_drm.h" +#include "psb_reg.h" +#include "psb_schedule.h" +#include "intel_drv.h" +#include "ttm/ttm_object.h" +#include "ttm/ttm_fence_driver.h" +#include "ttm/ttm_bo_driver.h" +#include "ttm/ttm_lock.h" + +extern struct ttm_bo_driver psb_ttm_bo_driver; + +enum { + CHIP_PSB_8108 = 0, + CHIP_PSB_8109 = 1, + CHIP_MRST_4100 = 2 +}; + +/* + *Hardware bugfixes + */ + +#define FIX_TG_16 +#define FIX_TG_2D_CLOCKGATE +#define OSPM_STAT + +#define DRIVER_NAME "psb" +#define DRIVER_DESC "drm driver for the Intel GMA500" +#define DRIVER_AUTHOR "Tungsten Graphics Inc." +#define OSPM_PROC_ENTRY "ospm" + +#define PSB_DRM_DRIVER_DATE "2009-02-09" +#define PSB_DRM_DRIVER_MAJOR 8 +#define PSB_DRM_DRIVER_MINOR 0 +#define PSB_DRM_DRIVER_PATCHLEVEL 0 + +/* + *TTM driver private offsets. + */ + +#define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) + +#define PSB_OBJECT_HASH_ORDER 13 +#define PSB_FILE_OBJECT_HASH_ORDER 12 +#define PSB_BO_HASH_ORDER 12 + +#define PSB_VDC_OFFSET 0x00000000 +#define PSB_VDC_SIZE 0x000080000 +#define MRST_MMIO_SIZE 0x0000C0000 +#define PSB_SGX_SIZE 0x8000 +#define PSB_SGX_OFFSET 0x00040000 +#define MRST_SGX_OFFSET 0x00080000 +#define PSB_MMIO_RESOURCE 0 +#define PSB_GATT_RESOURCE 2 +#define PSB_GTT_RESOURCE 3 +#define PSB_GMCH_CTRL 0x52 +#define PSB_BSM 0x5C +#define _PSB_GMCH_ENABLED 0x4 +#define PSB_PGETBL_CTL 0x2020 +#define _PSB_PGETBL_ENABLED 0x00000001 +#define PSB_SGX_2D_SLAVE_PORT 0x4000 +#define PSB_TT_PRIV0_LIMIT (256*1024*1024) +#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT) +#define PSB_NUM_VALIDATE_BUFFERS 2048 +#define PSB_MEM_KERNEL_START 0x10000000 +#define PSB_MEM_PDS_START 0x20000000 +#define PSB_MEM_MMU_START 0x40000000 + +#define DRM_PSB_MEM_KERNEL TTM_PL_PRIV0 +#define DRM_PSB_FLAG_MEM_KERNEL TTM_PL_FLAG_PRIV0 + +/* + *Flags for external memory type field. + */ + +#define MRST_MSVDX_OFFSET 0x90000 /*MSVDX Base offset */ +#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */ +/* MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */ +#define PSB_MSVDX_SIZE 0x10000 + +#define LNC_TOPAZ_OFFSET 0xA0000 +#define LNC_TOPAZ_SIZE 0x10000 + +#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */ +#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */ +#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */ + +/* + *PTE's and PDE's + */ + +#define PSB_PDE_MASK 0x003FFFFF +#define PSB_PDE_SHIFT 22 +#define PSB_PTE_SHIFT 12 + +#define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */ +#define PSB_PTE_WO 0x0002 /* Write only */ +#define PSB_PTE_RO 0x0004 /* Read only */ +#define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */ + +/* + *VDC registers and bits + */ +#define PSB_HWSTAM 0x2098 +#define PSB_INSTPM 0x20C0 +#define PSB_INT_IDENTITY_R 0x20A4 +#define _PSB_VSYNC_PIPEB_FLAG (1<<5) +#define _PSB_VSYNC_PIPEA_FLAG (1<<7) +#define _PSB_IRQ_SGX_FLAG (1<<18) +#define _PSB_IRQ_MSVDX_FLAG (1<<19) +#define _LNC_IRQ_TOPAZ_FLAG (1<<20) +#define PSB_INT_MASK_R 0x20A8 +#define PSB_INT_ENABLE_R 0x20A0 +#define PSB_PIPEASTAT 0x70024 +#define _PSB_VBLANK_INTERRUPT_ENABLE (1 << 17) +#define _PSB_VBLANK_CLEAR (1 << 1) +#define PSB_PIPEBSTAT 0x71024 + +#define _PSB_MMU_ER_MASK 0x0001FF00 +#define _PSB_MMU_ER_HOST (1 << 16) +#define GPIOA 0x5010 +#define GPIOB 0x5014 +#define GPIOC 0x5018 +#define GPIOD 0x501c +#define GPIOE 0x5020 +#define GPIOF 0x5024 +#define GPIOG 0x5028 +#define GPIOH 0x502c +#define GPIO_CLOCK_DIR_MASK (1 << 0) +#define GPIO_CLOCK_DIR_IN (0 << 1) +#define GPIO_CLOCK_DIR_OUT (1 << 1) +#define GPIO_CLOCK_VAL_MASK (1 << 2) +#define GPIO_CLOCK_VAL_OUT (1 << 3) +#define GPIO_CLOCK_VAL_IN (1 << 4) +#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) +#define GPIO_DATA_DIR_MASK (1 << 8) +#define GPIO_DATA_DIR_IN (0 << 9) +#define GPIO_DATA_DIR_OUT (1 << 9) +#define GPIO_DATA_VAL_MASK (1 << 10) +#define GPIO_DATA_VAL_OUT (1 << 11) +#define GPIO_DATA_VAL_IN (1 << 12) +#define GPIO_DATA_PULLUP_DISABLE (1 << 13) + +#define VCLK_DIVISOR_VGA0 0x6000 +#define VCLK_DIVISOR_VGA1 0x6004 +#define VCLK_POST_DIV 0x6010 + +#define PSB_COMM_2D (PSB_ENGINE_2D << 4) +#define PSB_COMM_3D (PSB_ENGINE_3D << 4) +#define PSB_COMM_TA (PSB_ENGINE_TA << 4) +#define PSB_COMM_HP (PSB_ENGINE_HP << 4) +#define PSB_COMM_USER_IRQ (1024 >> 2) +#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1) +#define PSB_COMM_FW (2048 >> 2) + +#define PSB_UIRQ_VISTEST 1 +#define PSB_UIRQ_OOM_REPLY 2 +#define PSB_UIRQ_FIRE_TA_REPLY 3 +#define PSB_UIRQ_FIRE_RASTER_REPLY 4 + +#define PSB_2D_SIZE (256*1024*1024) +#define PSB_MAX_RELOC_PAGES 1024 + +#define PSB_LOW_REG_OFFS 0x0204 +#define PSB_HIGH_REG_OFFS 0x0600 + +#define PSB_NUM_VBLANKS 2 + +#define PSB_COMM_2D (PSB_ENGINE_2D << 4) +#define PSB_COMM_3D (PSB_ENGINE_3D << 4) +#define PSB_COMM_TA (PSB_ENGINE_TA << 4) +#define PSB_COMM_HP (PSB_ENGINE_HP << 4) +#define PSB_COMM_FW (2048 >> 2) + +#define PSB_2D_SIZE (256*1024*1024) +#define PSB_MAX_RELOC_PAGES 1024 + +#define PSB_LOW_REG_OFFS 0x0204 +#define PSB_HIGH_REG_OFFS 0x0600 + +#define PSB_NUM_VBLANKS 2 +#define PSB_WATCHDOG_DELAY (DRM_HZ / 10) + +#define PSB_PWR_STATE_MASK 0x0F +#define PSB_PWR_ACTION_MASK 0xF0 +#define PSB_PWR_STATE_D0i0 0x1 +#define PSB_PWR_STATE_D0i3 0x2 +#define PSB_PWR_STATE_D3 0x3 +#define PSB_PWR_ACTION_DOWN 0x10 /*Need to power down*/ +#define PSB_PWR_ACTION_UP 0x20/*Need to power up*/ +#define PSB_GRAPHICS_ISLAND 0x1 +#define PSB_VIDEO_ENC_ISLAND 0x2 +#define PSB_VIDEO_DEC_ISLAND 0x4 +#define LNC_TOPAZ_POWERON 0x1 +#define LNC_TOPAZ_POWEROFF 0x0 + +/* + *User options. + */ + +struct drm_psb_uopt { + int clock_gating; +}; + +/** + *struct psb_context + * + *@buffers: array of pre-allocated validate buffers. + *@used_buffers: number of buffers in @buffers array currently in use. + *@validate_buffer: buffers validated from user-space. + *@kern_validate_buffers : buffers validated from kernel-space. + *@fence_flags : Fence flags to be used for fence creation. + * + *This structure is used during execbuf validation. + */ + +struct psb_context { + struct psb_validate_buffer *buffers; + uint32_t used_buffers; + struct list_head validate_list; + struct list_head kern_validate_list; + uint32_t fence_types; + uint32_t val_seq; +}; + +struct psb_gtt { + struct drm_device *dev; + int initialized; + uint32_t gatt_start; + uint32_t gtt_start; + uint32_t gtt_phys_start; + unsigned gtt_pages; + unsigned gatt_pages; + uint32_t stolen_base; + uint32_t pge_ctl; + u16 gmch_ctrl; + unsigned long stolen_size; + unsigned long vram_stolen_size; + unsigned long ci_stolen_size; + unsigned long rar_stolen_size; + uint32_t *gtt_map; + struct rw_semaphore sem; +}; + +struct psb_use_base { + struct list_head head; + struct ttm_fence_object *fence; + unsigned int reg; + unsigned long offset; + unsigned int dm; +}; + +struct psb_validate_buffer; + +struct psb_msvdx_cmd_queue { + struct list_head head; + void *cmd; + unsigned long cmd_size; + uint32_t sequence; +}; + + +struct drm_psb_private { + + /* + *TTM Glue. + */ + + struct drm_global_reference mem_global_ref; + int has_global; + + struct drm_device *dev; + struct ttm_object_device *tdev; + struct ttm_fence_device fdev; + struct ttm_bo_device bdev; + struct ttm_lock ttm_lock; + struct vm_operations_struct *ttm_vm_ops; + int has_fence_device; + int has_bo_device; + + unsigned long chipset; + + struct psb_xhw_buf resume_buf; + struct drm_psb_dev_info_arg dev_info; + struct drm_psb_uopt uopt; + + struct psb_gtt *pg; + + struct page *scratch_page; + struct page *comm_page; + /* Deleted volatile because it is not recommended to use. */ + uint32_t *comm; + uint32_t comm_mmu_offset; + uint32_t mmu_2d_offset; + uint32_t sequence[PSB_NUM_ENGINES]; + uint32_t last_sequence[PSB_NUM_ENGINES]; + int idle[PSB_NUM_ENGINES]; + uint32_t last_submitted_seq[PSB_NUM_ENGINES]; + int engine_lockup_2d; + + struct psb_mmu_driver *mmu; + struct psb_mmu_pd *pf_pd; + + uint8_t *sgx_reg; + uint8_t *vdc_reg; + uint32_t gatt_free_offset; + + /* + *MSVDX + */ + int has_msvdx; + uint8_t *msvdx_reg; + int msvdx_needs_reset; + atomic_t msvdx_mmu_invaldc; + + /* + *TOPAZ + */ + uint8_t *topaz_reg; + + void *topaz_mtx_reg_state; + struct ttm_buffer_object *topaz_mtx_data_mem; + uint32_t topaz_cur_codec; + uint32_t cur_mtx_data_size; + int topaz_needs_reset; + int has_topaz; +#define TOPAZ_MAX_IDELTIME (HZ*30) + int topaz_start_idle; + unsigned long topaz_idle_start_jiffies; + /* used by lnc_topaz_lockup */ + uint32_t topaz_current_sequence; + uint32_t topaz_last_sequence; + uint32_t topaz_finished_sequence; + + /* + *Fencing / irq. + */ + + uint32_t sgx_irq_mask; + uint32_t sgx2_irq_mask; + uint32_t vdc_irq_mask; + + spinlock_t irqmask_lock; + spinlock_t sequence_lock; + int fence0_irq_on; + int irq_enabled; + unsigned int irqen_count_2d; + wait_queue_head_t event_2d_queue; + +#ifdef FIX_TG_16 + wait_queue_head_t queue_2d; + atomic_t lock_2d; + atomic_t ta_wait_2d; + atomic_t ta_wait_2d_irq; + atomic_t waiters_2d; +#else + struct mutex mutex_2d; +#endif + uint32_t msvdx_current_sequence; + uint32_t msvdx_last_sequence; + int fence2_irq_on; + + /* + *Modesetting + */ + struct intel_mode_device mode_dev; + + /* + *MSVDX Rendec Memory + */ + struct ttm_buffer_object *ccb0; + uint32_t base_addr0; + struct ttm_buffer_object *ccb1; + uint32_t base_addr1; + + /* + * CI share buffer + */ + unsigned int ci_region_start; + unsigned int ci_region_size; + + /* + *Memory managers + */ + + int have_vram; + int have_camera; + int have_tt; + int have_mem_mmu; + int have_mem_aper; + int have_mem_kernel; + int have_mem_pds; + int have_mem_rastgeom; + struct mutex temp_mem; + + /* + *Relocation buffer mapping. + */ + + spinlock_t reloc_lock; + unsigned int rel_mapped_pages; + wait_queue_head_t rel_mapped_queue; + + /* + *SAREA + */ + struct drm_psb_sarea *sarea_priv; + + /* + *LVDS info + */ + int backlight_duty_cycle; /* restore backlight to this value */ + bool panel_wants_dither; + struct drm_display_mode *panel_fixed_mode; + +/* MRST private date start */ +/*FIXME JLIU7 need to revisit */ + bool sku_83; + bool sku_100; + bool sku_100L; + bool sku_bypass; + uint32_t iLVDS_enable; + + /* pipe config register value */ + uint32_t pipeconf; + + /* plane control register value */ + uint32_t dspcntr; + +/* MRST_DSI private date start */ + /* + *MRST DSI info + */ + /* The DSI device ready */ + bool dsi_device_ready; + + /* The DPI panel power on */ + bool dpi_panel_on; + + /* The DBI panel power on */ + bool dbi_panel_on; + + /* The DPI display */ + bool dpi; + + /* status */ + uint32_t videoModeFormat:2; + uint32_t laneCount:3; + uint32_t status_reserved:27; + + /* dual display - DPI & DBI */ + bool dual_display; + + /* HS or LP transmission */ + bool lp_transmission; + + /* configuration phase */ + bool config_phase; + + /* DSI clock */ + uint32_t RRate; + uint32_t DDR_Clock; + uint32_t DDR_Clock_Calculated; + uint32_t ClockBits; + + /* DBI Buffer pointer */ + u8 *p_DBI_commandBuffer_orig; + u8 *p_DBI_commandBuffer; + uint32_t DBI_CB_pointer; + u8 *p_DBI_dataBuffer_orig; + u8 *p_DBI_dataBuffer; + uint32_t DBI_DB_pointer; + + /* DPI panel spec */ + uint32_t pixelClock; + uint32_t HsyncWidth; + uint32_t HbackPorch; + uint32_t HfrontPorch; + uint32_t HactiveArea; + uint32_t VsyncWidth; + uint32_t VbackPorch; + uint32_t VfrontPorch; + uint32_t VactiveArea; + uint32_t bpp:5; + uint32_t Reserved:27; + + /* DBI panel spec */ + uint32_t dbi_pixelClock; + uint32_t dbi_HsyncWidth; + uint32_t dbi_HbackPorch; + uint32_t dbi_HfrontPorch; + uint32_t dbi_HactiveArea; + uint32_t dbi_VsyncWidth; + uint32_t dbi_VbackPorch; + uint32_t dbi_VfrontPorch; + uint32_t dbi_VactiveArea; + uint32_t dbi_bpp:5; + uint32_t dbi_Reserved:27; + +/* MRST_DSI private date end */ + + /* + *Register state + */ + uint32_t saveDSPACNTR; + uint32_t saveDSPBCNTR; + uint32_t savePIPEACONF; + uint32_t savePIPEBCONF; + uint32_t savePIPEASRC; + uint32_t savePIPEBSRC; + uint32_t saveFPA0; + uint32_t saveFPA1; + uint32_t saveDPLL_A; + uint32_t saveDPLL_A_MD; + uint32_t saveHTOTAL_A; + uint32_t saveHBLANK_A; + uint32_t saveHSYNC_A; + uint32_t saveVTOTAL_A; + uint32_t saveVBLANK_A; + uint32_t saveVSYNC_A; + uint32_t saveDSPASTRIDE; + uint32_t saveDSPASIZE; + uint32_t saveDSPAPOS; + uint32_t saveDSPABASE; + uint32_t saveDSPASURF; + uint32_t saveFPB0; + uint32_t saveFPB1; + uint32_t saveDPLL_B; + uint32_t saveDPLL_B_MD; + uint32_t saveHTOTAL_B; + uint32_t saveHBLANK_B; + uint32_t saveHSYNC_B; + uint32_t saveVTOTAL_B; + uint32_t saveVBLANK_B; + uint32_t saveVSYNC_B; + uint32_t saveDSPBSTRIDE; + uint32_t saveDSPBSIZE; + uint32_t saveDSPBPOS; + uint32_t saveDSPBBASE; + uint32_t saveDSPBSURF; + uint32_t saveVCLK_DIVISOR_VGA0; + uint32_t saveVCLK_DIVISOR_VGA1; + uint32_t saveVCLK_POST_DIV; + uint32_t saveVGACNTRL; + uint32_t saveADPA; + uint32_t saveLVDS; + uint32_t saveDVOA; + uint32_t saveDVOB; + uint32_t saveDVOC; + uint32_t savePP_ON; + uint32_t savePP_OFF; + uint32_t savePP_CONTROL; + uint32_t savePP_CYCLE; + uint32_t savePFIT_CONTROL; + uint32_t savePaletteA[256]; + uint32_t savePaletteB[256]; + uint32_t saveBLC_PWM_CTL; + uint32_t saveCLOCKGATING; + + /* + *Xhw + */ + + uint32_t *xhw; + struct ttm_buffer_object *xhw_bo; + struct ttm_bo_kmap_obj xhw_kmap; + struct list_head xhw_in; + spinlock_t xhw_lock; + atomic_t xhw_client; + struct drm_file *xhw_file; + wait_queue_head_t xhw_queue; + wait_queue_head_t xhw_caller_queue; + struct mutex xhw_mutex; + struct psb_xhw_buf *xhw_cur_buf; + int xhw_submit_ok; + int xhw_on; + + /* + *Scheduling. + */ + + struct mutex reset_mutex; + struct psb_scheduler scheduler; + struct mutex cmdbuf_mutex; + uint32_t ta_mem_pages; + struct psb_ta_mem *ta_mem; + int force_ta_mem_load; + atomic_t val_seq; + + /* + *TODO: change this to be per drm-context. + */ + + struct psb_context context; + + /* + *Watchdog + */ + + spinlock_t watchdog_lock; + struct timer_list watchdog_timer; + struct work_struct watchdog_wq; + struct work_struct msvdx_watchdog_wq; + struct work_struct topaz_watchdog_wq; + int timer_available; + + /* + *msvdx command queue + */ + spinlock_t msvdx_lock; + struct mutex msvdx_mutex; + struct list_head msvdx_queue; + int msvdx_busy; + int msvdx_fw_loaded; + void *msvdx_fw; + int msvdx_fw_size; + + /* + *topaz command queue + */ + spinlock_t topaz_lock; + struct mutex topaz_mutex; + struct list_head topaz_queue; + int topaz_busy; /* 0 means topaz is free */ + int topaz_fw_loaded; + + /* topaz ccb data */ + /* XXX: should the addr stored by 32 bits? more compatible way?? */ + uint32_t topaz_ccb_buffer_addr; + uint32_t topaz_ccb_ctrl_addr; + uint32_t topaz_ccb_size; + uint32_t topaz_cmd_windex; + uint16_t topaz_cmd_seq; + + uint32_t stored_initial_qp; + uint32_t topaz_dash_access_ctrl; + + struct ttm_buffer_object *topaz_bo; /* 4K->2K/2K for writeback/sync */ + struct ttm_bo_kmap_obj topaz_bo_kmap; + void *topaz_ccb_wb; + uint32_t topaz_wb_offset; + uint32_t *topaz_sync_addr; + uint32_t topaz_sync_offset; + uint32_t topaz_sync_cmd_seq; + + struct rw_semaphore sgx_sem; /*sgx is in used*/ + struct semaphore pm_sem; /*pm action in process*/ + unsigned char graphics_state; +#ifdef OSPM_STAT + unsigned long gfx_d0i3_time; + unsigned long gfx_d0i0_time; + unsigned long gfx_d3_time; + unsigned long gfx_last_mode_change; + unsigned long gfx_d0i0_cnt; + unsigned long gfx_d0i3_cnt; + unsigned long gfx_d3_cnt; +#endif + + /* MSVDX OSPM */ + unsigned char msvdx_state; + unsigned long msvdx_last_action; + uint32_t msvdx_clk_state; + + /* TOPAZ OSPM */ + unsigned char topaz_power_state; + unsigned long topaz_last_action; + uint32_t topaz_clk_state; +}; + +struct psb_fpriv { + struct ttm_object_file *tfile; +}; + +struct psb_mmu_driver; + +extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int); +extern int drm_pick_crtcs(struct drm_device *dev); + + +static inline struct psb_fpriv *psb_fpriv(struct drm_file *file_priv) +{ + return (struct psb_fpriv *) file_priv->driver_priv; +} + +static inline struct drm_psb_private *psb_priv(struct drm_device *dev) +{ + return (struct drm_psb_private *) dev->dev_private; +} + +/* + *TTM glue. psb_ttm_glue.c + */ + +extern int psb_open(struct inode *inode, struct file *filp); +extern int psb_release(struct inode *inode, struct file *filp); +extern int psb_mmap(struct file *filp, struct vm_area_struct *vma); + +extern int psb_fence_signaled_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_verify_access(struct ttm_buffer_object *bo, + struct file *filp); +extern ssize_t psb_ttm_read(struct file *filp, char __user *buf, + size_t count, loff_t *f_pos); +extern ssize_t psb_ttm_write(struct file *filp, const char __user *buf, + size_t count, loff_t *f_pos); +extern int psb_fence_finish_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_fence_unref_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_pl_waitidle_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_pl_setstatus_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_pl_synccpu_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_pl_unref_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_pl_reference_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_pl_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_extension_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_ttm_global_init(struct drm_psb_private *dev_priv); +extern void psb_ttm_global_release(struct drm_psb_private *dev_priv); +/* + *MMU stuff. + */ + +extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers, + int trap_pagefaults, + int invalid_type, + struct drm_psb_private *dev_priv); +extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver); +extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver + *driver); +extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset, + uint32_t gtt_start, uint32_t gtt_pages); +extern void psb_mmu_test(struct psb_mmu_driver *driver, uint32_t offset); +extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver, + int trap_pagefaults, + int invalid_type); +extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd); +extern void psb_mmu_flush(struct psb_mmu_driver *driver); +extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd, + unsigned long address, + uint32_t num_pages); +extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, + uint32_t start_pfn, + unsigned long address, + uint32_t num_pages, int type); +extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual, + unsigned long *pfn); + +/* + *Enable / disable MMU for different requestors. + */ + +extern void psb_mmu_enable_requestor(struct psb_mmu_driver *driver, + uint32_t mask); +extern void psb_mmu_disable_requestor(struct psb_mmu_driver *driver, + uint32_t mask); +extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context); +extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages, + unsigned long address, uint32_t num_pages, + uint32_t desired_tile_stride, + uint32_t hw_tile_stride, int type); +extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, + unsigned long address, uint32_t num_pages, + uint32_t desired_tile_stride, + uint32_t hw_tile_stride); +/* + *psb_sgx.c + */ + +extern int psb_blit_sequence(struct drm_psb_private *dev_priv, + uint32_t sequence); +extern void psb_init_2d(struct drm_psb_private *dev_priv); +extern int psb_idle_2d(struct drm_device *dev); +extern int psb_idle_3d(struct drm_device *dev); +extern int psb_emit_2d_copy_blit(struct drm_device *dev, + uint32_t src_offset, + uint32_t dst_offset, uint32_t pages, + int direction); +extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_reg_submit(struct drm_psb_private *dev_priv, + uint32_t *regs, unsigned int cmds); +extern int psb_submit_copy_cmdbuf(struct drm_device *dev, + struct ttm_buffer_object *cmd_buffer, + unsigned long cmd_offset, + unsigned long cmd_size, int engine, + uint32_t *copy_buffer); + +extern void psb_init_disallowed(void); +extern void psb_fence_or_sync(struct drm_file *file_priv, + uint32_t engine, + uint32_t fence_types, + uint32_t fence_flags, + struct list_head *list, + struct psb_ttm_fence_rep *fence_arg, + struct ttm_fence_object **fence_p); +extern int psb_validate_kernel_buffer(struct psb_context *context, + struct ttm_buffer_object *bo, + uint32_t fence_class, + uint64_t set_flags, + uint64_t clr_flags); +extern void psb_init_ospm(struct drm_psb_private *dev_priv); +extern void psb_check_power_state(struct drm_device *dev, int devices); +extern void psb_down_island_power(struct drm_device *dev, int islands); +extern void psb_up_island_power(struct drm_device *dev, int islands); +extern int psb_try_power_down_sgx(struct drm_device *dev); + +/* + *psb_irq.c + */ + +extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS); +extern void psb_irq_preinstall(struct drm_device *dev); +extern int psb_irq_postinstall(struct drm_device *dev); +extern void psb_irq_uninstall(struct drm_device *dev); +extern int psb_vblank_wait2(struct drm_device *dev, + unsigned int *sequence); +extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); + +/* + *psb_fence.c + */ + +extern void psb_fence_handler(struct drm_device *dev, uint32_t class); +extern void psb_2D_irq_off(struct drm_psb_private *dev_priv); +extern void psb_2D_irq_on(struct drm_psb_private *dev_priv); +extern uint32_t psb_fence_advance_sequence(struct drm_device *dev, + uint32_t class); +extern int psb_fence_emit_sequence(struct ttm_fence_device *fdev, + uint32_t fence_class, + uint32_t flags, uint32_t *sequence, + unsigned long *timeout_jiffies); +extern void psb_fence_error(struct drm_device *dev, + uint32_t class, + uint32_t sequence, uint32_t type, int error); +extern int psb_ttm_fence_device_init(struct ttm_fence_device *fdev); + +/*MSVDX stuff*/ +extern void psb_msvdx_irq_off(struct drm_psb_private *dev_priv); +extern void psb_msvdx_irq_on(struct drm_psb_private *dev_priv); + +/* + *psb_gtt.c + */ +extern int psb_gtt_init(struct psb_gtt *pg, int resume); +extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages, + unsigned offset_pages, unsigned num_pages, + unsigned desired_tile_stride, + unsigned hw_tile_stride, int type); +extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages, + unsigned num_pages, + unsigned desired_tile_stride, + unsigned hw_tile_stride); + +extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev); +extern void psb_gtt_takedown(struct psb_gtt *pg, int free); + +/* + *psb_fb.c + */ +extern int psbfb_probed(struct drm_device *dev); +extern int psbfb_remove(struct drm_device *dev, + struct drm_framebuffer *fb); +extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern void psbfb_suspend(struct drm_device *dev); +extern void psbfb_resume(struct drm_device *dev); + +/* + *psb_reset.c + */ + +extern void psb_reset(struct drm_psb_private *dev_priv, int reset_2d); +extern void psb_schedule_watchdog(struct drm_psb_private *dev_priv); +extern void psb_watchdog_init(struct drm_psb_private *dev_priv); +extern void psb_watchdog_takedown(struct drm_psb_private *dev_priv); +extern void psb_print_pagefault(struct drm_psb_private *dev_priv); + +/* + *psb_xhw.c + */ + +extern int psb_xhw_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_xhw_init_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); +extern int psb_xhw_init(struct drm_device *dev); +extern void psb_xhw_takedown(struct drm_psb_private *dev_priv); +extern void psb_xhw_init_takedown(struct drm_psb_private *dev_priv, + struct drm_file *file_priv, int closing); +extern int psb_xhw_scene_bind_fire(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, + uint32_t fire_flags, + uint32_t hw_context, + uint32_t *cookie, + uint32_t *oom_cmds, + uint32_t num_oom_cmds, + uint32_t offset, + uint32_t engine, uint32_t flags); +extern int psb_xhw_fire_raster(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, + uint32_t fire_flags); +extern int psb_xhw_scene_info(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, uint32_t w, + uint32_t h, uint32_t *hw_cookie, + uint32_t *bo_size, uint32_t *clear_p_start, + uint32_t *clear_num_pages); + +extern int psb_xhw_reset_dpm(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf); +extern int psb_xhw_check_lockup(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, uint32_t *value); +extern int psb_xhw_ta_mem_info(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, + uint32_t pages, + uint32_t * hw_cookie, + uint32_t * size, + uint32_t * ta_min_size); +extern int psb_xhw_ta_oom(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, uint32_t *cookie); +extern void psb_xhw_ta_oom_reply(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, + uint32_t *cookie, + uint32_t *bca, + uint32_t *rca, uint32_t *flags); +extern int psb_xhw_vistest(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf); +extern int psb_xhw_handler(struct drm_psb_private *dev_priv); +extern int psb_xhw_resume(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf); +extern void psb_xhw_fire_reply(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, uint32_t *cookie); +extern int psb_xhw_ta_mem_load(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf, + uint32_t flags, + uint32_t param_offset, + uint32_t pt_offset, uint32_t *hw_cookie); +extern void psb_xhw_clean_buf(struct drm_psb_private *dev_priv, + struct psb_xhw_buf *buf); + +/* + *psb_schedule.c: HW bug fixing. + */ + +#ifdef FIX_TG_16 + +extern void psb_2d_unlock(struct drm_psb_private *dev_priv); +extern void psb_2d_lock(struct drm_psb_private *dev_priv); +extern int psb_2d_trylock(struct drm_psb_private *dev_priv); +extern void psb_resume_ta_2d_idle(struct drm_psb_private *dev_priv); +extern int psb_2d_trylock(struct drm_psb_private *dev_priv); +extern void psb_2d_atomic_unlock(struct drm_psb_private *dev_priv); +#else + +#define psb_2d_lock(_dev_priv) mutex_lock(&(_dev_priv)->mutex_2d) +#define psb_2d_unlock(_dev_priv) mutex_unlock(&(_dev_priv)->mutex_2d) + +#endif + +/* modesetting */ +extern void psb_modeset_init(struct drm_device *dev); +extern void psb_modeset_cleanup(struct drm_device *dev); + + +/* + *Utilities + */ +#define DRM_DRIVER_PRIVATE_T struct drm_psb_private + +static inline u32 MSG_READ32(uint port, uint offset) +{ + int mcr = (0xD0<<24) | (port << 16) | (offset << 8); + outl(0x800000D0, 0xCF8); + outl(mcr, 0xCFC); + outl(0x800000D4, 0xCF8); + return inl(0xcfc); +} +static inline void MSG_WRITE32(uint port, uint offset, u32 value) +{ + int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; + outl(0x800000D4, 0xCF8); + outl(value, 0xcfc); + outl(0x800000D0, 0xCF8); + outl(mcr, 0xCFC); +} + +static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + + return ioread32(dev_priv->vdc_reg + (reg)); +} + +#define REG_READ(reg) REGISTER_READ(dev, (reg)) +static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg, + uint32_t val) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + + iowrite32((val), dev_priv->vdc_reg + (reg)); +} + +#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val)) + +static inline void REGISTER_WRITE16(struct drm_device *dev, + uint32_t reg, uint32_t val) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + + iowrite16((val), dev_priv->vdc_reg + (reg)); +} + +#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val)) + +static inline void REGISTER_WRITE8(struct drm_device *dev, + uint32_t reg, uint32_t val) +{ + struct drm_psb_private *dev_priv = dev->dev_private; + + iowrite8((val), dev_priv->vdc_reg + (reg)); +} + +#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val)) + +#define PSB_ALIGN_TO(_val, _align) \ + (((_val) + ((_align) - 1)) & ~((_align) - 1)) +#define PSB_WVDC32(_val, _offs) \ + iowrite32(_val, dev_priv->vdc_reg + (_offs)) +#define PSB_RVDC32(_offs) \ + ioread32(dev_priv->vdc_reg + (_offs)) +#define PSB_WSGX32(_val, _offs) \ + iowrite32(_val, dev_priv->sgx_reg + (_offs)) +#define PSB_RSGX32(_offs) \ + ioread32(dev_priv->sgx_reg + (_offs)) +#define PSB_WMSVDX32(_val, _offs) \ + iowrite32(_val, dev_priv->msvdx_reg + (_offs)) +#define PSB_RMSVDX32(_offs) \ + ioread32(dev_priv->msvdx_reg + (_offs)) + +#define PSB_ALPL(_val, _base) \ + (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) +#define PSB_ALPLM(_val, _base) \ + ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK)) + +#define PSB_D_RENDER (1 << 16) + +#define PSB_D_GENERAL (1 << 0) +#define PSB_D_INIT (1 << 1) +#define PSB_D_IRQ (1 << 2) +#define PSB_D_FW (1 << 3) +#define PSB_D_PERF (1 << 4) +#define PSB_D_TMP (1 << 5) +#define PSB_D_PM (1 << 6) + +extern int drm_psb_debug; +extern int drm_psb_no_fb; +extern int drm_psb_disable_vsync; +extern int drm_idle_check_interval; +extern int drm_psb_ospm; + +#define PSB_DEBUG_FW(_fmt, _arg...) \ + PSB_DEBUG(PSB_D_FW, _fmt, ##_arg) +#define PSB_DEBUG_GENERAL(_fmt, _arg...) \ + PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg) +#define PSB_DEBUG_INIT(_fmt, _arg...) \ + PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg) +#define PSB_DEBUG_IRQ(_fmt, _arg...) \ + PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg) +#define PSB_DEBUG_RENDER(_fmt, _arg...) \ + PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg) +#define PSB_DEBUG_PERF(_fmt, _arg...) \ + PSB_DEBUG(PSB_D_PERF, _fmt, ##_arg) +#define PSB_DEBUG_TMP(_fmt, _arg...) \ + PSB_DEBUG(PSB_D_TMP, _fmt, ##_arg) +#define PSB_DEBUG_PM(_fmt, _arg...) \ + PSB_DEBUG(PSB_D_PM, _fmt, ##_arg) + +#if DRM_DEBUG_CODE +#define PSB_DEBUG(_flag, _fmt, _arg...) \ + do { \ + if (unlikely((_flag) & drm_psb_debug)) \ + printk(KERN_DEBUG \ + "[psb:0x%02x:%s] " _fmt , _flag, \ + __func__ , ##_arg); \ + } while (0) +#else +#define PSB_DEBUG(_fmt, _arg...) do { } while (0) +#endif + +#define IS_POULSBO(dev) (((dev)->pci_device == 0x8108) || \ + ((dev)->pci_device == 0x8109)) + +#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100) + +#endif --- /dev/null +++ b/drivers/staging/psb/psb_fb.c @@ -0,0 +1,1687 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + * develop this driver. + * + **************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "psb_drv.h" +#include "intel_reg.h" +#include "intel_drv.h" +#include "ttm/ttm_userobj_api.h" +#include "psb_fb.h" +#include "psb_sgx.h" + +static int fill_fb_bitfield(struct fb_var_screeninfo *var, int depth) +{ + switch (depth) { + case 8: + var->red.offset = 0; + var->green.offset = 0; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 15: + var->red.offset = 10; + var->green.offset = 5; + var->blue.offset = 0; + var->red.length = 5; + var->green.length = 5; + var->blue.length = 5; + var->transp.length = 1; + var->transp.offset = 15; + break; + case 16: + var->red.offset = 11; + var->green.offset = 5; + var->blue.offset = 0; + var->red.length = 5; + var->green.length = 6; + var->blue.length = 5; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 24: + var->red.offset = 16; + var->green.offset = 8; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 0; + var->transp.offset = 0; + break; + case 32: + var->red.offset = 16; + var->green.offset = 8; + var->blue.offset = 0; + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; + var->transp.length = 8; + var->transp.offset = 24; + break; + default: + return -EINVAL; + } + + return 0; +} + +static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb); +static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb, + struct drm_file *file_priv, + unsigned int *handle); + +static const struct drm_framebuffer_funcs psb_fb_funcs = { + .destroy = psb_user_framebuffer_destroy, + .create_handle = psb_user_framebuffer_create_handle, +}; + +struct psbfb_par { + struct drm_device *dev; + struct psb_framebuffer *psbfb; + + int dpms_state; + + int crtc_count; + /* crtc currently bound to this */ + uint32_t crtc_ids[2]; +}; + +#define CMAP_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16) + +static int psbfb_setcolreg(unsigned regno, unsigned red, unsigned green, + unsigned blue, unsigned transp, + struct fb_info *info) +{ + struct psbfb_par *par = info->par; + struct drm_framebuffer *fb = &par->psbfb->base; + uint32_t v; + + if (!fb) + return -ENOMEM; + + if (regno > 255) + return 1; + +#if 0 /* JB: not drop, check that this works */ + if (fb->bits_per_pixel == 8) { + list_for_each_entry(crtc, &dev->mode_config.crtc_list, + head) { + for (i = 0; i < par->crtc_count; i++) + if (crtc->base.id == par->crtc_ids[i]) + break; + + if (i == par->crtc_count) + continue; + + if (crtc->funcs->gamma_set) + crtc->funcs->gamma_set(crtc, red, green, + blue, regno); + } + return 0; + } +#endif + + red = CMAP_TOHW(red, info->var.red.length); + blue = CMAP_TOHW(blue, info->var.blue.length); + green = CMAP_TOHW(green, info->var.green.length); + transp = CMAP_TOHW(transp, info->var.transp.length); + + v = (red << info->var.red.offset) | + (green << info->var.green.offset) | + (blue << info->var.blue.offset) | + (transp << info->var.transp.offset); + + if (regno < 16) { + switch (fb->bits_per_pixel) { + case 16: + ((uint32_t *) info->pseudo_palette)[regno] = v; + break; + case 24: + case 32: + ((uint32_t *) info->pseudo_palette)[regno] = v; + break; + } + } + + return 0; +} + +static struct drm_display_mode *psbfb_find_first_mode(struct + fb_var_screeninfo + *var, + struct fb_info *info, + struct drm_crtc + *crtc) +{ + struct psbfb_par *par = info->par; + struct drm_device *dev = par->dev; + struct drm_display_mode *drm_mode; + struct drm_display_mode *last_mode = NULL; + struct drm_connector *connector; + int found; + + found = 0; + list_for_each_entry(connector, &dev->mode_config.connector_list, + head) { + if (connector->encoder && connector->encoder->crtc == crtc) { + found = 1; + break; + } + } + + /* found no connector, bail */ + if (!found) + return NULL; + + found = 0; + list_for_each_entry(drm_mode, &connector->modes, head) { + if (drm_mode->hdisplay == var->xres && + drm_mode->vdisplay == var->yres + && drm_mode->clock != 0) { + found = 1; + last_mode = drm_mode; + } + } + + /* No mode matching mode found */ + if (!found) + return NULL; + + return last_mode; +} + +static int psbfb_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) +{ + struct psbfb_par *par = info->par; + struct psb_framebuffer *psbfb = par->psbfb; + struct drm_device *dev = par->dev; + int ret; + int depth; + int pitch; + int bpp = var->bits_per_pixel; + + if (!psbfb) + return -ENOMEM; + + if (!var->pixclock) + return -EINVAL; + + /* don't support virtuals for now */ + if (var->xres_virtual > var->xres) + return -EINVAL; + + if (var->yres_virtual > var->yres) + return -EINVAL; + + switch (bpp) { +#if 0 /* JB: for now only support true color */ + case 8: + depth = 8; + break; +#endif + case 16: + depth = (var->green.length == 6) ? 16 : 15; + break; + case 24: /* assume this is 32bpp / depth 24 */ + bpp = 32; + /* fallthrough */ + case 32: + depth = (var->transp.length > 0) ? 32 : 24; + break; + default: + return -EINVAL; + } + + pitch = ((var->xres * ((bpp + 1) / 8)) + 0x3f) & ~0x3f; + + /* Check that we can resize */ + if ((pitch * var->yres) > (psbfb->bo->num_pages << PAGE_SHIFT)) { +#if 1 + /* Need to resize the fb object. + * But the generic fbdev code doesn't really understand + * that we can do this. So disable for now. + */ + DRM_INFO("Can't support requested size, too big!\n"); + return -EINVAL; +#else + struct drm_psb_private *dev_priv = psb_priv(dev); + struct ttm_bo_device *bdev = &dev_priv->bdev; + struct ttm_buffer_object *fbo = NULL; + struct ttm_bo_kmap_obj tmp_kmap; + + /* a temporary BO to check if we could resize in setpar. + * Therefore no need to set NO_EVICT. + */ + ret = ttm_buffer_object_create(bdev, + pitch * var->yres, + ttm_bo_type_kernel, + TTM_PL_FLAG_TT | + TTM_PL_FLAG_VRAM | + TTM_PL_FLAG_NO_EVICT, + 0, 0, &fbo); + if (ret || !fbo) + return -ENOMEM; + + ret = ttm_bo_kmap(fbo, 0, fbo->num_pages, &tmp_kmap); + if (ret) { + ttm_bo_usage_deref_unlocked(&fbo); + return -EINVAL; + } + + ttm_bo_kunmap(&tmp_kmap); + /* destroy our current fbo! */ + ttm_bo_usage_deref_unlocked(&fbo); +#endif + } + + ret = fill_fb_bitfield(var, depth); + if (ret) + return ret; + +#if 1 + /* Here we walk the output mode list and look for modes. If we haven't + * got it, then bail. Not very nice, so this is disabled. + * In the set_par code, we create our mode based on the incoming + * parameters. Nicer, but may not be desired by some. + */ + { + struct drm_crtc *crtc; + int i; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, + head) { + struct intel_crtc *intel_crtc = + to_intel_crtc(crtc); + + for (i = 0; i < par->crtc_count; i++) + if (crtc->base.id == par->crtc_ids[i]) + break; + + if (i == par->crtc_count) + continue; + + if (intel_crtc->mode_set.num_connectors == 0) + continue; + + if (!psbfb_find_first_mode(&info->var, info, crtc)) + return -EINVAL; + } + } +#else + (void) i; + (void) dev; /* silence warnings */ + (void) crtc; + (void) drm_mode; + (void) connector; +#endif + + return 0; +} + +/* this will let fbcon do the mode init */ +static int psbfb_set_par(struct fb_info *info) +{ + struct psbfb_par *par = info->par; + struct psb_framebuffer *psbfb = par->psbfb; + struct drm_framebuffer *fb = &psbfb->base; + struct drm_device *dev = par->dev; + struct fb_var_screeninfo *var = &info->var; + struct drm_psb_private *dev_priv = dev->dev_private; + struct drm_display_mode *drm_mode; + int pitch; + int depth; + int bpp = var->bits_per_pixel; + + if (!fb) + return -ENOMEM; + + switch (bpp) { + case 8: + depth = 8; + break; + case 16: + depth = (var->green.length == 6) ? 16 : 15; + break; + case 24: /* assume this is 32bpp / depth 24 */ + bpp = 32; + /* fallthrough */ + case 32: + depth = (var->transp.length > 0) ? 32 : 24; + break; + default: + DRM_ERROR("Illegal BPP\n"); + return -EINVAL; + } + + pitch = ((var->xres * ((bpp + 1) / 8)) + 0x3f) & ~0x3f; + + if ((pitch * var->yres) > (psbfb->bo->num_pages << PAGE_SHIFT)) { +#if 1 + /* Need to resize the fb object. + * But the generic fbdev code doesn't really understand + * that we can do this. So disable for now. + */ + DRM_INFO("Can't support requested size, too big!\n"); + return -EINVAL; +#else + int ret; + struct ttm_buffer_object *fbo = NULL, *tfbo; + struct ttm_bo_kmap_obj tmp_kmap, tkmap; + + ret = ttm_buffer_object_create(bdev, + pitch * var->yres, + ttm_bo_type_kernel, + TTM_PL_FLAG_MEM_TT | + TTM_PL_FLAG_MEM_VRAM | + TTM_PL_FLAG_NO_EVICT, + 0, 0, &fbo); + if (ret || !fbo) { + DRM_ERROR + ("failed to allocate new resized framebuffer\n"); + return -ENOMEM; + } + + ret = ttm_bo_kmap(fbo, 0, fbo->num_pages, &tmp_kmap); + if (ret) { + DRM_ERROR("failed to kmap framebuffer.\n"); + ttm_bo_usage_deref_unlocked(&fbo); + return -EINVAL; + } + + DRM_DEBUG("allocated %dx%d fb: 0x%08lx, bo %p\n", + fb->width, fb->height, fb->offset, fbo); + + /* set new screen base */ + info->screen_base = tmp_kmap.virtual; + + tkmap = fb->kmap; + fb->kmap = tmp_kmap; + ttm_bo_kunmap(&tkmap); + + tfbo = fb->bo; + fb->bo = fbo; + ttm_bo_usage_deref_unlocked(&tfbo); +#endif + } + + psbfb->offset = psbfb->bo->offset - dev_priv->pg->gatt_start; + fb->width = var->xres; + fb->height = var->yres; + fb->bits_per_pixel = bpp; + fb->pitch = pitch; + fb->depth = depth; + + info->fix.line_length = psbfb->base.pitch; + info->fix.visual = + (psbfb->base.depth == + 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; + + /* some fbdev's apps don't want these to change */ + info->fix.smem_start = dev->mode_config.fb_base + psbfb->offset; + +#if 0 + /* relates to resize - disable */ + info->fix.smem_len = info->fix.line_length * var->yres; + info->screen_size = info->fix.smem_len; /* ??? */ +#endif + + /* Should we walk the output's modelist or just create our own ??? + * For now, we create and destroy a mode based on the incoming + * parameters. But there's commented out code below which scans + * the output list too. + */ +#if 1 + /* This code is now in the for loop futher down. */ +#endif + + { + struct drm_crtc *crtc; + int ret; + int i; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, + head) { + struct intel_crtc *intel_crtc = + to_intel_crtc(crtc); + + for (i = 0; i < par->crtc_count; i++) + if (crtc->base.id == par->crtc_ids[i]) + break; + + if (i == par->crtc_count) + continue; + + if (intel_crtc->mode_set.num_connectors == 0) + continue; + +#if 1 + drm_mode = + psbfb_find_first_mode(&info->var, info, crtc); + if (!drm_mode) + DRM_ERROR("No matching mode found\n"); + intel_crtc->mode_set.mode = drm_mode; +#endif + +#if 0 /* FIXME: TH */ + if (crtc->fb == intel_crtc->mode_set.fb) { +#endif + DRM_DEBUG + ("setting mode on crtc %p with id %u\n", + crtc, crtc->base.id); + ret = + crtc->funcs-> + set_config(&intel_crtc->mode_set); + if (ret) { + DRM_ERROR("Failed setting mode\n"); + return ret; + } +#if 0 + } +#endif + } + DRM_DEBUG("Set par returned OK.\n"); + return 0; + } + + return 0; +} + +static int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf, + unsigned size) +{ + int ret = 0; + int i; + unsigned submit_size; + + while (size > 0) { + submit_size = (size < 0x60) ? size : 0x60; + size -= submit_size; + ret = psb_2d_wait_available(dev_priv, submit_size); + if (ret) + return ret; + + submit_size <<= 2; + for (i = 0; i < submit_size; i += 4) { + PSB_WSGX32(*cmdbuf++, PSB_SGX_2D_SLAVE_PORT + i); + } + (void)PSB_RSGX32(PSB_SGX_2D_SLAVE_PORT + i - 4); + } + return 0; +} + +static int psb_accel_2d_fillrect(struct drm_psb_private *dev_priv, + uint32_t dst_offset, uint32_t dst_stride, + uint32_t dst_format, uint16_t dst_x, + uint16_t dst_y, uint16_t size_x, + uint16_t size_y, uint32_t fill) +{ + uint32_t buffer[10]; + uint32_t *buf; + + buf = buffer; + + *buf++ = PSB_2D_FENCE_BH; + + *buf++ = + PSB_2D_DST_SURF_BH | dst_format | (dst_stride << + PSB_2D_DST_STRIDE_SHIFT); + *buf++ = dst_offset; + + *buf++ = + PSB_2D_BLIT_BH | + PSB_2D_ROT_NONE | + PSB_2D_COPYORDER_TL2BR | + PSB_2D_DSTCK_DISABLE | + PSB_2D_SRCCK_DISABLE | PSB_2D_USE_FILL | PSB_2D_ROP3_PATCOPY; + + *buf++ = fill << PSB_2D_FILLCOLOUR_SHIFT; + *buf++ = + (dst_x << PSB_2D_DST_XSTART_SHIFT) | (dst_y << + PSB_2D_DST_YSTART_SHIFT); + *buf++ = + (size_x << PSB_2D_DST_XSIZE_SHIFT) | (size_y << + PSB_2D_DST_YSIZE_SHIFT); + *buf++ = PSB_2D_FLUSH_BH; + + return psbfb_2d_submit(dev_priv, buffer, buf - buffer); +} + +static void psbfb_fillrect_accel(struct fb_info *info, + const struct fb_fillrect *r) +{ + struct psbfb_par *par = info->par; + struct psb_framebuffer *psbfb = par->psbfb; + struct drm_framebuffer *fb = &psbfb->base; + struct drm_psb_private *dev_priv = par->dev->dev_private; + uint32_t offset; + uint32_t stride; + uint32_t format; + + if (!fb) + return; + + offset = psbfb->offset; + stride = fb->pitch; + + switch (fb->depth) { + case 8: + format = PSB_2D_DST_332RGB; + break; + case 15: + format = PSB_2D_DST_555RGB; + break; + case 16: + format = PSB_2D_DST_565RGB; + break; + case 24: + case 32: + /* this is wrong but since we don't do blending its okay */ + format = PSB_2D_DST_8888ARGB; + break; + default: + /* software fallback */ + cfb_fillrect(info, r); + return; + } + + psb_accel_2d_fillrect(dev_priv, + offset, stride, format, + r->dx, r->dy, r->width, r->height, r->color); +} + +static void psbfb_fillrect(struct fb_info *info, + const struct fb_fillrect *rect) +{ + struct psbfb_par *par = info->par; + struct drm_device *dev = par->dev; + struct drm_psb_private *dev_priv = dev->dev_private; + + if (unlikely(info->state != FBINFO_STATE_RUNNING)) + return; + + if (info->flags & FBINFO_HWACCEL_DISABLED) + return cfb_fillrect(info, rect); + + if (psb_2d_trylock(dev_priv)) { + psb_check_power_state(dev, PSB_DEVICE_SGX); + psbfb_fillrect_accel(info, rect); + psb_2d_unlock(dev_priv); + if (drm_psb_ospm && IS_MRST(dev)) + schedule_delayed_work(&dev_priv->scheduler.wq, 1); + } else + cfb_fillrect(info, rect); +} + +uint32_t psb_accel_2d_copy_direction(int xdir, int ydir) +{ + if (xdir < 0) + return (ydir < + 0) ? PSB_2D_COPYORDER_BR2TL : + PSB_2D_COPYORDER_TR2BL; + else + return (ydir < + 0) ? PSB_2D_COPYORDER_BL2TR : + PSB_2D_COPYORDER_TL2BR; +} + +/* + * @srcOffset in bytes + * @srcStride in bytes + * @srcFormat psb 2D format defines + * @dstOffset in bytes + * @dstStride in bytes + * @dstFormat psb 2D format defines + * @srcX offset in pixels + * @srcY offset in pixels + * @dstX offset in pixels + * @dstY offset in pixels + * @sizeX of the copied area + * @sizeY of the copied area + */ +static int psb_accel_2d_copy(struct drm_psb_private *dev_priv, + uint32_t src_offset, uint32_t src_stride, + uint32_t src_format, uint32_t dst_offset, + uint32_t dst_stride, uint32_t dst_format, + uint16_t src_x, uint16_t src_y, + uint16_t dst_x, uint16_t dst_y, + uint16_t size_x, uint16_t size_y) +{ + uint32_t blit_cmd; + uint32_t buffer[10]; + uint32_t *buf; + uint32_t direction; + + buf = buffer; + + direction = + psb_accel_2d_copy_direction(src_x - dst_x, src_y - dst_y); + + if (direction == PSB_2D_COPYORDER_BR2TL || + direction == PSB_2D_COPYORDER_TR2BL) { + src_x += size_x - 1; + dst_x += size_x - 1; + } + if (direction == PSB_2D_COPYORDER_BR2TL || + direction == PSB_2D_COPYORDER_BL2TR) { + src_y += size_y - 1; + dst_y += size_y - 1; + } + + blit_cmd = + PSB_2D_BLIT_BH | + PSB_2D_ROT_NONE | + PSB_2D_DSTCK_DISABLE | + PSB_2D_SRCCK_DISABLE | + PSB_2D_USE_PAT | PSB_2D_ROP3_SRCCOPY | direction; + + *buf++ = PSB_2D_FENCE_BH; + *buf++ = + PSB_2D_DST_SURF_BH | dst_format | (dst_stride << + PSB_2D_DST_STRIDE_SHIFT); + *buf++ = dst_offset; + *buf++ = + PSB_2D_SRC_SURF_BH | src_format | (src_stride << + PSB_2D_SRC_STRIDE_SHIFT); + *buf++ = src_offset; + *buf++ = + PSB_2D_SRC_OFF_BH | (src_x << PSB_2D_SRCOFF_XSTART_SHIFT) | + (src_y << PSB_2D_SRCOFF_YSTART_SHIFT); + *buf++ = blit_cmd; + *buf++ = + (dst_x << PSB_2D_DST_XSTART_SHIFT) | (dst_y << + PSB_2D_DST_YSTART_SHIFT); + *buf++ = + (size_x << PSB_2D_DST_XSIZE_SHIFT) | (size_y << + PSB_2D_DST_YSIZE_SHIFT); + *buf++ = PSB_2D_FLUSH_BH; + + return psbfb_2d_submit(dev_priv, buffer, buf - buffer); +} + +static void psbfb_copyarea_accel(struct fb_info *info, + const struct fb_copyarea *a) +{ + struct psbfb_par *par = info->par; + struct psb_framebuffer *psbfb = par->psbfb; + struct drm_framebuffer *fb = &psbfb->base; + struct drm_psb_private *dev_priv = par->dev->dev_private; + uint32_t offset; + uint32_t stride; + uint32_t src_format; + uint32_t dst_format; + + if (!fb) + return; + + offset = psbfb->offset; + stride = fb->pitch; + + switch (fb->depth) { + case 8: + src_format = PSB_2D_SRC_332RGB; + dst_format = PSB_2D_DST_332RGB; + break; + case 15: + src_format = PSB_2D_SRC_555RGB; + dst_format = PSB_2D_DST_555RGB; + break; + case 16: + src_format = PSB_2D_SRC_565RGB; + dst_format = PSB_2D_DST_565RGB; + break; + case 24: + case 32: + /* this is wrong but since we don't do blending its okay */ + src_format = PSB_2D_SRC_8888ARGB; + dst_format = PSB_2D_DST_8888ARGB; + break; + default: + /* software fallback */ + cfb_copyarea(info, a); + return; + } + + psb_accel_2d_copy(dev_priv, + offset, stride, src_format, + offset, stride, dst_format, + a->sx, a->sy, a->dx, a->dy, a->width, a->height); +} + +static void psbfb_copyarea(struct fb_info *info, + const struct fb_copyarea *region) +{ + struct psbfb_par *par = info->par; + struct drm_device *dev = par->dev; + struct drm_psb_private *dev_priv = dev->dev_private; + + if (unlikely(info->state != FBINFO_STATE_RUNNING)) + return; + + if (info->flags & FBINFO_HWACCEL_DISABLED) + return cfb_copyarea(info, region); + + if (psb_2d_trylock(dev_priv)) { + psb_check_power_state(dev, PSB_DEVICE_SGX); + psbfb_copyarea_accel(info, region); + psb_2d_unlock(dev_priv); + if (drm_psb_ospm && IS_MRST(dev)) + schedule_delayed_work(&dev_priv->scheduler.wq, 1); + } else + cfb_copyarea(info, region); +} + +void psbfb_imageblit(struct fb_info *info, const struct fb_image *image) +{ + if (unlikely(info->state != FBINFO_STATE_RUNNING)) + return; + + cfb_imageblit(info, image); +} + +static void psbfb_onoff(struct fb_info *info, int dpms_mode) +{ + struct psbfb_par *par = info->par; + struct drm_device *dev = par->dev; + struct drm_crtc *crtc; + struct drm_encoder *encoder; + int i; + + /* + * For each CRTC in this fb, find all associated encoders + * and turn them off, then turn off the CRTC. + */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct drm_crtc_helper_funcs *crtc_funcs = + crtc->helper_private; + + for (i = 0; i < par->crtc_count; i++) + if (crtc->base.id == par->crtc_ids[i]) + break; + + if (i == par->crtc_count) + continue; + + if (dpms_mode == DRM_MODE_DPMS_ON) + crtc_funcs->dpms(crtc, dpms_mode); + + /* Found a CRTC on this fb, now find encoders */ + list_for_each_entry(encoder, + &dev->mode_config.encoder_list, head) { + if (encoder->crtc == crtc) { + struct drm_encoder_helper_funcs + *encoder_funcs; + encoder_funcs = encoder->helper_private; + encoder_funcs->dpms(encoder, dpms_mode); + } + } + + if (dpms_mode == DRM_MODE_DPMS_OFF) + crtc_funcs->dpms(crtc, dpms_mode); + } +} + +static int psbfb_blank(int blank_mode, struct fb_info *info) +{ + struct psbfb_par *par = info->par; + + par->dpms_state = blank_mode; + PSB_DEBUG_PM("psbfb_blank \n"); + switch (blank_mode) { + case FB_BLANK_UNBLANK: + psbfb_onoff(info, DRM_MODE_DPMS_ON); + break; + case FB_BLANK_NORMAL: + psbfb_onoff(info, DRM_MODE_DPMS_STANDBY); + break; + case FB_BLANK_HSYNC_SUSPEND: + psbfb_onoff(info, DRM_MODE_DPMS_STANDBY); + break; + case FB_BLANK_VSYNC_SUSPEND: + psbfb_onoff(info, DRM_MODE_DPMS_SUSPEND); + break; + case FB_BLANK_POWERDOWN: + psbfb_onoff(info, DRM_MODE_DPMS_OFF); + break; + } + + return 0; +} + + +static int psbfb_kms_off(struct drm_device *dev, int suspend) +{ + struct drm_framebuffer *fb = 0; + DRM_DEBUG("psbfb_kms_off_ioctl\n"); + + mutex_lock(&dev->mode_config.mutex); + list_for_each_entry(fb, &dev->mode_config.fb_list, head) { + struct fb_info *info = fb->fbdev; + + if (suspend) + fb_set_suspend(info, 1); + } + mutex_unlock(&dev->mode_config.mutex); + + return 0; +} + +int psbfb_kms_off_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + int ret; + + if (drm_psb_no_fb) + return 0; + acquire_console_sem(); + ret = psbfb_kms_off(dev, 0); + release_console_sem(); + + return ret; +} + +static int psbfb_kms_on(struct drm_device *dev, int resume) +{ + struct drm_framebuffer *fb = 0; + + DRM_DEBUG("psbfb_kms_on_ioctl\n"); + + mutex_lock(&dev->mode_config.mutex); + list_for_each_entry(fb, &dev->mode_config.fb_list, head) { + struct fb_info *info = fb->fbdev; + + if (resume) + fb_set_suspend(info, 0); + + } + mutex_unlock(&dev->mode_config.mutex); + + return 0; +} + +int psbfb_kms_on_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + int ret; + + if (drm_psb_no_fb) + return 0; + acquire_console_sem(); + ret = psbfb_kms_on(dev, 0); + release_console_sem(); + drm_helper_disable_unused_functions(dev); + return ret; +} + +void psbfb_suspend(struct drm_device *dev) +{ + acquire_console_sem(); + psbfb_kms_off(dev, 1); + release_console_sem(); +} + +void psbfb_resume(struct drm_device *dev) +{ + acquire_console_sem(); + psbfb_kms_on(dev, 1); + release_console_sem(); + drm_helper_disable_unused_functions(dev); +} + +static int psbfb_mmap(struct fb_info *info, struct vm_area_struct *vma) +{ + struct psbfb_par *par = info->par; + struct psb_framebuffer *psbfb = par->psbfb; + struct ttm_buffer_object *bo = psbfb->bo; + unsigned long size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; + unsigned long offset = vma->vm_pgoff; + + if (vma->vm_pgoff != 0) + return -EINVAL; + if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) + return -EINVAL; + if (offset + size > bo->num_pages) + return -EINVAL; + + mutex_lock(&bo->mutex); + if (!psbfb->addr_space) + psbfb->addr_space = vma->vm_file->f_mapping; + mutex_unlock(&bo->mutex); + + return ttm_fbdev_mmap(vma, bo); +} + +int psbfb_sync(struct fb_info *info) +{ + struct psbfb_par *par = info->par; + struct drm_psb_private *dev_priv = par->dev->dev_private; + + if (psb_2d_trylock(dev_priv)) { + if (dev_priv->graphics_state == PSB_PWR_STATE_D0i0) + psb_idle_2d(par->dev); + psb_2d_unlock(dev_priv); + } else + udelay(5); + + return 0; +} + +static struct fb_ops psbfb_ops = { + .owner = THIS_MODULE, + .fb_check_var = psbfb_check_var, + .fb_set_par = psbfb_set_par, + .fb_setcolreg = psbfb_setcolreg, + .fb_fillrect = psbfb_fillrect, + .fb_copyarea = psbfb_copyarea, + .fb_imageblit = psbfb_imageblit, + .fb_mmap = psbfb_mmap, + .fb_sync = psbfb_sync, + .fb_blank = psbfb_blank, +}; + +static struct drm_mode_set panic_mode; + +int psbfb_panic(struct notifier_block *n, unsigned long ununsed, + void *panic_str) +{ + DRM_ERROR("panic occurred, switching back to text console\n"); + drm_crtc_helper_set_config(&panic_mode); + + return 0; +} +EXPORT_SYMBOL(psbfb_panic); + +static struct notifier_block paniced = { + .notifier_call = psbfb_panic, +}; + + +static struct drm_framebuffer *psb_framebuffer_create + (struct drm_device *dev, struct drm_mode_fb_cmd *r, + void *mm_private) +{ + struct psb_framebuffer *fb; + int ret; + + fb = kzalloc(sizeof(*fb), GFP_KERNEL); + if (!fb) + return NULL; + + ret = drm_framebuffer_init(dev, &fb->base, &psb_fb_funcs); + + if (ret) + goto err; + + drm_helper_mode_fill_fb_struct(&fb->base, r); + + fb->bo = mm_private; + + return &fb->base; + +err: + kfree(fb); + return NULL; +} + +static struct drm_framebuffer *psb_user_framebuffer_create + (struct drm_device *dev, struct drm_file *filp, + struct drm_mode_fb_cmd *r) +{ + struct ttm_buffer_object *bo = NULL; + uint64_t size; + + bo = ttm_buffer_object_lookup(psb_fpriv(filp)->tfile, r->handle); + if (!bo) + return NULL; + + /* JB: TODO not drop, make smarter */ + size = ((uint64_t) bo->num_pages) << PAGE_SHIFT; + if (size < r->width * r->height * 4) + return NULL; + + /* JB: TODO not drop, refcount buffer */ + return psb_framebuffer_create(dev, r, bo); +} + +int psbfb_create(struct drm_device *dev, uint32_t fb_width, + uint32_t fb_height, uint32_t surface_width, + uint32_t surface_height, struct psb_framebuffer **psbfb_p) +{ + struct fb_info *info; + struct psbfb_par *par; + struct drm_framebuffer *fb; + struct psb_framebuffer *psbfb; + struct ttm_bo_kmap_obj tmp_kmap; + struct drm_mode_fb_cmd mode_cmd; + struct device *device = &dev->pdev->dev; + struct ttm_bo_device *bdev = &psb_priv(dev)->bdev; + int size, aligned_size, ret; + struct ttm_buffer_object *fbo = NULL; + bool is_iomem; + + mode_cmd.width = surface_width; /* crtc->desired_mode->hdisplay; */ + mode_cmd.height = surface_height; /* crtc->desired_mode->vdisplay; */ + + mode_cmd.bpp = 32; + mode_cmd.pitch = mode_cmd.width * ((mode_cmd.bpp + 1) / 8); + mode_cmd.depth = 24; + + size = mode_cmd.pitch * mode_cmd.height; + aligned_size = ALIGN(size, PAGE_SIZE); + ret = ttm_buffer_object_create(bdev, + aligned_size, + ttm_bo_type_kernel, + TTM_PL_FLAG_TT | + TTM_PL_FLAG_VRAM | + TTM_PL_FLAG_NO_EVICT, + 0, 0, 0, NULL, &fbo); + + if (unlikely(ret != 0)) { + DRM_ERROR("failed to allocate framebuffer.\n"); + return -ENOMEM; + } + + mutex_lock(&dev->struct_mutex); + fb = psb_framebuffer_create(dev, &mode_cmd, fbo); + if (!fb) { + DRM_ERROR("failed to allocate fb.\n"); + ret = -ENOMEM; + goto out_err0; + } + psbfb = to_psb_fb(fb); + psbfb->bo = fbo; + + list_add(&fb->filp_head, &dev->mode_config.fb_kernel_list); + info = framebuffer_alloc(sizeof(struct psbfb_par), device); + if (!info) { + ret = -ENOMEM; + goto out_err1; + } + + par = info->par; + par->psbfb = psbfb; + + strcpy(info->fix.id, "psbfb"); + info->fix.type = FB_TYPE_PACKED_PIXELS; + info->fix.visual = FB_VISUAL_TRUECOLOR; + info->fix.type_aux = 0; + info->fix.xpanstep = 1; /* doing it in hw */ + info->fix.ypanstep = 1; /* doing it in hw */ + info->fix.ywrapstep = 0; + info->fix.accel = FB_ACCEL_I830; + info->fix.type_aux = 0; + + info->flags = FBINFO_DEFAULT; + + info->fbops = &psbfb_ops; + + info->fix.line_length = fb->pitch; + info->fix.smem_start = + dev->mode_config.fb_base + psbfb->bo->offset; + info->fix.smem_len = size; + + info->flags = FBINFO_DEFAULT; + + ret = ttm_bo_kmap(psbfb->bo, 0, psbfb->bo->num_pages, &tmp_kmap); + if (ret) { + DRM_ERROR("error mapping fb: %d\n", ret); + goto out_err2; + } + + + info->screen_base = ttm_kmap_obj_virtual(&tmp_kmap, &is_iomem); + info->screen_size = size; + + if (is_iomem) + memset_io(info->screen_base, 0, size); + else + memset(info->screen_base, 0, size); + + info->pseudo_palette = fb->pseudo_palette; + info->var.xres_virtual = fb->width; + info->var.yres_virtual = fb->height; + info->var.bits_per_pixel = fb->bits_per_pixel; + info->var.xoffset = 0; + info->var.yoffset = 0; + info->var.activate = FB_ACTIVATE_NOW; + info->var.height = -1; + info->var.width = -1; + + info->var.xres = fb_width; + info->var.yres = fb_height; + + info->fix.mmio_start = pci_resource_start(dev->pdev, 0); + info->fix.mmio_len = pci_resource_len(dev->pdev, 0); + + info->pixmap.size = 64 * 1024; + info->pixmap.buf_align = 8; + info->pixmap.access_align = 32; + info->pixmap.flags = FB_PIXMAP_SYSTEM; + info->pixmap.scan_align = 1; + + DRM_DEBUG("fb depth is %d\n", fb->depth); + DRM_DEBUG(" pitch is %d\n", fb->pitch); + fill_fb_bitfield(&info->var, fb->depth); + + fb->fbdev = info; + + par->dev = dev; + + /* To allow resizing without swapping buffers */ + printk(KERN_INFO"allocated %dx%d fb: 0x%08lx, bo %p\n", + psbfb->base.width, + psbfb->base.height, psbfb->bo->offset, psbfb->bo); + + if (psbfb_p) + *psbfb_p = psbfb; + + mutex_unlock(&dev->struct_mutex); + + return 0; +out_err2: + unregister_framebuffer(info); +out_err1: + fb->funcs->destroy(fb); +out_err0: + mutex_unlock(&dev->struct_mutex); + ttm_bo_unref(&fbo); + return ret; +} + +static int psbfb_multi_fb_probe_crtc(struct drm_device *dev, + struct drm_crtc *crtc) +{ + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + struct drm_framebuffer *fb = crtc->fb; + struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb); + struct drm_connector *connector; + struct fb_info *info; + struct psbfb_par *par; + struct drm_mode_set *modeset; + unsigned int width, height; + int new_fb = 0; + int ret, i, conn_count; + + if (!drm_helper_crtc_in_use(crtc)) + return 0; + + if (!crtc->desired_mode) + return 0; + + width = crtc->desired_mode->hdisplay; + height = crtc->desired_mode->vdisplay; + + /* is there an fb bound to this crtc already */ + if (!intel_crtc->mode_set.fb) { + ret = + psbfb_create(dev, width, height, width, height, + &psbfb); + if (ret) + return -EINVAL; + new_fb = 1; + } else { + fb = intel_crtc->mode_set.fb; + if ((fb->width < width) || (fb->height < height)) + return -EINVAL; + } + + info = fb->fbdev; + par = info->par; + + modeset = &intel_crtc->mode_set; + modeset->fb = fb; + conn_count = 0; + list_for_each_entry(connector, &dev->mode_config.connector_list, + head) { + if (connector->encoder) + if (connector->encoder->crtc == modeset->crtc) { + modeset->connectors[conn_count] = + connector; + conn_count++; + if (conn_count > INTELFB_CONN_LIMIT) + BUG(); + } + } + + for (i = conn_count; i < INTELFB_CONN_LIMIT; i++) + modeset->connectors[i] = NULL; + + par->crtc_ids[0] = crtc->base.id; + + modeset->num_connectors = conn_count; + if (modeset->mode != modeset->crtc->desired_mode) + modeset->mode = modeset->crtc->desired_mode; + + par->crtc_count = 1; + + if (new_fb) { + info->var.pixclock = -1; + if (register_framebuffer(info) < 0) + return -EINVAL; + } else + psbfb_set_par(info); + + printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, + info->fix.id); + + /* Switch back to kernel console on panic */ + panic_mode = *modeset; + atomic_notifier_chain_register(&panic_notifier_list, &paniced); + printk(KERN_INFO "registered panic notifier\n"); + + return 0; +} + +static int psbfb_multi_fb_probe(struct drm_device *dev) +{ + + struct drm_crtc *crtc; + int ret = 0; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + ret = psbfb_multi_fb_probe_crtc(dev, crtc); + if (ret) + return ret; + } + return ret; +} + +static int psbfb_single_fb_probe(struct drm_device *dev) +{ + struct drm_crtc *crtc; + struct drm_connector *connector; + unsigned int fb_width = (unsigned) -1, fb_height = (unsigned) -1; + unsigned int surface_width = 0, surface_height = 0; + int new_fb = 0; + int crtc_count = 0; + int ret, i, conn_count = 0; + struct fb_info *info; + struct psbfb_par *par; + struct drm_mode_set *modeset = NULL; + struct drm_framebuffer *fb = NULL; + struct psb_framebuffer *psbfb = NULL; + + /* first up get a count of crtcs now in use and + * new min/maxes width/heights */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + if (drm_helper_crtc_in_use(crtc)) { + if (crtc->desired_mode) { + fb = crtc->fb; + if (crtc->desired_mode->hdisplay < + fb_width) + fb_width = + crtc->desired_mode->hdisplay; + + if (crtc->desired_mode->vdisplay < + fb_height) + fb_height = + crtc->desired_mode->vdisplay; + + if (crtc->desired_mode->hdisplay > + surface_width) + surface_width = + crtc->desired_mode->hdisplay; + + if (crtc->desired_mode->vdisplay > + surface_height) + surface_height = + crtc->desired_mode->vdisplay; + + } + crtc_count++; + } + } + + if (crtc_count == 0 || fb_width == -1 || fb_height == -1) { + /* hmm everyone went away - assume VGA cable just fell out + and will come back later. */ + return 0; + } + + /* do we have an fb already? */ + if (list_empty(&dev->mode_config.fb_kernel_list)) { + /* create an fb if we don't have one */ + ret = + psbfb_create(dev, fb_width, fb_height, surface_width, + surface_height, &psbfb); + if (ret) + return -EINVAL; + new_fb = 1; + fb = &psbfb->base; + } else { + fb = list_first_entry(&dev->mode_config.fb_kernel_list, + struct drm_framebuffer, filp_head); + + /* if someone hotplugs something bigger than we have already + * allocated, we are pwned. As really we can't resize an + * fbdev that is in the wild currently due to fbdev not really + * being designed for the lower layers moving stuff around + * under it. - so in the grand style of things - punt. */ + if ((fb->width < surface_width) + || (fb->height < surface_height)) { + DRM_ERROR + ("Framebuffer not large enough to scale" + " console onto.\n"); + return -EINVAL; + } + } + + info = fb->fbdev; + par = info->par; + + crtc_count = 0; + /* okay we need to setup new connector sets in the crtcs */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct intel_crtc *intel_crtc = to_intel_crtc(crtc); + modeset = &intel_crtc->mode_set; + modeset->fb = fb; + conn_count = 0; + list_for_each_entry(connector, + &dev->mode_config.connector_list, + head) { + if (connector->encoder) + if (connector->encoder->crtc == + modeset->crtc) { + modeset->connectors[conn_count] = + connector; + conn_count++; + if (conn_count > + INTELFB_CONN_LIMIT) + BUG(); + } + } + + for (i = conn_count; i < INTELFB_CONN_LIMIT; i++) + modeset->connectors[i] = NULL; + + par->crtc_ids[crtc_count++] = crtc->base.id; + + modeset->num_connectors = conn_count; + if (modeset->mode != modeset->crtc->desired_mode) + modeset->mode = modeset->crtc->desired_mode; + } + par->crtc_count = crtc_count; + + if (new_fb) { + info->var.pixclock = -1; + if (register_framebuffer(info) < 0) + return -EINVAL; + } else + psbfb_set_par(info); + + printk(KERN_INFO "fb%d: %s frame buffer device\n", info->node, + info->fix.id); + + /* Switch back to kernel console on panic */ + panic_mode = *modeset; + atomic_notifier_chain_register(&panic_notifier_list, &paniced); + printk(KERN_INFO "registered panic notifier\n"); + + return 0; +} + +int psbfb_probe(struct drm_device *dev) +{ + int ret = 0; + + DRM_DEBUG("\n"); + + /* something has changed in the lower levels of hell - deal with it + here */ + + /* two modes : a) 1 fb to rule all crtcs. + b) one fb per crtc. + two actions 1) new connected device + 2) device removed. + case a/1 : if the fb surface isn't big enough - + resize the surface fb. + if the fb size isn't big enough - resize fb into surface. + if everything big enough configure the new crtc/etc. + case a/2 : undo the configuration + possibly resize down the fb to fit the new configuration. + case b/1 : see if it is on a new crtc - setup a new fb and add it. + case b/2 : teardown the new fb. + */ + + /* mode a first */ + /* search for an fb */ + if (0 /*i915_fbpercrtc == 1 */) + ret = psbfb_multi_fb_probe(dev); + else + ret = psbfb_single_fb_probe(dev); + + return ret; +} +EXPORT_SYMBOL(psbfb_probe); + +int psbfb_remove(struct drm_device *dev, struct drm_framebuffer *fb) +{ + struct fb_info *info; + struct psb_framebuffer *psbfb = to_psb_fb(fb); + + if (drm_psb_no_fb) + return 0; + + info = fb->fbdev; + + if (info) { + unregister_framebuffer(info); + ttm_bo_kunmap(&psbfb->kmap); + ttm_bo_unref(&psbfb->bo); + framebuffer_release(info); + } + + atomic_notifier_chain_unregister(&panic_notifier_list, &paniced); + memset(&panic_mode, 0, sizeof(struct drm_mode_set)); + return 0; +} +EXPORT_SYMBOL(psbfb_remove); + +static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb, + struct drm_file *file_priv, + unsigned int *handle) +{ + /* JB: TODO currently we can't go from a bo to a handle with ttm */ + (void) file_priv; + *handle = 0; + return 0; +} + +static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb) +{ + struct drm_device *dev = fb->dev; + if (fb->fbdev) + psbfb_remove(dev, fb); + + /* JB: TODO not drop, refcount buffer */ + drm_framebuffer_cleanup(fb); + + kfree(fb); +} + +static const struct drm_mode_config_funcs psb_mode_funcs = { + .fb_create = psb_user_framebuffer_create, + .fb_changed = psbfb_probe, +}; + +static void psb_setup_outputs(struct drm_device *dev) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + struct drm_connector *connector; + + if (IS_MRST(dev)) { + if (dev_priv->iLVDS_enable) + /* Set up integrated LVDS for MRST */ + mrst_lvds_init(dev, &dev_priv->mode_dev); + else { + /* Set up integrated MIPI for MRST */ + mrst_dsi_init(dev, &dev_priv->mode_dev); + } + } else { + intel_lvds_init(dev, &dev_priv->mode_dev); + /* intel_sdvo_init(dev, SDVOB); */ + } + + list_for_each_entry(connector, &dev->mode_config.connector_list, + head) { + struct intel_output *intel_output = + to_intel_output(connector); + struct drm_encoder *encoder = &intel_output->enc; + int crtc_mask = 0, clone_mask = 0; + + /* valid crtcs */ + switch (intel_output->type) { + case INTEL_OUTPUT_SDVO: + crtc_mask = ((1 << 0) | (1 << 1)); + clone_mask = (1 << INTEL_OUTPUT_SDVO); + break; + case INTEL_OUTPUT_LVDS: + if (IS_MRST(dev)) + crtc_mask = (1 << 0); + else + crtc_mask = (1 << 1); + + clone_mask = (1 << INTEL_OUTPUT_LVDS); + break; + case INTEL_OUTPUT_MIPI: + crtc_mask = (1 << 0); + clone_mask = (1 << INTEL_OUTPUT_MIPI); + break; + } + encoder->possible_crtcs = crtc_mask; + encoder->possible_clones = + intel_connector_clones(dev, clone_mask); + } +} + +static void *psb_bo_from_handle(struct drm_device *dev, + struct drm_file *file_priv, + unsigned int handle) +{ + return ttm_buffer_object_lookup(psb_fpriv(file_priv)->tfile, + handle); +} + +static size_t psb_bo_size(struct drm_device *dev, void *bof) +{ + struct ttm_buffer_object *bo = bof; + return bo->num_pages << PAGE_SHIFT; +} + +static size_t psb_bo_offset(struct drm_device *dev, void *bof) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + struct ttm_buffer_object *bo = bof; + + size_t offset = bo->offset - dev_priv->pg->gatt_start; + DRM_DEBUG("Offset %u\n", offset); + return offset; +} + +static int psb_bo_pin_for_scanout(struct drm_device *dev, void *bo) +{ +#if 0 /* JB: Not used for the drop */ + struct ttm_buffer_object *bo = bof; + We should do things like check if + the buffer is in a scanout : able + place.And make sure that its pinned. +#endif + return 0; + } + + static int psb_bo_unpin_for_scanout(struct drm_device *dev, + void *bo) { +#if 0 /* JB: Not used for the drop */ + struct ttm_buffer_object *bo = bof; +#endif + return 0; + } + + void psb_modeset_init(struct drm_device *dev) + { + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + struct intel_mode_device *mode_dev = &dev_priv->mode_dev; + int i; + int num_pipe; + + /* Init mm functions */ + mode_dev->bo_from_handle = psb_bo_from_handle; + mode_dev->bo_size = psb_bo_size; + mode_dev->bo_offset = psb_bo_offset; + mode_dev->bo_pin_for_scanout = psb_bo_pin_for_scanout; + mode_dev->bo_unpin_for_scanout = psb_bo_unpin_for_scanout; + + drm_mode_config_init(dev); + + dev->mode_config.min_width = 0; + dev->mode_config.min_height = 0; + + dev->mode_config.funcs = (void *) &psb_mode_funcs; + + dev->mode_config.max_width = 2048; + dev->mode_config.max_height = 2048; + + /* set memory base */ + dev->mode_config.fb_base = + pci_resource_start(dev->pdev, 0); + + if (IS_MRST(dev)) + num_pipe = 1; + else + num_pipe = 2; + + + for (i = 0; i < num_pipe; i++) + intel_crtc_init(dev, i, mode_dev); + + psb_setup_outputs(dev); + + /* setup fbs */ + /* drm_initial_config(dev, false); */ + } + + void psb_modeset_cleanup(struct drm_device *dev) + { + drm_mode_config_cleanup(dev); + } --- /dev/null +++ b/drivers/staging/psb/psb_fb.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2008, Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Authors: + * Eric Anholt + * + **/ + +#ifndef _PSB_FB_H_ +#define _PSB_FB_H_ + +struct psb_framebuffer { + struct drm_framebuffer base; + struct address_space *addr_space; + struct ttm_buffer_object *bo; + struct ttm_bo_kmap_obj kmap; + uint64_t offset; +}; + +#define to_psb_fb(x) container_of(x, struct psb_framebuffer, base) + + +extern int intel_connector_clones(struct drm_device *dev, int type_mask); + +extern int psb_2d_submit(struct drm_psb_private *, uint32_t *, uint32_t); + +#endif + --- /dev/null +++ b/drivers/staging/psb/psb_fence.c @@ -0,0 +1,343 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + * develop this driver. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ + +#include +#include "psb_drv.h" + +static void psb_print_ta_fence_status(struct ttm_fence_device *fdev) +{ + struct drm_psb_private *dev_priv = + container_of(fdev, struct drm_psb_private, fdev); + struct psb_scheduler_seq *seq = dev_priv->scheduler.seq; + int i; + + for (i=0; i < _PSB_ENGINE_TA_FENCE_TYPES; ++i) { + DRM_INFO("Type 0x%02x, sequence %lu, reported %d\n", + (1 << i), + (unsigned long) seq->sequence, + seq->reported); + seq++; + } +} + +static void psb_poll_ta(struct ttm_fence_device *fdev, + uint32_t waiting_types) +{ + struct drm_psb_private *dev_priv = + container_of(fdev, struct drm_psb_private, fdev); + uint32_t cur_flag = 1; + uint32_t flags = 0; + uint32_t sequence = 0; + uint32_t remaining = 0xFFFFFFFF; + uint32_t diff; + + struct psb_scheduler *scheduler; + struct psb_scheduler_seq *seq; + struct ttm_fence_class_manager *fc = + &fdev->fence_class[PSB_ENGINE_TA]; + + scheduler = &dev_priv->scheduler; + seq = scheduler->seq; + + while (likely(waiting_types & remaining)) { + if (!(waiting_types & cur_flag)) + goto skip; + if (seq->reported) + goto skip; + if (flags == 0) + sequence = seq->sequence; + else if (sequence != seq->sequence) { + ttm_fence_handler(fdev, PSB_ENGINE_TA, + sequence, flags, 0); + sequence = seq->sequence; + flags = 0; + } + flags |= cur_flag; + + /* + * Sequence may not have ended up on the ring yet. + * In that case, report it but don't mark it as + * reported. A subsequent poll will report it again. + */ + + diff = (fc->latest_queued_sequence - sequence) & + fc->sequence_mask; + if (diff < fc->wrap_diff) + seq->reported = 1; + +skip: + cur_flag <<= 1; + remaining <<= 1; + seq++; + } + + if (flags) + ttm_fence_handler(fdev, PSB_ENGINE_TA, sequence, flags, 0); + +} + +static void psb_poll_other(struct ttm_fence_device *fdev, + uint32_t fence_class, uint32_t waiting_types) +{ + struct drm_psb_private *dev_priv = + container_of(fdev, struct drm_psb_private, fdev); + struct ttm_fence_class_manager *fc = + &fdev->fence_class[fence_class]; + uint32_t sequence; + + if (unlikely(!dev_priv)) + return; + + if (waiting_types) { + switch (fence_class) { + case PSB_ENGINE_VIDEO: + sequence = dev_priv->msvdx_current_sequence; + break; + case LNC_ENGINE_ENCODE: + sequence = dev_priv->topaz_current_sequence; + break; + default: + sequence = dev_priv->comm[fence_class << 4]; + break; + } + + ttm_fence_handler(fdev, fence_class, sequence, + _PSB_FENCE_TYPE_EXE, 0); + + switch (fence_class) { + case PSB_ENGINE_2D: + if (dev_priv->fence0_irq_on && !fc->waiting_types) { + psb_2D_irq_off(dev_priv); + dev_priv->fence0_irq_on = 0; + } else if (!dev_priv->fence0_irq_on + && fc->waiting_types) { + psb_2D_irq_on(dev_priv); + dev_priv->fence0_irq_on = 1; + } + break; +#if 0 + /* + * FIXME: MSVDX irq switching + */ + + case PSB_ENGINE_VIDEO: + if (dev_priv->fence2_irq_on && !fc->waiting_types) { + psb_msvdx_irq_off(dev_priv); + dev_priv->fence2_irq_on = 0; + } else if (!dev_priv->fence2_irq_on + && fc->pending_exe_flush) { + psb_msvdx_irq_on(dev_priv); + dev_priv->fence2_irq_on = 1; + } + break; +#endif + default: + return; + } + } +} + +static void psb_fence_poll(struct ttm_fence_device *fdev, + uint32_t fence_class, uint32_t waiting_types) +{ + if (unlikely((PSB_D_PM & drm_psb_debug) && (fence_class == 0))) + PSB_DEBUG_PM("psb_fence_poll: %d\n", fence_class); + switch (fence_class) { + case PSB_ENGINE_TA: + psb_poll_ta(fdev, waiting_types); + break; + default: + psb_poll_other(fdev, fence_class, waiting_types); + break; + } +} + +void psb_fence_error(struct drm_device *dev, + uint32_t fence_class, + uint32_t sequence, uint32_t type, int error) +{ + struct drm_psb_private *dev_priv = psb_priv(dev); + struct ttm_fence_device *fdev = &dev_priv->fdev; + unsigned long irq_flags; + struct ttm_fence_class_manager *fc = + &fdev->fence_class[fence_class]; + + BUG_ON(fence_class >= PSB_NUM_ENGINES); + write_lock_irqsave(&fc->lock, irq_flags); + ttm_fence_handler(fdev, fence_class, sequence, type, error); + write_unlock_irqrestore(&fc->lock, irq_flags); +} + +int psb_fence_emit_sequence(struct ttm_fence_device *fdev, + uint32_t fence_class, + uint32_t flags, uint32_t *sequence, + unsigned long *timeout_jiffies) +{ + struct drm_psb_private *dev_priv = + container_of(fdev, struct drm_psb_private, fdev); + uint32_t seq = 0; + int ret; + + if (!dev_priv) + return -EINVAL; + + if (fence_class >= PSB_NUM_ENGINES) + return -EINVAL; + + switch (fence_class) { + case PSB_ENGINE_2D: + spin_lock(&dev_priv->sequence_lock); + seq = ++dev_priv->sequence[fence_class]; + spin_unlock(&dev_priv->sequence_lock); + ret = psb_blit_sequence(dev_priv, seq); + if (ret) + return ret; + break; + case PSB_ENGINE_VIDEO: + spin_lock(&dev_priv->sequence_lock); + seq = dev_priv->sequence[fence_class]++; + spin_unlock(&dev_priv->sequence_lock); + break; + case LNC_ENGINE_ENCODE: + spin_lock(&dev_priv->sequence_lock); + seq = dev_priv->sequence[fence_class]++; + spin_unlock(&dev_priv->sequence_lock); + break; + default: + spin_lock(&dev_priv->sequence_lock); + seq = dev_priv->sequence[fence_class]; + spin_unlock(&dev_priv->sequence_lock); + } + + *sequence = seq; + + if (fence_class == PSB_ENGINE_TA) + *timeout_jiffies = jiffies + DRM_HZ / 2; + else + *timeout_jiffies = jiffies + DRM_HZ * 3; + + return 0; +} + +uint32_t psb_fence_advance_sequence(struct drm_device *dev, + uint32_t fence_class) +{ + struct drm_psb_private *dev_priv = + (struct drm_psb_private *) dev->dev_private; + uint32_t sequence; + + spin_lock(&dev_priv->sequence_lock); + sequence = ++dev_priv->sequence[fence_class]; + spin_unlock(&dev_priv->sequence_lock); + + return sequence; +} + +static void psb_fence_lockup(struct ttm_fence_object *fence, + uint32_t fence_types) +{ + struct ttm_fence_class_manager *fc = ttm_fence_fc(fence); + + if (fence->fence_class == PSB_ENGINE_TA) { + + /* + * The 3D engine has its own lockup detection. + * Just extend the fence expiry time. + */ + + DRM_INFO("Extending 3D fence timeout.\n"); + write_lock(&fc->lock); + + DRM_INFO("Sequence %lu, types 0x%08x signaled 0x%08x\n", + (unsigned long) fence->sequence, fence_types, + fence->info.signaled_types); + + if (time_after_eq(jiffies, fence->timeout_jiffies)) + fence->timeout_jiffies = jiffies + DRM_HZ / 2; + + psb_print_ta_fence_status(fence->fdev); + write_unlock(&fc->lock); + } else { + DRM_ERROR + ("GPU timeout (probable lockup) detected on engine %u " + "fence type 0x%08x\n", + (unsigned int) fence->fence_class, + (unsigned int) fence_types); + write_lock(&fc->lock); + ttm_fence_handler(fence->fdev, fence->fence_class, + fence->sequence, fence_types, -EBUSY); + write_unlock(&fc->lock); + } +} + +void psb_fence_handler(struct drm_device *dev, uint32_t fence_class) +{ + struct drm_psb_private *dev_priv = psb_priv(dev); + struct ttm_fence_device *fdev = &dev_priv->fdev; + struct ttm_fence_class_manager *fc = + &fdev->fence_class[fence_class]; + unsigned long irq_flags; + +#ifdef FIX_TG_16 + if (fence_class == PSB_ENGINE_2D) { + + if ((atomic_read(&dev_priv->ta_wait_2d_irq) == 1) && + (PSB_RSGX32(PSB_CR_2D_SOCIF) == _PSB_C2_SOCIF_EMPTY) && + ((PSB_RSGX32(PSB_CR_2D_BLIT_STATUS) & + _PSB_C2B_STATUS_BUSY) == 0)) + psb_resume_ta_2d_idle(dev_priv); + } +#endif + write_lock_irqsave(&fc->lock, irq_flags); + psb_fence_poll(fdev, fence_class, fc->waiting_types); + write_unlock_irqrestore(&fc->lock, irq_flags); +} + + +static struct ttm_fence_driver psb_ttm_fence_driver = { + .has_irq = NULL, + .emit = psb_fence_emit_sequence, + .flush = NULL, + .poll = psb_fence_poll, + .needed_flush = NULL, + .wait = NULL, + .signaled = NULL, + .lockup = psb_fence_lockup, +}; + +int psb_ttm_fence_device_init(struct ttm_fence_device *fdev) +{ + struct drm_psb_private *dev_priv = + container_of(fdev, struct drm_psb_private, fdev); + struct ttm_fence_class_init fci = {.wrap_diff = (1 << 30), + .flush_diff = (1 << 29), + .sequence_mask = 0xFFFFFFFF + }; + + return ttm_fence_device_init(PSB_NUM_ENGINES, + dev_priv->mem_global_ref.object, + fdev, &fci, 1, + &psb_ttm_fence_driver); +} --- /dev/null +++ b/drivers/staging/psb/psb_gtt.c @@ -0,0 +1,257 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + * develop this driver. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include "psb_drv.h" + +static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type) +{ + uint32_t mask = PSB_PTE_VALID; + + if (type & PSB_MMU_CACHED_MEMORY) + mask |= PSB_PTE_CACHED; + if (type & PSB_MMU_RO_MEMORY) + mask |= PSB_PTE_RO; + if (type & PSB_MMU_WO_MEMORY) + mask |= PSB_PTE_WO; + + return (pfn << PAGE_SHIFT) | mask; +} + +struct psb_gtt *psb_gtt_alloc(struct drm_device *dev) +{ + struct psb_gtt *tmp = drm_calloc(1, sizeof(*tmp), DRM_MEM_DRIVER); + + if (!tmp) + return NULL; + + init_rwsem(&tmp->sem); + tmp->dev = dev; + + return tmp; +} + +void psb_gtt_takedown(struct psb_gtt *pg, int free) +{ + struct drm_psb_private *dev_priv = pg->dev->dev_private; + + if (!pg) + return; + + if (pg->gtt_map) { + iounmap(pg->gtt_map); + pg->gtt_map = NULL; + } + if (pg->initialized) { + pci_write_config_word(pg->dev->pdev, PSB_GMCH_CTRL, + pg->gmch_ctrl); + PSB_WVDC32(pg->pge_ctl, PSB_PGETBL_CTL); + (void) PSB_RVDC32(PSB_PGETBL_CTL); + } + if (free) + drm_free(pg, sizeof(*pg), DRM_MEM_DRIVER); +} + +int psb_gtt_init(struct psb_gtt *pg, int resume) +{ + struct drm_device *dev = pg->dev; + struct drm_psb_private *dev_priv = dev->dev_private; + unsigned gtt_pages; + unsigned long stolen_size, vram_stolen_size, ci_stolen_size; + unsigned i, num_pages; + unsigned pfn_base; + + int ret = 0; + uint32_t pte; + + pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &pg->gmch_ctrl); + pci_write_config_word(dev->pdev, PSB_GMCH_CTRL, + pg->gmch_ctrl | _PSB_GMCH_ENABLED); + + pg->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL); + PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL); + (void) PSB_RVDC32(PSB_PGETBL_CTL); + + pg->initialized = 1; + + pg->gtt_phys_start = pg->pge_ctl & PAGE_MASK; + + pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE); + pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE); + gtt_pages = + pci_resource_len(dev->pdev, PSB_GTT_RESOURCE) >> PAGE_SHIFT; + pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE) + >> PAGE_SHIFT; + + pci_read_config_dword(dev->pdev, PSB_BSM, &pg->stolen_base); + vram_stolen_size = pg->gtt_phys_start - pg->stolen_base - PAGE_SIZE; + + ci_stolen_size = dev_priv->ci_region_size; + /* add CI & RAR share buffer space to stolen_size */ + /* stolen_size = vram_stolen_size + ci_stolen_size; */ + stolen_size = vram_stolen_size; + + PSB_DEBUG_INIT("GTT phys start: 0x%08x.\n", pg->gtt_phys_start); + PSB_DEBUG_INIT("GTT start: 0x%08x.\n", pg->gtt_start); + PSB_DEBUG_INIT("GATT start: 0x%08x.\n", pg->gatt_start); + PSB_DEBUG_INIT("GTT pages: %u\n", gtt_pages); + PSB_DEBUG_INIT("Stolen size: %lu kiB\n", stolen_size / 1024); + + if (resume && (gtt_pages != pg->gtt_pages) && + (stolen_size != pg->stolen_size)) { + DRM_ERROR("GTT resume error.\n"); + ret = -EINVAL; + goto out_err; + } + + pg->gtt_pages = gtt_pages; + pg->stolen_size = stolen_size; + pg->vram_stolen_size = vram_stolen_size; + pg->ci_stolen_size = ci_stolen_size; + pg->gtt_map = + ioremap_nocache(pg->gtt_phys_start, gtt_pages << PAGE_SHIFT); + if (!pg->gtt_map) { + DRM_ERROR("Failure to map gtt.\n"); + ret = -ENOMEM; + goto out_err; + } + + /* + * insert vram stolen pages. + */ + + pfn_base = pg->stolen_base >> PAGE_SHIFT; + num_pages = vram_stolen_size >> PAGE_SHIFT; + PSB_DEBUG_INIT("Set up %d stolen pages starting at 0x%08x\n", + num_pages, pfn_base); + for (i = 0; i < num_pages; ++i) { + pte = psb_gtt_mask_pte(pfn_base + i, 0); + iowrite32(pte, pg->gtt_map + i); + } +#if 0 + /* + * insert CI stolen pages + */ + + pfn_base = dev_priv->ci_region_start >> PAGE_SHIFT; + num_pages = ci_stolen_size >> PAGE_SHIFT; + PSB_DEBUG_INIT("Set up %d stolen pages starting at 0x%08x\n", + num_pages, pfn_base); + for (; i < num_pages; ++i) { + pte = psb_gtt_mask_pte(pfn_base + i, 0); + iowrite32(pte, pg->gtt_map + i); + } +#endif + /* + * Init rest of gtt. + */ + + pfn_base = page_to_pfn(dev_priv->scratch_page); + pte = psb_gtt_mask_pte(pfn_base, 0); + PSB_DEBUG_INIT("Initializing the rest of a total " + "of %d gtt pages.\n", pg->gatt_pages); + + for (; i < pg->gatt_pages; ++i) + iowrite32(pte, pg->gtt_map + i); + (void) ioread32(pg->gtt_map + i - 1); + + return 0; + +out_err: + psb_gtt_takedown(pg, 0); + return ret; +} + +int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages, + unsigned offset_pages, unsigned num_pages, + unsigned desired_tile_stride, + unsigned hw_tile_stride, int type) +{ + unsigned rows = 1; + unsigned add; + unsigned row_add; + unsigned i; + unsigned j; + uint32_t *cur_page = NULL; + uint32_t pte; + + if (hw_tile_stride) + rows = num_pages / desired_tile_stride; + else + desired_tile_stride = num_pages; + + add = desired_tile_stride; + row_add = hw_tile_stride; + + down_read(&pg->sem); + for (i = 0; i < rows; ++i) { + cur_page = pg->gtt_map + offset_pages; + for (j = 0; j < desired_tile_stride; ++j) { + pte = + psb_gtt_mask_pte(page_to_pfn(*pages++), type); + iowrite32(pte, cur_page++); + } + offset_pages += add; + } + (void) ioread32(cur_page - 1); + up_read(&pg->sem); + + return 0; +} + +int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages, + unsigned num_pages, unsigned desired_tile_stride, + unsigned hw_tile_stride) +{ + struct drm_psb_private *dev_priv = pg->dev->dev_private; + unsigned rows = 1; + unsigned add; + unsigned row_add; + unsigned i; + unsigned j; + uint32_t *cur_page = NULL; + unsigned pfn_base = page_to_pfn(dev_priv->scratch_page); + uint32_t pte = psb_gtt_mask_pte(pfn_base, 0); + + if (hw_tile_stride) + rows = num_pages / desired_tile_stride; + else + desired_tile_stride = num_pages; + + add = desired_tile_stride; + row_add = hw_tile_stride; + + down_read(&pg->sem); + for (i = 0; i < rows; ++i) { + cur_page = pg->gtt_map + offset_pages; + for (j = 0; j < desired_tile_stride; ++j) + iowrite32(pte, cur_page++); + + offset_pages += add; + } + (void) ioread32(cur_page - 1); + up_read(&pg->sem); + + return 0; +} --- /dev/null +++ b/drivers/staging/psb/psb_irq.c @@ -0,0 +1,420 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. + * All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * + * Intel funde