From: Jim Gifford , Grant Grundler , Peter Horton With Grant's help I was able to get the tulip driver to work with 64 bit MIPS. Signed-off-by: Andrew Morton --- drivers/net/tulip/eeprom.c | 16 ++++++++++++++++ drivers/net/tulip/media.c | 22 ++++++++++++++++++++-- drivers/net/tulip/tulip.h | 7 +++++-- drivers/net/tulip/tulip_core.c | 2 +- net/tulip/interrupt.c | 0 5 files changed, 42 insertions(+), 5 deletions(-) diff -puN drivers/net/tulip/eeprom.c~tulip-fix-for-64-bit-mips drivers/net/tulip/eeprom.c --- 25/drivers/net/tulip/eeprom.c~tulip-fix-for-64-bit-mips 2005-05-31 02:43:27.000000000 -0700 +++ 25-akpm/drivers/net/tulip/eeprom.c 2005-05-31 02:43:27.000000000 -0700 @@ -63,6 +63,22 @@ static struct eeprom_fixup eeprom_fixups */ { 0x1e00, 0x0000, 0x000b, 0x8f01, 0x0103, 0x0300, 0x0821, 0x000, 0x0001, 0x0000, 0x01e1 } }, + {"Cobalt Microserver", 0, 0x10, 0xE0, {0x1e00, /* 0 == controller #, 1e == offset */ + 0x0000, /* 0 == high offset, 0 == gap */ + 0x0800, /* Default Autoselect */ + 0x8001, /* 1 leaf, extended type, bogus len */ + 0x0003, /* Type 3 (MII), PHY #0 */ + 0x0400, /* 0 init instr, 4 reset instr */ + 0x0801, /* Set control mode, GP0 output */ + 0x0000, /* Drive GP0 Low (RST is active low) */ + 0x0800, /* control mode, GP0 input (undriven) */ + 0x0000, /* clear control mode */ + 0x7800, /* 100TX FDX + HDX, 10bT FDX + HDX */ + 0x01e0, /* Advertise all above */ + 0x5000, /* FDX all above */ + 0x1800, /* Set fast TTM in 100bt modes */ + 0x0000, /* PHY cannot be unplugged */ + }}, {NULL}}; diff -puN drivers/net/tulip/interrupt.c~tulip-fix-for-64-bit-mips drivers/net/tulip/interrupt.c diff -puN drivers/net/tulip/media.c~tulip-fix-for-64-bit-mips drivers/net/tulip/media.c --- 25/drivers/net/tulip/media.c~tulip-fix-for-64-bit-mips 2005-05-31 02:43:27.000000000 -0700 +++ 25-akpm/drivers/net/tulip/media.c 2005-05-31 02:43:27.000000000 -0700 @@ -44,8 +44,10 @@ static const unsigned char comet_miireg2 /* MII transceiver control section. Read and write the MII registers using software-generated serial - MDIO protocol. See the MII specifications or DP83840A data sheet - for details. */ + MDIO protocol. + See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions") + or DP83840A data sheet for more details. + */ int tulip_mdio_read(struct net_device *dev, int phy_id, int location) { @@ -308,13 +310,29 @@ void tulip_select_media(struct net_devic int reset_length = p[2 + init_length]; misc_info = (u16*)(reset_sequence + reset_length); if (startup) { + int timeout = 10; /* max 1 ms */ iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12); for (i = 0; i < reset_length; i++) iowrite32(reset_sequence[i], ioaddr + CSR12); + + /* flush posted writes */ + ioread32(ioaddr + CSR12); + + /* Sect 3.10.3 in DP83840A.pdf (p39) */ + udelay(500); + + /* Section 4.2 in DP83840A.pdf (p43) */ + /* and IEEE 802.3 "22.2.4.1.1 Reset" */ + while (timeout-- && + (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET)) + udelay(100); } for (i = 0; i < init_length; i++) iowrite32(init_sequence[i], ioaddr + CSR12); + + ioread32(ioaddr + CSR12); /* flush posted writes */ } + tmp_info = get_u16(&misc_info[1]); if (tmp_info) tp->advertising[phy_num] = tmp_info | 1; diff -puN drivers/net/tulip/tulip_core.c~tulip-fix-for-64-bit-mips drivers/net/tulip/tulip_core.c --- 25/drivers/net/tulip/tulip_core.c~tulip-fix-for-64-bit-mips 2005-05-31 02:43:27.000000000 -0700 +++ 25-akpm/drivers/net/tulip/tulip_core.c 2005-05-31 02:43:27.000000000 -0700 @@ -22,7 +22,7 @@ #else #define DRV_VERSION "1.1.13" #endif -#define DRV_RELDATE "May 11, 2002" +#define DRV_RELDATE "December 15, 2004" #include diff -puN drivers/net/tulip/tulip.h~tulip-fix-for-64-bit-mips drivers/net/tulip/tulip.h --- 25/drivers/net/tulip/tulip.h~tulip-fix-for-64-bit-mips 2005-05-31 02:43:27.000000000 -0700 +++ 25-akpm/drivers/net/tulip/tulip.h 2005-05-31 02:43:27.000000000 -0700 @@ -475,8 +475,11 @@ static inline void tulip_stop_rxtx(struc udelay(10); if (!i) - printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed\n", - pci_name(tp->pdev)); + printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed" + " (CSR5 0x%x CSR6 0x%x)\n", + pci_name(tp->pdev), + ioread32(ioaddr + CSR5), + ioread32(ioaddr + CSR6)); } } _