The Common Flash Interface specification was developed by Intel,
AMD and other flash manufactures that provides a universal method
for probing the capabilities of flash devices. If you wish to
support any device that is CFI-compliant, you need to enable this
option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
for more information on CFI.

This option enables JEDEC-style probing of flash chips which are not
compatible with the Common Flash Interface, but will use the common
CFI-targeted flash drivers for any chips which are identified which
are in fact compatible in all but the probe method. This actually
covers most AMD/Fujitsu-compatible chips and also non-CFI
Intel chips.

If you need to specify a specific endianness for access to flash
chips, or if you wish to reduce the size of the kernel by including
support for only specific arrangements of flash chips, say 'Y'. This
option does not directly affect the code, but will enable other
configuration options which allow you to do so.

If unsure, say 'N'.

This option defines the way in which the CPU attempts to arrange
data bits when writing the 'magic' commands to the chips. Saying
'NO', which is the default when CONFIG_MTD_CFI_ADV_OPTIONS isn't
enabled, means that the CPU will not do any swapping; the chips
are expected to be wired to the CPU in 'host-endian' form.
Specific arrangements are possible with the BIG_ENDIAN_BYTE and
LITTLE_ENDIAN_BYTE, if the bytes are reversed.

If you have a LART, on which the data (and address) lines were
connected in a fashion which ensured that the nets were as short
as possible, resulting in a bit-shuffling which seems utterly
random to the untrained eye, you need the LART_ENDIAN_BYTE option.

Yes, there really exists something sicker than PDP-endian :)

This option does not affect the code directly, but will enable
some other configuration options which would allow you to reduce
the size of the kernel by including support for only certain
arrangements of CFI chips. If unsure, say 'N' and all options
which are supported by the current code will be enabled.

If you wish to support CFI devices on a physical bus which is
8 bits wide, say 'Y'.

If you wish to support CFI devices on a physical bus which is
16 bits wide, say 'Y'.

If you wish to support CFI devices on a physical bus which is
32 bits wide, say 'Y'.

If you wish to support CFI devices on a physical bus which is
64 bits wide, say 'Y'.

If you wish to support CFI devices on a physical bus which is
128 bits wide, say 'Y'.

If you wish to support CFI devices on a physical bus which is
256 bits wide, say 'Y'.

If your flash chips are not interleaved - i.e. you only have one
flash chip addressed by each bus cycle, then say 'Y'.

If your flash chips are interleaved in pairs - i.e. you have two
flash chips addressed by each bus cycle, then say 'Y'.

If your flash chips are interleaved in fours - i.e. you have four
flash chips addressed by each bus cycle, then say 'Y'.

If your flash chips are interleaved in eights - i.e. you have eight
flash chips addressed by each bus cycle, then say 'Y'.

This enables support for reading, writing and locking so called
"Protection Registers" present on some flash chips.
A subset of them are pre-programmed at the factory with a
unique set of values. The rest is user-programmable.

The user-programmable Protection Registers contain one-time
programmable (OTP) bits; when programmed, register bits cannot be
erased. Each Protection Register can be accessed multiple times to
program individual bits, as long as the register remains unlocked.

Each Protection Register has an associated Lock Register bit. When a
Lock Register bit is programmed, the associated Protection Register
can only be read; it can no longer be programmed. Additionally,
because the Lock Register bits themselves are OTP, when programmed,
Lock Register bits cannot be erased. Therefore, when a Protection
Register is locked, it cannot be unlocked.

This feature should therefore be used with extreme care. Any mistake
in the programming of OTP bits will waste them.

The Common Flash Interface defines a number of different command
sets which a CFI-compliant chip may claim to implement. This code
provides support for one of those command sets, used on Intel
StrataFlash and other parts.

The Common Flash Interface defines a number of different command
sets which a CFI-compliant chip may claim to implement. This code
provides support for one of those command sets, used on chips
including the AMD Am29LV320.

The Common Flash Interface defines a number of different command
sets which a CFI-compliant chip may claim to implement. This code
provides support for one of those command sets.

This option enables basic support for RAM chips accessed through
a bus mapping driver.

This option enables basic support for ROM chips accessed through
a bus mapping driver.

This option enables support for a dummy probing driver used to
allocated placeholder MTD devices on systems that have socketed
or removable media.  Use of this driver as a fallback chip probe
preserves the expected registration order of MTD device nodes on
the system regardless of media presence.  Device nodes created
with this driver will return -ENODEV upon access.

This allows MTD support to work with flash memory which is also
used for XIP purposes.  If you're not sure what this is all about
then say N.