The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and handhelds such as the Compaq IPAQ. ARM-based PCs are no longer manufactured, but legacy ARM-based PC hardware remains popular in Europe. There is an ARM Linux project with a web page at <http://www.arm.linux.org.uk/>.
The Extended Industry Standard Architecture (EISA) bus was developed as an open alternative to the IBM MicroChannel bus. The EISA bus provided some of the features of the IBM MicroChannel bus while maintaining backward compatibility with cards made for the older ISA bus. The EISA bus saw limited use between 1988 and 1995 when it was made obsolete by the PCI bus. Say Y here if you are building a kernel for an EISA-based machine. Otherwise, say N.
MicroChannel Architecture is found in some IBM PS/2 machines and laptops. It is a bus system similar to PCI or ISA. See <file:Documentation/mca.txt> (and especially the web page given there) before attempting to build an MCA bus kernel.
Internal node to signify that the ARCH has CPUFREQ support and that the relevant menu configurations are displayed for it.
The base address of exception vectors.
Patch phys-to-virt and virt-to-phys translation functions at boot and module load time according to the position of the kernel in system memory. This can only be used with non-XIP MMU kernels where the base of physical memory is at a 16MB boundary, or theoretically 64K for the MSM machine class.
This option extends the physical to virtual translation patching to allow physical memory down to a theoretical minimum of 64K boundaries.
Select if you want MMU-based virtualised addressing space support by paged memory management. If unsure, say 'Y'.
Support for ARM's Integrator platform.
This enables support for ARM Ltd RealView boards.
This enables support for ARM Ltd Versatile board.
This enables support for the ARM Ltd Versatile Express boards.
This enables support for systems based on the Atmel AT91RM9200, AT91SAM9 and AT91CAP9 processors.
Support for Broadcom's BCMRing platform.
Support for Cirrus Logic 711x/721x based boards.
Support for Cavium Networks CNS3XXX platform.
Support for the Cortina Systems Gemini family SoCs
This is an evaluation board for the StrongARM processor available from Digital. It has limited hardware on-board, including an Ethernet interface, two PCMCIA sockets, two serial ports and a parallel port.
This enables support for the Cirrus EP93xx series of CPUs.
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
Support for Freescale MXC/iMX-based family of processors
Support for Freescale MXS-based family of processors
This enables support for systems based on the Hilscher NetX Soc
This enables support for systems based on the Hynix HMS720x
Support for Intel's IOP13XX (XScale) family of processors.
Support for Intel's 80219 and IOP32X (XScale) family of processors.
Support for Intel's IOP33X (XScale) family of processors.
Support for Intel's IXP23xx (XScale) family of processors.
Support for Intel's IXP2400/2800 (XScale) family of processors.
Support for Intel's IXP4XX (XScale) family of processors.
Support for the Marvell Dove SoC 88AP510
Support for the following Marvell Kirkwood series SoCs: 88F6180, 88F6192 and 88F6281.
Support for the Marvell Loki (88RC8480) SoC.
Support for the NXP LPC32XX family of processors
Support for the following Marvell MV78xx0 series SoCs: MV781x0, MV782x0.
Support for the following Marvell Orion 5x series SoCs: Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), Orion-2 (5281), Orion-1-90 (6183).
Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices.
Support for Nuvoton (Winbond logic dept.) ARM9 processor, At present, the w90x900 has been renamed nuc900, regarding the ARM series product line, you can login the following link address to know more. <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a low-power and high performance MPEG-4/JPEG multimedia controller chip.
This enables support for NVIDIA Tegra based systems (Tegra APX, Tegra 6xx and Tegra 2 series).
This enables support for Philips PNX4008 mobile platform.
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
Support for Qualcomm MSM/QSD based systems. This runs on the apps processor of the MSM/QSD and depends on a shared memory interface to the modem processor which runs the baseband stack and controls some vital subsystems (clock and power control, etc).
Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
On the Acorn Risc-PC, Linux can support the internal IDE disk and CD-ROM interface, serial and parallel port, and the floppy drive.
Support for StrongARM 11x0 based boards.
Samsung S3C2410X CPU based systems, such as the Simtec Electronics BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the Samsung SMDK2410 development board (and derivatives). Note, the S3C2416 and the S3C2450 are so close that they even share the same SoC ID code. This means that there is no separate machine directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
Samsung S3C64XX series based systems
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, SMDK6450.
Samsung S5PC100 series based systems
Samsung S5PV210/S5PC110 series based systems
Samsung EXYNOS4 series based systems
Support for the StrongARM based Digital DNARD machine, also known as "Shark" (<http://www.shark-linux.de/shark.html>).
Support for Telechips TCC ARM926-based systems.
Support for ST-Ericsson U300 series mobile platforms.
Support for ST-Ericsson's Ux500 architecture
Support for the Nomadik platform by ST-Ericsson
Support for TI's DaVinci platform.
Support for TI's OMAP platform (OMAP1/2/3/4).
Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
Enable support for iWMMXt context switching at run time if running on a CPU that supports it.
Allow each machine to specify it's own IRQ handler at run time.
Invalidation of the Instruction Cache operation can fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. It does not affect the MPCore. This option enables the ARM Ltd. recommended workaround.
This option enables the workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb interworking branch is replaced with another code sequence at the same virtual address, whether due to self-modifying code or virtual to physical address re-mapping, Cortex-A8 does not recover from the stale interworking branch prediction. This results in Cortex-A8 executing the new code sequence in the incorrect ARM or Thumb state. The workaround enables the BTB/BTAC operations by setting ACTLR.IBE and also flushes the branch target cache at every context switch. Note that setting specific bits in the ACTLR register may not be available in non-secure mode.
This option enables the workaround for the 458693 Cortex-A8 (r2p0) erratum. For very specific sequences of memory operations, it is possible for a hazard condition intended for a cache line to instead be incorrectly associated with a different cache line. This false hazard might then cause a processor deadlock. The workaround enables the L1 caching of the NEON accesses and disables the PLD instruction in the ACTLR register. Note that setting specific bits in the ACTLR register may not be available in non-secure mode.
This option enables the workaround for the 460075 Cortex-A8 (r2p0) erratum. Any asynchronous access to the L2 cache may encounter a situation in which recent store transactions to the L2 cache are lost and overwritten with stale memory contents from external memory. The workaround disables the write-allocate mode for the L2 cache via the ACTLR register. Note that setting specific bits in the ACTLR register may not be available in non-secure mode.
This option enables the workaround for the 742230 Cortex-A9 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction between two write operations may not ensure the correct visibility ordering of the two writes. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which causes the DMB instruction to behave as a DSB, ensuring the correct behaviour of the two writes.
This option enables the workaround for the 742231 Cortex-A9 (r2p0..r2p2) erratum. Under certain conditions, specific to the Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, accessing some data located in the same cache line, may get corrupted data due to bad handling of the address hazard when the line gets replaced from one of the CPUs at the same time as another CPU is accessing it. This workaround sets specific bits in the diagnostic register of the Cortex-A9 which reduces the linefill issuing capabilities of the processor.
The PL310 L2 cache controller implements three types of Clean & Invalidate maintenance operations: by Physical Address (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC). They are architecturally defined to behave as the execution of a clean operation followed immediately by an invalidate operation, both performing to the same memory location. This functionality is not correctly implemented in PL310 as clean lines are not invalidated as a result of these operations.
This option enables the workaround for the 720789 Cortex-A9 (prior to r2p0) erratum. A faulty ASID can be sent to the other CPUs for the broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. As a consequence of this erratum, some TLB entries which should be invalidated are not, resulting in an incoherency in the system page tables. The workaround changes the TLB flushing routines to invalidate entries regardless of the ASID.
PL310 implements the Clean & Invalidate by Way L2 cache maintenance operation (offset 0x7FC). This operation runs in background so that PL310 can handle normal accesses while it is in progress. Under very rare circumstances, due to this erratum, write data can be lost when PL310 treats a cacheable write transaction during a Clean & Invalidate by Way operation.
This option enables the workaround for the 743622 Cortex-A9 (r2p0..r2p2) erratum. Under very rare conditions, a faulty optimisation in the Cortex-A9 Store Buffer may lead to data corruption. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which disables the Store Buffer optimisation, preventing the defect from occurring. This has no visible impact on the overall performance or power consumption of the processor.
This option enables the workaround for the 751472 Cortex-A9 (prior to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the completion of a following broadcasted operation if the second operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB.
This option enables the workaround for the 753970 PL310 (r3p0) erratum. Under some condition the effect of cache sync operation on the store buffer still remains when the operation completes. This means that the store buffer is always asked to drain and this prevents it from merging any further writes. The workaround is to replace the normal offset of cache sync operation (0x730) by another offset targeting an unmapped PL310 register 0x740. This has the same effect as the cache sync operation: store buffer drain and waiting for all buffers empty.
This option enables the workaround for the 754322 Cortex-A9 (r2p*, r3p*) erratum. A speculative memory access may cause a page table walk which starts prior to an ASID switch but completes afterwards. This can populate the micro-TLB with a stale entry which may be hit with the new ASID. This workaround places two dsb instructions in the mm switching code so that no page table walks can cross the ASID switch.
This option enables the workaround for the 754327 Cortex-A9 (prior to r2p0) erratum. The Store Buffer does not have any automatic draining mechanism and therefore a livelock may occur if an external agent continuously polls a memory location waiting to observe an update. This workaround defines cpu_relax() as smp_mb(), preventing correctly written polling loops from denying visibility of updates to memory.
Find out whether you have ISA slots on your motherboard. ISA is the name of a bus system, i.e. the way the CPU talks to the other stuff inside your box. Other bus systems are PCI, EISA, MicroChannel (MCA) or VESA. ISA is an older system, now being displaced by PCI; newer boards don't support it. If you have ISA, say Y, otherwise N.
Find out whether you have a PCI motherboard. PCI is the name of a bus system, i.e. the way the CPU talks to the other stuff inside your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or VESA. If you have PCI, say Y, otherwise N.
Enable PCI on the BSE nanoEngine board.
This enables support for systems with more than one CPU. If you have a system with only one CPU, like most personal computers, say N. If you have a system with more than one CPU, say Y. If you say N here, the kernel will run on single and multiprocessor machines, but will use only one CPU of a multiprocessor machine. If you say Y here, the kernel will run on many, but not all, single processor machines. On a single processor machine, the kernel will run faster if you say N here. See also <file:Documentation/i386/IO-APIC.txt>, <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at <http://tldp.org/HOWTO/SMP-HOWTO.html>. If you don't know what to do here, say N.
SMP kernels contain instructions which fail on non-SMP processors. Enabling this option allows the kernel to modify itself to make these instructions safe. Disabling it allows about 1K of space savings. If you don't know what to do here, say Y.
This option enables support for the ARM system coherency unit
This options enables support for the ARM timer and watchdog unit
Select the desired split between kernel and user memory. If you are not absolutely sure what you are doing, leave this option alone! config VMSPLIT_3G bool "3G/1G user/kernel split" config VMSPLIT_2G bool "2G/2G user/kernel split" config VMSPLIT_1G bool "1G/3G user/kernel split"
Say Y here to experiment with turning CPUs off and on. CPUs can be controlled through /sys/devices/system/cpu.
Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system accounting to be spread across the timer interval, preventing a "thundering herd" at every timer tick.
By enabling this option, the kernel will be compiled in Thumb-2 mode. A compiler/assembler that understand the unified ARM-Thumb syntax is needed. If unsure, say N.
Various binutils versions can resolve Thumb-2 branches to locally-defined, preemptible global symbols as short-range "b.n" branch instructions. This is a problem, because there's no guarantee the final destination of the symbol, or any candidate locations for a trampoline, are within range of the branch. For this reason, the kernel does not support fixing up the R_ARM_THM_JUMP11 (102) relocation in modules at all, and it makes little sense to add support. The symptom is that the kernel fails with an "unsupported relocation" error when loading some modules. Until fixed tools are available, passing -fno-optimize-sibling-calls to gcc should prevent gcc generating code which hits this problem, at the cost of a bit of extra runtime stack usage in some cases. The problem is described in more detail at: https://bugs.launchpad.net/binutils-linaro/+bug/725126 Only Thumb-2 kernels are affected. Unless you are sure your tools don't have this problem, say Y.
This option allows for the kernel to be compiled using the latest ARM ABI (aka EABI). This is only useful if you are using a user space environment that is also compiled with EABI. Since there are major incompatibilities between the legacy ABI and EABI, especially with regard to structure member alignment, this option also changes the kernel syscall calling convention to disambiguate both ABIs and allow for backward compatibility support (selected with CONFIG_OABI_COMPAT). To use this you need GCC version 4.0.0 or later.
This option preserves the old syscall interface along with the new (ARM EABI) one. It also provides a compatibility layer to intercept syscalls that have structure arguments which layout in memory differs between the legacy ABI and the new ARM EABI (only for non "thumb" binaries). This option adds a tiny overhead to all syscalls and produces a slightly larger kernel. If you know you'll be using only pure EABI user space then you can say N here. If this option is not selected and you attempt to execute a legacy ABI binary then the result will be UNPREDICTABLE (in fact it can be predicted that it won't work at all). If in doubt say Y.
The address space of ARM processors is only 4 Gigabytes large and it has to accommodate user address space, kernel address space as well as some memory mapped IO. That means that, if you have a large amount of physical memory and/or IO, not all of the memory can be "permanently mapped" by the kernel. The physical memory that is not permanently mapped is called "high memory". Depending on the selected kernel/user memory split, minimum vmalloc space and actual amount of RAM, you may not need this option which should result in a slightly faster kernel. If unsure, say n.
Enable hardware performance counter support for perf events. If disabled, perf events will use software events only.
The kernel memory allocator divides physically contiguous memory blocks into "zones", where each zone is a power of two number of pages. This option selects the largest power of two that the kernel keeps in the memory allocator. If you need to allocate very large blocks of physically contiguous memory, then you may need to increase this value. This config option is actually maximum order plus one. For example, a value of 11 means that the largest free memory block is 2^10 pages.
If you say Y here, the LEDs on your machine will be used to provide useful information about your current system status. If you are compiling a kernel for a NetWinder or EBSA-285, you will be able to select which LEDs are active using the options below. If you are compiling a kernel for the EBSA-110 or the LART however, the red LED will simply flash regularly to indicate that the system is still functional. It is safe to say Y here if you have a CATS system, but the driver will do nothing.
If you say Y here, one of the system LEDs (the green one on the NetWinder, the amber one on the EBSA285, or the red one on the LART) will flash regularly to indicate that the system is still operational. This is mainly useful to kernel hackers who are debugging unstable kernels. The LART uses the same LED for both Timer LED and CPU usage LED functions. You may choose to use both, but the Timer LED function will overrule the CPU usage LED.
If you say Y here, the red LED will be used to give a good real time indication of CPU usage, by lighting whenever the idle task is not currently executing. The LART uses the same LED for both Timer LED and CPU usage LED functions. You may choose to use both, but the Timer LED function will overrule the CPU usage LED.
ARM processors cannot fetch/store information which is not naturally aligned on the bus, i.e., a 4 byte fetch must start at an address divisible by 4. On 32-bit ARM processors, these non-aligned fetch/store instructions will be emulated in software if you say here, which has a severe performance impact. This is necessary for correct operation of some network protocols. With an IP-only configuration it is safe to say N, otherwise say Y.
Implement faster copy_to_user and clear_user methods for CPU cores where a 8-word STM instruction give significantly higher memory write throughput than a sequence of individual 32bit stores. A possible side effect is a slight increase in scheduling latency between threads sharing the same address space if they invoke such copy operations with large buffers. However, if the CPU data cache is using a write-allocate mode, this option is unlikely to provide any performance gain.
This kernel feature is useful for number crunching applications that may need to compute untrusted bytecode during their execution. By using pipes or other transports made available to the process as file descriptors supporting the read/write syscalls, it's possible to isolate those applications in their own address space using seccomp. Once seccomp is enabled via prctl(PR_SET_SECCOMP), it cannot be disabled and the task is only allowed to execute a few safe syscalls defined by each seccomp mode.
This option turns on the -fstack-protector GCC feature. This feature puts, at the beginning of functions, a canary value on the stack just before the return address, and validates the value just before actually returning. Stack based buffer overflows (that need to overwrite this return address) now also overwrite the canary, which gets detected and the attack is then neutralized via a kernel panic. This feature requires gcc version 4.2 or above.
This was deprecated in 2001 and announced to live on for 5 years. Some old boot loaders still use this way.
Include support for flattened device tree machine descriptions.
The physical address at which the ROM-able zImage is to be placed in the target. Platforms which normally make use of ROM-able zImage formats normally set this to a suitable value in their defconfig file. If ZBOOT_ROM is not enabled, this has no effect.
The base address of an area of read/write memory in the target for the ROM-able zImage which must be available while the decompressor is running. It must be large enough to hold the entire decompressed kernel plus an additional 128 KiB. Platforms which normally make use of ROM-able zImage formats normally set this to a suitable value in their defconfig file. If ZBOOT_ROM is not enabled, this has no effect.
Say Y here if you intend to execute your compressed kernel image (zImage) directly from ROM or flash. If unsure, say N.
Say Y here to include experimental MMCIF loading code in the ROM-able zImage. With this enabled it is possible to write the the ROM-able zImage kernel image to an MMC card and boot the kernel straight from the reset vector. At reset the processor Mask ROM will load the first part of the the ROM-able zImage which in turn loads the rest the kernel image to RAM using the MMCIF hardware block.
On some architectures (EBSA110 and CATS), there is currently no way for the boot loader to pass arguments to the kernel. For these architectures, you should supply some command-line options at build time by entering them here. As a minimum, you should specify the memory size and the root device (e.g., mem=64M root=/dev/nfs).
Uses the command-line options passed by the boot loader. If the boot loader doesn't provide any, the default kernel command string provided in CMDLINE will be used.
The command-line arguments provided by the boot loader will be appended to the default kernel command string.
Always use the default kernel command string, even if the boot loader passes other arguments to the kernel. This is useful if you cannot or don't want to change the command-line options your boot loader passes to the kernel.
Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM space since the text section of the kernel is not loaded from flash to RAM. Read-write sections, such as the data section and stack, are still copied to RAM. The XIP kernel is not compressed since it has to run directly from flash, so it will take more space to store it. The flash address used to link the kernel object files, and for storing it, is configuration dependent. Therefore, if you say Y here, you must know the proper physical address where to store the kernel image depending on your own flash memory usage. Also note that the make target becomes "make xipImage" rather than "make zImage" or "make Image". The final kernel binary to put in ROM memory will be arch/arm/boot/xipImage. If unsure, say N.
This is the physical address in your flash memory the kernel will be linked for and stored to. This address is dependent on your own flash usage.
kexec is a system call that implements the ability to shutdown your current kernel, and to start another kernel. It is like a reboot but it is independent of the system firmware. And like a reboot you can start any kernel with it, not just Linux. It is an ongoing process to be certain the hardware in a machine is properly shutdown, so do not be surprised if this code does not initially work for you. It may help to enable device hotplugging support.
Should the atags used to boot the kernel be exported in an "atags" file in procfs. Useful with kexec.
Generate crash dump after being started by kexec. This should be normally only set in special crash dump kernels which are loaded in the main kernel with kexec-tools into a specially reserved region and then later executed after a crash by kdump/kexec. The crash dump kernel must be compiled to a memory address not used by the main kernel For more details see Documentation/kdump/kdump.txt
ZRELADDR is the physical address where the decompressed kernel image will be placed. If AUTO_ZRELADDR is selected, the address will be determined at run-time by masking the current IP with 0xf8000000. This assumes the zImage being placed in the first 128MB from start of memory.
This enables the CPUfreq driver for i.MX CPUs.
This enables the CPUfreq driver for ARM Integrator CPUs. For details, take a look at <file:Documentation/cpu-freq>. If in doubt, say Y.
Internal configuration node for common cpufreq on Samsung SoC
This enables the CPUfreq driver for the Samsung S3C24XX family of CPUs. For details, take a look at <file:Documentation/cpu-freq>. If in doubt, say N.
Compile in support for changing the PLL frequency from the S3C24XX series CPUfreq driver. The PLL takes time to settle after a frequency change, so by default it is not enabled. This also means that the PLL tables for the selected CPU(s) will be built which may increase the size of the kernel image.
Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
Export status information via debugfs.
Say Y to include the NWFPE floating point emulator in the kernel. This is necessary to run most binaries. Linux does not currently support floating point hardware so you need to say Y here even if your machine has an FPA or floating point co-processor podule. You may say N here if you are going to load the Acorn FPEmulator early in the bootup.
Say Y to include 80-bit support in the kernel floating-point emulator. Otherwise, only 32 and 64-bit support is compiled in. Note that gcc does not generate 80-bit operations by default, so in most cases this option only enlarges the size of the floating point emulator without any good reason. You almost surely want to say N here.
Say Y here to include the FAST floating point emulator in the kernel. This is an experimental much faster emulator which now also has full precision for the mantissa. It does not support any exceptions. It is very simple, and approximately 3-6 times faster than NWFPE. It should be sufficient for most programs. It may be not suitable for scientific calculations, but you have to check this for yourself. If you do not feel you need a faster FP emulation you should better choose NWFPE.
Say Y to include VFP support code in the kernel. This is needed if your hardware includes a VFP unit. Please see <file:Documentation/arm/VFP/release-notes.txt> for release notes and additional status information. Say N if your target does not have VFP hardware.
Say Y to include support code for NEON, the ARMv7 Advanced SIMD Extension.
Say Y here to include the kernel code necessary if you want to run Acorn RISC OS/Arthur binaries under Linux. This code is still very experimental; if this sounds frightening, say N and sleep in peace. You can also say M here to compile this support as a module (which will be called arthur).